1512 results about "Data buffer" patented technology

The invention discloses a method for automatically drawing an OpenGL (Open Graphics Library) program by using Vulkan. The method comprises the following steps of: creating a context used by the Vulkan, initializing each module, processing an OpenGL instruction related to texture and data buffering, and managing storage of texture and data buffering resources in a video memory; a shader program used by the OpenGL is preprocessed into a format acceptable to Vulkan, and an OpenGL shader program instruction is created and destroyed; processing an OpenGL (Open Graphics Library) instruction related to frame buffering to generate structural body information required by Vulkan dynamic rendering; an OpenGL instruction of the sampler is also created; processing an OpenGL (Open Graphics Library) instruction for creating a vertex input format and managing a vertex data buffer area, and maintaining vertex input information, a vertex buffer area and an index buffer area required by Vulkan; and finally, drawing or calculating, distributing and calling Vulkan on the basis of all the instructions.

The invention discloses an equipment temperature adjusting method fusing a long short-term memory network, and particularly relates to the technical field of temperature control, which comprises the following steps: determining the deployment position of a sensor through thermal simulation, collecting multi-source heterogeneous data, dynamically adjusting the sampling frequency in combination with the temperature and the load current change rate, and adjusting the temperature of the sensor; after data preprocessing, an attention mechanism enhanced LSTM prediction model is constructed, a time sequence sample data set is divided according to equipment thermal response characteristics, training is carried out, and an optimal model is obtained through early stop mechanism optimization; predictive feedback double-closed-loop regulation and control is achieved based on the optimal model, outer loop PI control is combined with an integral separation mechanism to generate a basic control quantity, an inner loop outputs a correction quantity through fuzzification, reasoning and defuzzification, an actuator is driven after superposition, and safety linkage is triggered synchronously; constructing an incremental data buffer pool to screen effective samples, and adaptively updating model parameters by adopting a layered fine tuning strategy; the temperature regulation and control precision and the long-term self-adaptive capability are obviously improved, and the over-temperature risk of equipment is reduced.

The invention belongs to the technical field of data caching and batch synchronization, and discloses a management system data caching and batch synchronization method and system.The method comprises the steps that caching processing is conducted on pre-obtained data through a caching strategy based on a pre-constructed caching architecture, operation data are extracted through the cached data, and the operation data are stored in a database; carrying out local operation processing and operation type judgment by combining a transaction engine and an operation classifier; acquiring storage state data of the cache architecture in real time, performing synchronization strategy optimization on a preset synchronization strategy by using a decision tree algorithm, and performing batch synchronization processing in combination with a chained version number mechanism; and acquiring operation state data of the cache architecture, constructing a cache performance index system by using the operation state data, and performing data storage alarm processing by combining an autoregression integral moving average model and an association rule. According to the method, the high-frequency operation response speed is obviously optimized, the load of a back-end server is effectively reduced, and efficient utilization of hardware resources is realized.

The invention provides a cache architecture and method of an AXI interconnection module, electronic equipment and a storage medium, and relates to the technical field of storage, the cache architecture comprises an index cache region, a shared cache region and a shared cache access controller, the index cache region comprises an index entry list, and the shared cache region comprises an instruction cache region and a data cache region; each index cache region corresponds to one main device, the shared cache region corresponds to all the main devices, and the index entry list is used for recording index information of access transactions of the corresponding main devices; each index entry in the index entry list corresponds to one access transaction; and the shared cache access controller is used for storing instruction information corresponding to the access transaction in the instruction cache region based on the index information and storing data information corresponding to the access transaction in the data cache region. By applying the scheme of the invention, the utilization efficiency of on-chip resources can be improved on the basis of ensuring the transaction processing performance.

The invention relates to the field of equipment safety verification, in particular to a wifi router on-line upgrading safety verification method and a wifi router on-line upgrading safety verification system. A wifi router online upgrade security verification system comprises a firmware package construction module, a firmware package verification module and a guarantee activation module. According to the method, a firmware packet header protection logic closed loop is formed through an innovatively designed multi-order composite verification structural body and an anti-offset signature positioning framework; the system can detect the nanoscale tampering of an attacker to the length identification field in real time, cuts off the power supply of the flash memory controller and erases the data buffer area at the hardware fusing level response speed when verification fails, and compared with a traditional scheme, the response efficiency is improved.

The invention discloses a parallel processor dynamic resource allocation system and method based on reconfigurable hardware, and relates to the technical field of computer chips, and the system comprises a workload monitoring module which is responsible for monitoring the workload type and the resource demand of a task processed by a parallel processor in real time, and determining the task type and the resource demand by identifying the task type and the resource demand; a monitoring result is fed back to the resource allocation control module; the resource allocation control module is responsible for generating a corresponding resource allocation control signal based on feedback information of the workload monitoring module and dynamically configuring the reconfigurable hardware module; the reconfigurable hardware module is responsible for realizing efficient adaptation to diversified tasks through a plurality of reconfigurable units formed by programmable logic devices according to different working load dynamic reconfiguration functions and connection modes; and the data caching and transmission module is responsible for cross-module data circulation and global data storage. Different task requirements can be accurately adapted, and the resource utilization rate is improved.

The invention relates to an intelligent metering box monitoring method, system and device and a storage medium, and the method comprises the steps: continuously collecting the operation data of an intelligent metering box in an offline state of the intelligent metering box, carrying out the abnormal trend recognition of the operation data through combining with a pre-trained edge side abnormality recognition model, and obtaining a local judgment result; abnormal record data are generated according to the local judgment result, the abnormal record data are cached in a local storage unit, and the abnormal record data comprise fault types, timestamps and index values; generating a communication connection request signal under the condition that the communication connection condition is met, and controlling the communication channel to establish network connection according to the communication connection request signal; and after the communication response is received, collecting the network signal strength, and uploading the abnormal record data to a remote management platform based on the network signal strength. The intelligent metering box has the effect of improving the monitoring reliability of the intelligent metering box.

The invention relates to the technical field of audio control, and discloses a low-delay audio input switching method and system, a storage medium and equipment, and the method comprises the steps: carrying out the parallel pre-initialization of a plurality of pieces of audio input equipment, and building an independent parallel audio data cache for each piece of equipment; monitoring the state of each audio input device and the audio stream quality in real time, and judging whether switching is triggered or not based on a multi-factor decision model; after the switching decision is triggered, seamless audio data stream switching is executed, and format unification processing and cross fade-in and fade-out transition are included; a unified equipment operation interface is provided through the hardware abstraction layer, and system resources are optimized and managed; a delay sensing closed-loop control mechanism is constructed, processing delay of each link is monitored in real time, a caching strategy, a processing algorithm and resource allocation parameters are dynamically adjusted, self-adaptive balance of low delay and high tone quality is achieved, and through the method, quick and smooth switching of audio input equipment is achieved, delay is remarkably reduced, and real-time audio experience is improved.

The invention relates to the technical field of communication, and discloses a flow control method, electronic equipment and a storage medium, and the method comprises the steps: responding to data transmission of a target node, configuring a first-level cache of the target node, and configuring a data cache position corresponding to the target node as the first-level cache; under the condition that the data volume in the first-level cache reaches a preset back pressure threshold value, switching a data cache position corresponding to the target node to a second-level cache, and performing flow control on the target node; wherein the second-level cache is configured to be a shared cache of all nodes transmitting data to the local node. According to the invention, the problem of cache overflow caused by traffic burst of the switching network node can be solved.

The invention relates to the technical field of forest fire management, in particular to an integrated forest fire intelligent analysis method and system. The system comprises a background service system, a central intelligent analysis system and a mobile intelligent analysis system. The background service system is deployed in a cloud computing server cluster and is used for uniformly storing personnel information, fire scene information and geographic information data and realizing multi-source data fusion and authority management through a standardized API (Application Program Interface); the central intelligent analysis system is deployed in a high-performance computer, integrates a forest fire danger auxiliary decision-making model, a forest fire spreading trend prediction model, a force distribution dynamic display module and a collaborative plotting module, and supports fire spreading prediction and real-time decision-making instruction issuing based on multi-dimensional data such as weather, terrain and vegetation; the mobile intelligent analysis system realizes fire spreading trend analysis, mobile plotting and instruction receiving in an offline environment, supports offline data caching and calling in an emergency scene, and effectively improves forest fire emergency response efficiency and resource scheduling accuracy.

The invention discloses a multi-precision matrix calculation unit and a use method thereof, and relates to the technical field of integrated circuits, the multi-precision matrix calculation unit comprises a control logic unit, a cache module and a calculation array; wherein the control logic unit is used for configuring a computing array and controlling the cache module to read in and read out data; the cache module comprises three first cache sub-modules and one second cache sub-module; wherein the three first cache sub-modules are respectively used for caching a first to-be-processed matrix, a second to-be-processed matrix and a third to-be-processed matrix, and the second cache sub-module is used for caching a result matrix; and the calculation array is used for carrying out multiplication and addition operation on different types of to-be-processed matrixes to obtain a result matrix and writing the result matrix back to the cache module. The method can serve as a basic operation core for integrated processing of large-scale matrix multiplication and can also be integrated in processors such as RISC-V for matrix operation, universality is higher, and the method can adapt to fast and efficient calculation scenes.

The embodiment of the invention provides a model reasoning data caching method and device for a caching system and a storage medium, and the method comprises the steps: configuring a first virtual address mapped to a high-performance memory of the caching system for a data caching pool, and generating a first reasoning data according to the data size of the first reasoning data generated by a target reasoning model; determining a target memory space of the high-performance memory mapped by the first virtual address, and enabling the data volume of the first reasoning data to be in direct proportion to the memory space volume of the target memory space mapped by the first virtual address, thereby creating a dynamic data buffer pool of the target reasoning model, and then caching the first reasoning data based on the target memory space corresponding to the dynamic data buffer pool, thereby realizing on-demand allocation of the high-performance memory in the cache system, and improving the utilization efficiency and the use flexibility of the high-performance memory in the cache system.

Caching techniques can include: receiving, from a host, a read I / O operation requesting to read current content of a logical address; determining whether a data cache includes a data cache entry corresponding to the logical address; responsive to determining the data cache includes the data cache entry corresponding to the logical address, performing data cache hit processing to service the read I / O operation using the data cache entry; responsive to determining the data cache does not include the data cache entry corresponding to the logical address, performing data cache miss processing including: determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing mapping cache hit processing to service the read I / O operation using the descriptor of the mapping cache.

The invention belongs to the field of integrated circuits and computer system structures, and provides a caching method and system for a memory access unit of a superscalar processor, and the method comprises the steps: receiving a plurality of memory access instructions in the same period, and determining a corresponding Bank in a to-be-accessed cache through the memory access instructions; after the memory access instruction obtains a cache access permission, if cache line missing occurs, generating a missing request, merging all the missing requests, and performing parallel prefetching training on the merged missing requests by utilizing a mode of fusing a constant step length prefetching mode and a complex step length prefetching mode to obtain a prefetching request and a prefetching cache address corresponding to the prefetching request; requesting a missing cache line from the first-level cache to the second-level cache based on the missing queue, and writing the missing cache line back to the cache line of the corresponding data cache in the first-level cache; and storing the bus consistency request by using the sniffing queue, judging whether the data in the multi-core cache are consistent or not by using the consistency request, and performing consistency modification according to a judgment result. The cache hit rate and the bandwidth utilization rate are improved.

The invention relates to the technical field of embedded systems, and provides a high-speed data communication method and system based on synchronous triggering and parallel transmission. The method comprises the following steps: configuring a master timer, a plurality of slave timers and a corresponding number of DMA (Direct Memory Access) channels in an MCU (Microprogrammed Control Unit), and setting a data buffer area corresponding to each DMA channel; configuring a main timer to generate a synchronous trigger signal with a target sampling rate, and driving all slave timers to generate synchronous update events with sequentially delayed phases as parallel DMA trigger signals; the signals are utilized to control each DMA channel to alternately transmit external equipment data to a corresponding area of the buffer area in parallel; and finally, performing time sequence recombination on the multi-region data according to the phase sequence of the update event, and restoring a complete sampling sequence. The rate bottleneck of a single DMA channel is broken through, the aggregation bandwidth of multiple DMA channels is utilized, high-sampling-rate data collection far exceeding the single DMA limit is achieved under limited hardware resources, and the system data throughput rate is effectively improved.

The invention discloses a cross-border e-commerce abnormal transaction behavior risk prediction method based on a graph neural network, and the method comprises the steps: synchronously collecting multi-source data of a cross-border e-commerce platform, and writing the multi-source data into a data buffer region according to a unified event timestamp; mapping the multi-source data into a heterogeneous dynamic transaction graph; in the current time window, performing structure comparison on the historical transaction graph and the heterogeneous dynamic transaction graph to generate a structure difference sub-graph, and performing normalization processing to obtain a residual graph; splicing the heterogeneous dynamic transaction graph and the residual graph, inputting the spliced graph into a time sequence graph neural network, obtaining a risk embedding vector of a target transaction sub-graph, and calculating an abnormal score through a mapping function; and comparing the abnormal score with a first threshold value, outputting a risk level of the corresponding transaction and triggering early warning. The cross-border e-commerce abnormal transaction behavior risk can be quickly and accurately identified and predicted, the active identification and real-time early warning of the abnormal transaction risk can be realized, and the real-time performance and accuracy of the risk management of the cross-border e-commerce platform can be greatly improved.

The invention relates to the technical field of cloud computing, and particularly provides a data cache prefetching method and device, a storage medium and a program product. According to the method, file access characteristics representing file access preferences of a user are obtained based on historical access data of the user, a target file meeting a cache prefetching strategy is determined based on the file access characteristics, and the target file is cached and prefetched. By dynamically analyzing the historical access data of the user, the system can adjust the cache content in real time, actively load the data possibly required by the user and ensure that the high-frequency access data is always available, and the mechanism not only improves the data access speed, but also remarkably reduces the influence caused by network delay.

The invention belongs to the field of many-core processor design, and particularly relates to a many-core processor system based on a data flow framework and a task scheduling method.The system comprises a system control node, computing nodes and storage nodes which are connected through an on-chip internet, and each storage node and at least one computing node form a computing cluster; the system control node sends an instruction and data to the storage node through the on-chip internet, and the storage node distributes the data to the computing nodes in the computing cluster; an initialization unit of the computing node monitors a data buffer area of the on-chip internet through a state register, data are moved to a buffer unit, and initialization of a computing core is completed; the scheduling unit is responsible for scheduling a task queue, and transferring data required by a next task to the cache unit in advance through the DMA unit to realize parallel calculation and data transferring; the computing unit executes the computing task, and the data directly flows among different computing nodes, so that the memory access requirement is reduced, and the computing resource utilization rate is improved.

The invention relates to a processor and a kernel synchronization method for the processor. Based on the method and the device, the query request initiated by the plurality of processing cores in the processor for the same specified data can be selectively forwarded by the route, so that the occupation of the query request on the on-chip bandwidth of the processor can be reduced, and the query response occupying the on-chip bandwidth of the processor can be indirectly reduced. Or, the data cache unit where the specified data is located can reduce the generation of the query response for promoting the processing kernel to continue to initiate the query request, so that not only can the occupation of the query response to the on-chip bandwidth of the processor be reduced, but also the query request occupying the on-chip bandwidth of the processor can be indirectly reduced. Therefore, the occupation of the query request and the query response for realizing kernel synchronization on the on-chip bandwidth of the processor can be inhibited from the routing forwarding source of the query request or the generation source of the query response, so that the on-chip bandwidth occupied by the kernel synchronization in the processor can be reduced.

The invention provides a data cache optimization method, device and equipment for a vehicle-specification MCU and a storage medium, and the method comprises the steps: building a multi-target cache decision through predicting the future data access probability distribution, and giving consideration to the real-time performance and the memory utilization rate. A cache is divided into logic partitions with different priorities, and the sizes of the partitions are dynamically adjusted, so that a self-adaptive cache layout is formed. In combination with access probability distribution and a partitioning strategy, a dynamic pre-fetching threshold value is set, data pre-fetching is executed, and elimination and updating are performed in a task execution period, so that the caching efficiency and stability of a vehicle gauge MCU in a high-temperature and strong-vibration environment are improved, and the method is suitable for a vehicle-mounted control system with strict requirements on safety and performance.

The present application relates to the technical field of wireless communications, and discloses a resource allocation method, apparatus and device, a storage medium and a product, comprising: receiving a scheduling request signaling sent by a user equipment, and determining a signaling interaction time between the user equipment and a base station; sending an initial allocation signaling to the user equipment based on the scheduling request signaling and the signaling interaction time; determining target cache data according to the data cache state and a historical data cache state reported by the user equipment last time; and allocating uplink resources to the user equipment based on the target cache data, and sending a target allocation signaling corresponding to the target cache data to the user equipment. According to the method, multiple cache time slots are allocated to the user according to the signaling interaction time between the user and the base station, so that multi-thread uplink resource allocation is initiated, the user equipment can instantly report a data cache state to a satellite, and user data can be more instantly allocated with resources and transmitted.

The invention discloses a data cache management method and system based on big data, and relates to the technical field of data cache management, and the method comprises the steps: collecting access mode metadata, constructing a data cache state space and an action space, and screening an effective action set of data cache; on the basis of the state space, calculating a context feature weight, and constructing a CO-IAM model to predict a data caching action; performing data caching action implementation based on a CO-IAM model prediction result; by constructing a state space and an action space of data caching, introducing a CO-IAM model, performing precise modeling and dynamic adjustment based on context feature weight, generating an invalid action mask, filtering useless caching actions, optimizing a caching hit rate and access delay, and improving the performance of the whole caching system.

The invention provides a UCIe-based flow control method, a storage medium and an artificial intelligence chip. The flow control method comprises the following steps: reading a plurality of credit value data buffer depths and a plurality of security reserved data buffer depths corresponding to a plurality of virtual channels through a first core grain; reading a plurality of current receiving end exclusive data buffer depths of the plurality of receiving end exclusive data buffers and a plurality of current receiving end shared data buffer depths of the receiving end shared data buffer through the first core grain; updating a plurality of credit values corresponding to the plurality of virtual channels by the plurality of current receiving end dedicated data buffer depths and the plurality of current receiving end shared data buffer depths; and outputting the plurality of credit values to the second core particle through the first core particle. According to the flow control method, the credit value can be effectively updated.

The invention discloses a database access parameter real-time cooperative processing method and device based on multi-level cache, and belongs to the technical field of computer data caching. The method comprises the steps that a version number management table is configured; establishing a four-level cache architecture of a transaction-level cache layer, a process-level cache layer, a distributed cache layer and a database cache layer; receiving a transaction request, creating a transaction level cache layer and loading current version number information; comparing the version number in the transaction level cache layer with the version number in the process level cache layer; according to the version number comparison result, obtaining parameter data from the corresponding cache level according to a preset cache access priority strategy; and when the parameter change is detected, updating the corresponding version number in the version number management table, and updating the cache layer data as required. According to the method, real-time global effectiveness of parameter change is realized, parameter consistency of in-transit transaction is guaranteed, system processing performance and throughput are improved, system reliability and fault-tolerant capability are enhanced, and system resource utilization rate is optimized.

The invention relates to the technical field of artificial intelligence chips and storage management, in particular to a cache line replacement method and device, a chip and electronic equipment. The method is applied to a chip comprising a data cache, the data cache comprises N cache lines in which data are stored, an access path corresponding to each cache line is managed based on a binary tree structure comprising N-1 nodes in a PLRU algorithm, and a data replacement instruction is responded, obtaining a path status bit from a root node to a leaf node on an access path corresponding to each cache line; for a specified cache line, calculating a PLRU path value according to the path status bit, and calculating a replacement score in combination with the importance level and the corresponding weight of the stored data; determining a replaceable cache line according to the replacement score; and storing the to-be-cached data and the importance level thereof into a replaceable cache line to replace the original data and the original level. Therefore, the cache line replacement priority is evaluated by combining the PLRU path value and the importance level of the stored data, the cache hit rate is effectively improved, and the system performance is optimized.

The invention discloses an asynchronous multi-granularity memory access control method in a microprocessor, an asynchronous circuit and a memory access module, the memory access control method adopts asynchronous clock-free control, introduces a multi-granularity memory access control mechanism, and divides the memory access granularity into two classes of multi-word memory access and non-multi-word memory access for processing. According to the method, the access path and the cache strategy can be flexibly adjusted according to different access granularities, redundant operation during access is reduced, and the access efficiency is greatly improved. The asynchronous circuit is a delay-limited asynchronous circuit and comprises an asynchronous controller and an asynchronous micro-pipeline structure based on a'sending-relay-receiving 'structure. The memory access module based on the asynchronous circuit comprises a memory access state management module, a data access updating module, an instruction / data cache and peripheral interaction interface, and a data interaction interface between the memory access module and the write-back module. According to the invention, lower dynamic power consumption and higher energy efficiency ratio are realized, and high efficiency and low delay are realized under large data volume operation.

The invention relates to a data processing unit, a distributed system and a chip, and the method comprises the steps: a first RDMA engine receives a first network message sent by a previous network node, analyzes the first network message to obtain first data, writes the first data into a first data buffer region, and reports a first receiving notification to a first processor in a reduction stage; the first processor reads the first data from the first data buffer area according to the first receiving notification, reads the second data from the local GPU memory, performs reduction calculation based on the first data and the second data to obtain third data, writes the third data into the first data buffer area, and issues a first sending notification to the first RDMA engine; the first RDMA engine reads third data from the first data buffer area according to the first sending notification, generates a second network message according to the third data, and sends the second network message to the next network node; according to the invention, the computing power of the network node and the utilization rate of the bandwidth can be improved.

The invention belongs to the technical field of medical treatment, and discloses a wearable intelligent method and device for monitoring the mental health of community old people, and the method comprises the steps: collecting the physiological indexes of the community old people in real time through an intelligent chest card, and achieving the dynamic collection of multi-dimensional data; data are transmitted to the cloud platform through Bluetooth or Wi-Fi, the equipment supports a data caching mechanism, and key data are temporarily stored when connection is abnormal; a dynamic evaluation model is constructed based on AI learning, and a multi-factor decision tree model and a natural language processing NLP algorithm are combined; a group psychological health trend and an environment risk thermodynamic diagram are presented in real time through a chest card APP, main factors influencing psychological health of the old are analyzed, and community managers are assisted in making an intervention plan. By making and applying the community old people mental health monitoring and early warning model, a unified mental health assessment system is provided for old people in different states, the applicability, universality and compliance of mental assessment are improved, home rehabilitation is achieved, and the overall medical cost is reduced.

Caching techniques can include: receiving, from a host, a read I / O operation requesting to read current content of a logical address; determining whether a data cache includes a data cache entry corresponding to the logical address; responsive to determining the data cache includes the data cache entry corresponding to the logical address, performing data cache hit processing to service the read I / O operation using the data cache entry; responsive to determining the data cache does not include the data cache entry corresponding to the logical address, performing data cache miss processing including: determining whether a mapping cache includes a descriptor corresponding to the logical address; and responsive to determining the mapping cache includes the descriptor corresponding to the logical address, performing mapping cache hit processing to service the read I / O operation using the descriptor of the mapping cache.

The invention provides a universal serial bus (USB) 2.0 host speed reduction bridge based on bidirectional protocol handshake and a prototype verification or hardware simulation acceleration platform, which are characterized in that a slow-speed side module runs at a slow clock frequency, is responsible for realizing a protocol layer of a USB protocol and a physical link layer function of the USB protocol, and communicates with a USB2.0 host controller in a chip design (DUT) to be tested; the original speed side module works under the original clock frequency, logic of a protocol layer of a USB protocol and a physical link layer of the USB protocol is achieved, communication with an external real USB2.0 slave end device is achieved through a USB2.0 PHY, data caching and synchronization are achieved through a data caching RAM, and the bridge control module overall plans the whole situation and accurately regulates and controls independent handshake of the USB2.0 protocol layers on the two sides under the original clock frequency. Through bidirectional protocol handshake on the two sides of the speed reduction bridge, data communication between a low-speed to-be-tested chip design (DUT) in a chip prototype verification platform and external standard-speed real USB slave equipment is achieved through the speed reduction bridge.