135 results about "Write buffer" patented technology

The invention discloses a storage and calculation separation key value storage delay optimization method based on prediction driving, and aims to solve the problems of performance bottleneck and high tail delay caused by passive management and high network delay in a key value storage system in a storage and calculation separation scene. The method comprises the following steps: time load prediction: deploying a time sequence prediction model at a client, and predicting a future read-write request based on a historical access sequence; active cache prefetching: according to the predicted read request, actively preloading hotspot data from a server side to a client side for caching so as to improve the cache hit rate and hide network delay; active write-in optimization: according to the predicted write request, executing maintenance at a server side through predictive pre-insertion and active node splitting, and moving high index structure adjustment overhead out of a key request path to eliminate a write delay peak; and structure sensing batch synchronization: pre-fragmenting a local write buffer by using a server index top layer model of a client cache, and combining multiple independent remote insertion operations into one efficient batch update to reduce data synchronization overhead. Compared with an existing passive management system, the characteristics of model prediction and active cooperation are fully utilized, and the average delay and the tail delay of the system are reduced.

Methods, systems, and devices for configurable logical-to-physical table storage extension at a memory system are described. The described techniques provide for a memory system to share host write data and logical-to-physical (L2P) extension data within a write buffer. If the memory system triggers L2P extension, the memory system may compare a quantity of available buffer units with an upper bound of a range of buffer units configured for L2P extension. For example, if enough buffer units are available for a full L2P extension, the memory system may allocate a full L2P extension, and if there are not enough buffer units available, the memory system may allocate a partial L2P extension. If the memory system allocates a partial L2P extension, the memory system may begin flushing write data stored to the buffer and may allocate newly available buffer units for the L2P extension.

Methods, systems, and devices for write buffer management for a memory system are described. The described techniques provide for a memory system to receive data associated with multiple applications being executed concurrently and store the data to portions of a write buffer according to whether the data is sequential or non-sequential. For example, the memory system may receive sequential data for a first application between receiving non-sequential data for one or more second applications, and may partition a write buffer such that the sequential data is stored (e.g., sequentially) within a portion the write buffer and the non-sequential data is stored within a different portion of the write buffer. The memory system may flush portions of the write buffer to multiple-level memory cells once a portion is full, thereby storing sequential data to sequential physical addresses within the memory system.

An improved flushing technique controls a draining speed of data from a temporary storage tier to a backend storage tier of a node so that draining logic does not overwhelm an input / output (I / O) workload that is serviced by the storage tiers. Illustratively, the temporary storage tier is a persistent write buffer embodied as an operations log (oplog) and the backend storage tier is persistent physical disk storage embodied as an extent store. The technique improves an oplog flushing algorithm by enabling control of the oplog draining speed (rate) to provide consistent performance when the I / O workload (e.g., a primary ingest I / O stream) is serviced by the extent store and / or oplog during one or more states (e.g., static inertia state, idle state and rebuild state) of the oplog.

Examples of the present application provide memory systems, methods of operating thereof, and storage mediums. An example memory system includes at least one memory device and a memory controller; the memory controller is coupled with both a host and the memory device and includes a write buffer and a control section coupled with the write buffer; the control section is configured to: in response to upcoming execution of an erase event of a block in the memory device, configure a portion of an idle storage space of the memory controller as a newly-added storage space of the write buffer; write data received from the host to the newly-added storage space of the write buffer in response to execution of the erase event; and release the newly-added storage space of the write buffer in response to completion of the erase event.

The invention discloses a lightweight rapid serialization method for high-throughput scientific data, which comprises the following steps of: 1) defining a uniform data model for each line station, including a common header field, a state specific field and a line station exclusive field; the common header field records the same information contained in each line station, the state specific field describes the data generation state of the line station, and the line station exclusive field describes the customization attribute contained in the data stream in different data generation states; 2) each line station processes the generated data according to the data model, generates a data stream model and serializes the data stream model, and a generator calculates the initial offset and the number of occupied bytes of each field in a binary stream according to the type, length and sequence of the fields; for a pre-distributed continuous buffer area, generating field write-in logic positioned according to offset, converting each field value into a byte stream according to the data type of the field value, and writing the byte stream into a corresponding position of the buffer area; and splicing the code of the binary data of each field to obtain serialized data.

This invention discloses an edge-side out-of-order write reordering method for consumer-grade partitioned storage, belonging to the field of computer storage systems and flash memory management technology. Addressing the problem of degraded multi-threaded parallel write performance in consumer-grade partitioned storage due to kernel-forced sequential writes, and the insufficient capacity of the edge-side SRAM write buffer to meet large-scale out-of-order reordering requirements, this invention proposes a dynamic processing method with a two-layer reordering architecture. By dividing the high-performance SLC flash memory region in the device into page-level SLC and zone-level SLC as an extended write buffer, when processing write requests, the continuity and temperature label of the data in the SRAM buffer are judged; if the data is continuous and hot data, a direct flushing strategy is executed to the zone-level SLC; if out-of-order data occurs and the buffer is insufficient, a degradation strategy is executed to temporarily store the data in the page-level SLC; and continuity is dynamically restored when subsequent data is supplemented. This invention overcomes the limitations of small edge-side caches while releasing the parallel write potential of the device, significantly improving multi-threaded write IOPS.

According to some embodiments, a replication tool may arrange for a copy of original records from a data source to be written into a read-only replica in an application stack. Write buffer logic in the application stack may determine that information in an original record of the read-only replica has been locally updated at the application stack by application logic. The write buffer logic may then automatically create an updated version of the original record in a write buffer of the application stack based on the local update by the application logic. Moreover, prioritization logic may automatically determine whether information in the original record or the updated record will be accessed.

The application provides a memory particle packaging method and system based on a HIPI protocol, which packages memory particles through the HIPI protocol, and the memory particle packaging method comprises the following steps: receiving all signals sent by a DRAMC through a DRAM interface module, analyzing the signals through semantics, and then packaging the signals to a HIPI channel; synchronizing the bandwidth of the HIPI and the DRAM particle through a read-write buffer module to complete the HIPI packaging; generating a DQS signal and a Clock signal of the DRAM particle based on the access protocol of the DRAM through a DRAM clock signal generation module; and writing data into the DRAM particle or reading data out of the DRAM based on the DQS signal and the Clock signal. In the memory particle packaging process, the DRAMC and the memory particle do not need any modification, and the application is friendly to the development of hardware manufacturers.

Various aspects relate to a memory module including: a memory interface; a storage device for persistently storing data; a non-volatile memory device providing a memory storage for persistently storing data and providing a write buffer configured to receive, via the memory interface, and to store corresponding data to be written to the memory module; and a memory controller configured to write the corresponding data selectively from the write buffer to the storage device or to the memory storage.

The present application provides a memory management method and a storage device. The method comprises: obtaining temperature information of the storage device; obtaining write buffer quota information according to a difference between the temperature information and target temperature information; and adjusting a write buffer capacity of the storage device according to the write buffer quota information. Thus, a good balance between performance maintenance and temperature regulation of the storage device can be achieved.

The invention discloses an abnormal data reporting method and device, electronic equipment and a storage medium, and relates to the technical field of integrated circuits, and the method comprises the following steps: obtaining a first abnormal data group packet corresponding to an abnormal event occurring in an integrated circuit, and storing the first abnormal data group packet into a queue; detecting whether a second abnormal data group packet exists in the queue or not; if it is detected that the second abnormal data group packet exists in the queue, performing aggregation processing on the first abnormal data group packet and the second abnormal data group packet to obtain a third abnormal data group packet; when it is determined that the third abnormal data group packet obtains the priority arbitration right, writing the third abnormal data group into a buffer area; and generating and reporting an interrupt signal to a processor. According to the method and the device, the problems that the area of an integrated circuit is increased and the cost is relatively high due to the fact that the abnormal data report needs to use more register resources and the resource utilization rate is low, or a special data path and relatively large memory resources are needed can be solved.

The application relates to the technical field of big data analysis, and discloses an OT / IT heterogeneous data unified access and standardized conversion method, which comprises the following steps: acquiring a data stream and extracting service load data and metadata therefrom; converting the metadata into fixed-length hash features by using hash operation, stripping the metadata, and encapsulating the service load data and the hash features; dividing a plurality of continuous memory buffer areas corresponding to a bit mask base number of a memory space, and extracting feature offsets of the hash features by using the bit mask; sequentially appending and writing data into the buffer areas according to receiving time; and sequentially writing the data into a storage medium in batches when the memory occupation reaches a preset threshold. The application converts the device logical owner relationship into the continuity of the medium physical block by using the hash routing, suppresses write amplification, avoids system lagging caused by fragment consolidation, and guarantees the continuous and smooth data collection of a data surge.

A storage system includes a first storage device including a first write buffer and a first nonvolatile memory device, and a second storage device including a second write buffer and a second nonvolatile memory device. The first storage device is configured to, in response to a determination that a use buffer size of the first write buffer is greater than a first reference buffer size when the first storage device receives write data from a host, transfer the write data to the second storage device, and the second storage device is configured to store the write data.

The invention discloses a message transmission method and device, and relates to the technical field of communication. The method comprises the steps that an application processor core sends a shared memory creating request to a real-time processor core through Msgbox, and a Ping buffer area and a Pong buffer area of DMABuffer are created in a shared memory; the real-time processor core responds to a shared memory creating request of the application processor core, writes data into a current write buffer area of the DMABuffer, and notifies the real-time processor core through Msgbox; and the application processor core reads the data in the current read buffer area of the DMABuffer, and informs the real-time processor core to perform buffer area switching when reading is completed. The technical problem of low cross-core communication efficiency in the prior art is solved.

This application discloses a method and apparatus for writing buffer data in a memory management unit, relating to the field of chip verification technology, and is invented to shorten verification time and improve verification efficiency. The method includes: traversing a page table to obtain the mapping relationship between virtual addresses and physical addresses recorded in the page table; filtering the mapping relationship according to a predetermined strategy to obtain a target mapping relationship; converting the target mapping relationship into a predetermined format to obtain a target mapping relationship; and writing the predetermined format target mapping relationship into a substitution bypass buffer in the memory management unit through a backdoor access function. This application is applicable to verification related to substitution bypass buffers.

The invention discloses a reinforcement learning-based data flow task scheduling and resource adaptive allocation method, which comprises the following steps of: acquiring data to form an environment state vector; forming an action set based on the state vectors; determining a return interval and dispersing the return interval into a plurality of atomic support points to form a discrete return support set; the method comprises the following steps: constructing a decision network, and carrying out distributed modeling and training by adopting a Category DQN; preferentially sampling to form batches according to the time delay based on an experience playback buffer area in training, and weighting delay distribution and energy consumption distribution to synthesize a comprehensive return during action selection so as to determine an optimal action; calculating an expected return and selecting an action according to the distribution during scheduling execution; and generating rewards after execution, writing the rewards into the buffer area, and continuously updating the decision network. According to the method, multi-target distribution modeling and delay priority experience playback are introduced, and delay energy consumption consideration and resource adaptive scheduling of enterprise data flow tasks are realized.

A data transfer controller connected to a first digital interface of a computer system receives an instruction to prepare a plurality of non-contiguous data elements in a memory of the computer system for transfer to a peripheral device connected to the first digital interface. The data elements are read from the memory of the computer system via a plurality of gather transactions on a second digital interface. The second digital interface is connected to the data transfer controller and the memory. The second digital interface allows for use of a subset of overhead data of the first digital interface for the gather transactions. The data elements are written into a contiguous data block in a buffer. An indication that the contiguous data block is available for transfer from the buffer to the peripheral device via the first digital interface is provided to the peripheral device via the first digital interface.

In a flash memory device, portions of a write buffer may be merged into a user space logical unit based on a measurement of write buffer usage. In a Universal Flash Storage (UFS) device configured with the WriteBooster feature, the write buffer may be a WriteBooster buffer. When it is determined that a user space logical unit has become full, then the write buffer usage may be determined. Portions of the write buffer that are least used or have the longest remaining lifetime may be preferentially merged into the user space logical unit.

A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device and configured to receive a notification from the flash memory device that a performance threshold register value has been exceeded while the flash memory device is configured to use a shared write buffer. The HCI is also configured to, in response to receiving the notification, perform a remedial action that includes reassigning a portion of a first logical unit (LU).

The present invention proposes an out-of-order speculative execution emission queue and electronic device, comprising a write buffer, an overflow area, a main entry area, and a first selector. The write buffer, overflow area, and main entry area are all connected to the first selector, and the write buffer and overflow area are all connected to the main entry area, and the write buffer is also connected to the overflow area. After providing a first type of instruction to the first selector, or when the first direct transmission condition is not met, if the number of valid instructions remaining in the write buffer is greater than or equal to 1, the write buffer is used to send the valid instructions therein to the overflow area and / or the main entry area according to a preset priority rule. The emission queue is divided into three areas: the write buffer, the overflow area, and the main entry area. Each area only needs to find the corresponding instruction as output according to the instruction age, which greatly reduces the logical depth of the entire emission queue age matrix, thereby reducing the difficulty of timing convergence of the emission queue.

The present application relates to dynamic L2P caches. In some examples, methods, systems, and machine-readable media are disclosed for dynamically adjusting the size of an L2P cache in a memory device in response to observed operating conditions. The L2P cache can borrow memory space from donor memory locations, such as read or write buffers. For example, if the system observes a high number of read requests, the system can increase the size of the L2P cache at the expense of the write buffer (which can be reduced). Similarly, if the system observes a high number of write requests, the system can increase the size of the L2P cache at the expense of the read buffer (which can be reduced).

A storage device may set a write buffer including one or more of a plurality of first type memory blocks. And the storage device may determine whether a threshold condition is satisfied when a power off request is received, and add one or more target memory blocks selected from among a plurality of second type memory blocks to the write buffer when it is determined that the threshold condition is satisfied.

The present teaching relates to method, system, medium, and implementations for LED display. A first signal is received that signals a timing for a next data transfer. In response to the first signal, a bit-based image block stored in a memory is transferred, via a bus connected thereto, to one of a pair of alternate buffers pointed to by a write buffer pointer, which is subsequently toggled to point to another of the pair of alternate buffers. A second signal is received that signals a timing for refreshing the LED display. In response to the second signal, the bit-based image block is retrieved from the one of the pair of alternate buffers pointed to by a read buffer pointer, which is then toggled to point to the other of the pair of alternate buffers. The lights of the LED display are then refreshed in accordance with control signals generated based on the bit-based image block.

The invention discloses an audio writing method, device and equipment and a computer readable storage medium, and is applied to the field of intelligent automobiles and the technical field of audio processing. According to the method, the write-in permission of the corresponding thread is released after the first write-in request is received, so that the time of occupying the write-in permission by a single thread is shortened. And the sub-thread is created to write the audio data into the buffer area, so that the audio data can be written into the buffer area in the same time period, and the first writing request of the audio data sent by the audio application module through the thread is received, that is, the data volume of the audio data written in unit time is increased, and the writing efficiency is accelerated; and the phenomena of sound lagging and interruption caused by insufficient audio data volume in the buffer area are avoided.

A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device (FMD). The HCI is configured to obtain an indication that a size of a particular write buffer (WB) of the FMD is to increase. The FMD includes a plurality of memory resources including a plurality of logical units (LUs) and at least a particular WB. The HCI is also configured to select a particular memory resource for write buffer reallocation based at least in part on a particular usage metric for the particular memory resource.

An operation method of a universal flash storage (UFS) host configured to control a UFS device includes configuring a turbo write buffer of the UFS device; sending a first query request UFS protocol information unit (UPIU) including reconfiguration information about the turbo write buffer to the UFS device, during driving the UFS device; and receiving a first response UPIU associated with the first query request UPIU from the UFS device, wherein, the first query request UPIU is a request that causes a size of the turbo write buffer of the UFS device to be changed from a first size to a second size different from the first size.

The invention discloses a QSPI Flash controller based on an AXI bus interface, which is characterized by comprising an APB register control module, an AXI4 protocol controller module, a read-write buffer control module, a QSPI Flash control module and a QSPI Flash PHY chip, the APB register control module is used for receiving a Flash reading command; the QSPI Flash control module is used for carrying data at a specified position in an external QSPI Flash PHY (Physical Layer) chip to the read-write buffer control module when the APB register control module receives a Flash reading command; and the AXI4 protocol controller module is used for sending the data from the read-write buffer control module to the AXI bus. A standard IP is formed and can be conveniently integrated in a system on chip (SOC) with an AXI bus.

This application relates to the field of HVAC equipment control technology, and discloses a multi-protocol compatibility and edge computing method for HVAC equipment digital controllers. The method includes: parsing protocol bytecode to extract spatiotemporal metadata and establishing an instruction distribution table; executing instruction parsing data, calculating weights based on time consumption deviations and updating status words; filtering and writing to a buffer according to weights, or generating loss alarms by counting the number of discards; calculating the rolling variance representing fluctuations using a recursive algorithm based on an effective dataset; determining the trigger freeze signal based on comprehensive parameters, locking the buffer, and generating a fault snapshot. This invention achieves decoupling between the device communication protocol and the controller's underlying firmware by loading protocol bytecode containing spatiotemporal metadata and using a virtual machine engine for interpretation and execution. This allows the edge controller to adapt to HVAC equipment with different physical layer response characteristics and timing requirements without modifying the underlying code or recompiling the firmware, only by updating the protocol bytecode file.

Methods, systems, and devices for single level cell write buffer extension control are described. A host device may indicate a delay to be observed between write operations to a memory system. The memory system may perform random read operations or read operations for garbage collection during these delays, which allow the memory system to allocate space for a write buffer, such as a single-level cell (SLC) write buffer, even when performing a large quantity of write commands as part of a sequential write command. Additionally, by allocating space for the write buffer, the memory system may be able to keep writing to memory cells in accordance with the first write operation type, such as an SLC type, for longer periods of time, which may improve the write speeds and decrease an overall latency associated with sequential write operations.