30 results about "Write buffer" patented technology

Examples of the present application provide memory systems, methods of operating thereof, and storage mediums. An example memory system includes at least one memory device and a memory controller; the memory controller is coupled with both a host and the memory device and includes a write buffer and a control section coupled with the write buffer; the control section is configured to: in response to upcoming execution of an erase event of a block in the memory device, configure a portion of an idle storage space of the memory controller as a newly-added storage space of the write buffer; write data received from the host to the newly-added storage space of the write buffer in response to execution of the erase event; and release the newly-added storage space of the write buffer in response to completion of the erase event.

This invention discloses an edge-side out-of-order write reordering method for consumer-grade partitioned storage, belonging to the field of computer storage systems and flash memory management technology. Addressing the problem of degraded multi-threaded parallel write performance in consumer-grade partitioned storage due to kernel-forced sequential writes, and the insufficient capacity of the edge-side SRAM write buffer to meet large-scale out-of-order reordering requirements, this invention proposes a dynamic processing method with a two-layer reordering architecture. By dividing the high-performance SLC flash memory region in the device into page-level SLC and zone-level SLC as an extended write buffer, when processing write requests, the continuity and temperature label of the data in the SRAM buffer are judged; if the data is continuous and hot data, a direct flushing strategy is executed to the zone-level SLC; if out-of-order data occurs and the buffer is insufficient, a degradation strategy is executed to temporarily store the data in the page-level SLC; and continuity is dynamically restored when subsequent data is supplemented. This invention overcomes the limitations of small edge-side caches while releasing the parallel write potential of the device, significantly improving multi-threaded write IOPS.

Various aspects relate to a memory module including: a memory interface; a storage device for persistently storing data; a non-volatile memory device providing a memory storage for persistently storing data and providing a write buffer configured to receive, via the memory interface, and to store corresponding data to be written to the memory module; and a memory controller configured to write the corresponding data selectively from the write buffer to the storage device or to the memory storage.

The present application provides a memory management method and a storage device. The method comprises: obtaining temperature information of the storage device; obtaining write buffer quota information according to a difference between the temperature information and target temperature information; and adjusting a write buffer capacity of the storage device according to the write buffer quota information. Thus, a good balance between performance maintenance and temperature regulation of the storage device can be achieved.

This application discloses a method and apparatus for writing buffer data in a memory management unit, relating to the field of chip verification technology, and is invented to shorten verification time and improve verification efficiency. The method includes: traversing a page table to obtain the mapping relationship between virtual addresses and physical addresses recorded in the page table; filtering the mapping relationship according to a predetermined strategy to obtain a target mapping relationship; converting the target mapping relationship into a predetermined format to obtain a target mapping relationship; and writing the predetermined format target mapping relationship into a substitution bypass buffer in the memory management unit through a backdoor access function. This application is applicable to verification related to substitution bypass buffers.

A data transfer controller connected to a first digital interface of a computer system receives an instruction to prepare a plurality of non-contiguous data elements in a memory of the computer system for transfer to a peripheral device connected to the first digital interface. The data elements are read from the memory of the computer system via a plurality of gather transactions on a second digital interface. The second digital interface is connected to the data transfer controller and the memory. The second digital interface allows for use of a subset of overhead data of the first digital interface for the gather transactions. The data elements are written into a contiguous data block in a buffer. An indication that the contiguous data block is available for transfer from the buffer to the peripheral device via the first digital interface is provided to the peripheral device via the first digital interface.

This application relates to the field of HVAC equipment control technology, and discloses a multi-protocol compatibility and edge computing method for HVAC equipment digital controllers. The method includes: parsing protocol bytecode to extract spatiotemporal metadata and establishing an instruction distribution table; executing instruction parsing data, calculating weights based on time consumption deviations and updating status words; filtering and writing to a buffer according to weights, or generating loss alarms by counting the number of discards; calculating the rolling variance representing fluctuations using a recursive algorithm based on an effective dataset; determining the trigger freeze signal based on comprehensive parameters, locking the buffer, and generating a fault snapshot. This invention achieves decoupling between the device communication protocol and the controller's underlying firmware by loading protocol bytecode containing spatiotemporal metadata and using a virtual machine engine for interpretation and execution. This allows the edge controller to adapt to HVAC equipment with different physical layer response characteristics and timing requirements without modifying the underlying code or recompiling the firmware, only by updating the protocol bytecode file.

A data transmission method and a data processing circuit, the data processing circuit includes a memory to implement a buffer, and a control circuit to control the operation of the data processing circuit. When the data processing circuit receives input data, the data hot bits of the input data are used to address a plurality of data blocks, and after the data hot bits are parsed, the start address and data length of each data block are obtained and written into the buffer, thereby generating the effect of masking false data addresses. In addition, before writing the plurality of data blocks into the buffer, the data dependency between the data blocks can be confirmed by comparing the data hot bits of the data blocks.

In an example, a memory controller is configured to: check whether a logical block address corresponding to a host read command is maintained in a write buffer; determine a level of an amount of drift corresponding to the logical block address if the logical block address is not maintained in the write buffer, where different levels of the amount of drift correspond to different read voltages; and send a read command to a non-volatile memory device according to the level of the amount of drift corresponding to the logical block address. At least two of the processes of checking whether the logical block address is maintained, determining the level of the amount of drift, or sending the read command are performed in parallel.

A multifunctional storage device and a method of processing a message are disclosed. The multifunctional storage device can include a chassis, a storage device, and a bridge device. The storage device can include a connector to receive a first message from a host using a first protocol, a physical function (PF) and a virtual function (VF) exposed by the storage device via the connector, a storage to store data related to the first message, and a controller to manage writing write data to the storage and reading read data from the storage. The bridge device can include an embedded network interface controller (eNIC) to receive a second message from the host using a second protocol, a write buffer, a read buffer, a bridge circuit to convert the second message using the second protocol into the first message using the first protocol, and a root port to identify the storage device and to transmit the first message to the VF. The bridge device can be configured to map the host to the VF.

A memory includes interface circuitry for receiving at least one write command. Multiple memory banks are organized into multiple memory bank groups and operate according to a corresponding memory bank group timing sequence. Each of the multiple memory banks includes a memory cell array. Multiple write buffers temporarily store write data associated with at least one write command. Write buffer selection circuitry egresses the temporarily stored write data from a selected buffer among the multiple write buffers based on the memory bank group timing sequence and directs the egressed write data to a given array of memory cell arrays.

A processor includes a register file, a context controller that, in response to a target interrupt occurring, is configured to determine, a target register that stores new data acquired through each of commands for executing an interrupt service routine (ISR) among the plurality of registers, a write buffer configured to transmit pre-data stored in the target register to a memory, and a flag register configured to store set data including set values indicating whether the new data is stored in each of the registers. The context controller is configured to determine whether to transfer the pre-data to the memory through the write buffer based on the set data.

In some aspects, the techniques described herein relate to a method including receiving, from a host device, a first request to write first data to a memory device; adding the first request to a queue on the memory device; determining an availability of a write buffer of the memory device; retrieving the first data from the host device based on the determining and the first request added to the queue; and writing the first data to a write buffer of the memory device. The method may further include returning a completion message to the host device based on writing the first data to the write buffer; and writing the first data from the write buffer of the memory device to storage media. The first request may be an SQE, and the method may further include parsing the SQE and determining that the SQE is a write command.

A non-volatile memory (NVM) controller is configured to control reads from and writes to an NVM array, and includes a write buffer and a buffer control circuit. The write buffer includes a plurality of entries, each configured to store a write access having a corresponding page address of the NVM array and corresponding write data. The buffer control circuit is configured to store a write access having a corresponding page address of the NVM array and corresponding write data, and generate burst writes from the write buffer to the NVM array. The buffer control circuit generates a burst write by sequentially selecting write accesses from the write buffer which have consecutive page addresses, in which the length of the burst write is undefined when the burst write to the NVM array is initiated.

A data transfer controller connected to a first digital interface of a computer system receives an instruction to prepare a variety of non-contiguous data elements in the computer system's main memory for transfer to a peripheral device connected to the first digital interface. The data elements are read from the computer system's main memory via a variety of gather transactions on a second digital interface. The second digital interface is connected to the data transfer controller and the main memory. The second digital interface allows the use of a subset of overhead data from the first digital interface for the gather transactions. The data elements are written to a buffer within a contiguous data block.A statement indicating that the contiguous data block is available for transfer from the buffer to the peripheral device via the first digital interface is provided to the peripheral device via the first digital interface.

This invention provides a data storage device and a method for avoiding timeouts in forced garbage collection. The data storage device includes a controller and non-volatile memory. The non-volatile memory stores multiple instructions and includes a system area, a data area, and a spare area. The spare area includes multiple blocks, including blank blocks, host data write buffer blocks, and garbage collection blocks. The controller is coupled to the non-volatile memory and is used to execute multiple instructions to implement the timeout avoidance method for forced garbage collection, which includes: determining that the number of blank blocks is below a threshold; determining that no garbage collection blocks exist after a sudden power outage; and marking the host data write buffer block as both a garbage collection block and a host data write buffer block.

The application provides a Cache write cache device and a control method thereof, and relates to the technical field of artificial intelligence chips. The device comprises: a write cache table for storing a plurality of write cache entries, each write cache entry corresponding to attribute information of a Cache line; a memory for storing data of the Cache line corresponding to each write cache entry; a write cache control unit for processing storage requests and loading requests based on the write cache table, and for writing the data of the Cache line corresponding to the write cache entry from the memory to a data storage unit when a preset write-back condition is met; a loading request queue for buffering loading request information from a previous execution unit or a previous Cache; and an effective address generation module for generating a corresponding effective write-back address according to a write data effective flag signal recorded in the write cache entry when performing a write-back operation. The application effectively reduces the write-back pressure on the lower-level storage, eliminates the structural blockage of the storage backend to the computing frontend, and significantly improves the overall memory access efficiency and computing throughput.

This invention relates to a real-time processing method and system for power dispatch alarms, belonging to the field of power system automation technology. To overcome the shortcomings of existing power dispatch alarm message processing methods, such as high maintenance complexity, poor crash recovery capabilities, and the inability to fully save all events in avalanche scenarios, this invention employs a single consumer thread to sequentially consume alarm messages from a partitioned message queue. A hash function routes messages to a fixed worker thread, ensuring that messages from the same partition are processed by the same thread. Each thread uses independent local state, eliminating the need for lock synchronization. When the write buffer reaches a threshold, messages are batch-persisted to a multi-column family in the LSM-Tree storage engine. This invention is primarily used for real-time processing of power dispatch alarm messages.

Embodiments of the present application provide a data migration control method and device, a storage medium and a program product, and relate to the technical field of databases. The method comprises: reading data from a source end and storing the data in a read buffer according to a back pressure control instruction; converting and transmitting the data in the read buffer to a write buffer; writing the data in the write buffer to a target end; and in the reading, transmitting and writing of the data, the following operations are synchronously performed: decoupling adjustment of the capacities of the read buffer and the write buffer; and updating the back pressure control instruction according to a monitoring result of a state parameter of the write buffer and a performance state of the target end, to adjust subsequent data reading operations. The method of the present application increases the cooperative mechanism of the decoupling adjustment of the double buffers and the back pressure control based on the multi-level strategy, and improves the stability and throughput efficiency of large-scale data migration tasks.

Methods, systems, and devices for write buffer extensions for storage interface controllers are described. Apparatuses and methods are presented in which a buffer may be used to temporarily store data from an application if the memory device is in an INACTIVE power mode. This may allow the memory device to remain asleep. The buffer may be positioned on the host device so that the power mode of the memory device may not affect it. That way, data may be stored in the buffer without waking up the memory device. If the memory device is in an ACTIVE power mode, the data that has been temporarily stored in the buffer may be sent to the memory device for storage. During read operations, if the requested data is stored in the buffer, it may be used instead of data in the memory device.

This disclosure provides a memory cell and a memory device. The memory device may include: a memory cell array comprising a plurality of memory cells; and a controller connected to the memory cell array. A first memory cell among the plurality of memory cells includes: a first inverter comprising a first PMOS transistor and a first NMOS transistor connected between the first PMOS transistor and ground; a second inverter comprising a second NMOS transistor and a second PMOS transistor connected between the second NMOS transistor and a power supply voltage; a write buffer that generates first data based on a first enable signal output from the first inverter and a second enable signal output from the second inverter; and a latch circuit that stores the first data. The controller is configured to: during a write operation to the first memory cell, apply a first column select signal to the source-drain electrode of the first PMOS transistor.

The application discloses a data query caching method and device, equipment, a storage medium and a program product, and relates to the technical field of data processing. The method comprises the following steps: obtaining a data query result fed back by a structured query statement; constructing an HBase table set in the HBase according to the structured query statement and the data scale of the data query result, each HBase table being allocated with a table name serial number and a buffer interval and being configured with a unique row key; positioning an HBase table to be cached through the table name serial number; and writing the data query result into the buffer interval in batches based on the unique row key. After the data query result is obtained, the HBase table set is constructed in the HBase according to the structured query statement and the data scale, so that the buffer intervals of multiple HBase tables are utilized, the read-write efficiency is effectively improved while the massive data query result caching is implemented, and the problem of slow response speed of massive data caching is solved.

A memory read response is received from a memory controller in response to a memory request and includes specific data and specific metadata attendant to the specific data retrieved with specific memory addresses in the device memory. The specific data and specific metadata are sent to a host device in a host-bound memory read response. In response to determining that a metadata update condition is satisfied, a number of actions are performed as follows. Specific modified metadata attendant to the specific data is determined. A MEMC-bound memory write request for metadata update is generated. The MEMC-bound memory write request is used to write the specific modified metadata attendant to the specific data in the device memory. The specific data and the specific modified metadata are stored in an entry of a temporary write buffer until the entry is invalidated by the corresponding metadata update write acknowledgement returned from the MEMC.

According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.

This invention relates to the field of industrial data acquisition and edge network technology, and discloses a data acquisition method for an automatic grease-adding system based on edge computing. This method establishes a node mapping table in the edge control unit, generates a global interlocking signal by comparing the real-time current of the main circuit with a threshold, and dynamically switches the polling frequency of the underlying bus. When the value of the underlying status register deviates from the interlocking signal, a time window anti-jitter mechanism based on time difference is introduced to filter out missynchronization caused by physical transmission delay. Furthermore, the edge unit implements read-write decoupling; read requests achieve a through-response based on the mapping table, and write requests are stored in a write buffer queue after acceptance evaluation. When the interlocking signal undergoes a state switch due to a physical abrupt change, the system forcibly locks the queue and suspends writing, prioritizing high-frequency status polling. This invention effectively eliminates read-write collisions caused by network latency, thereby improving the data consistency and operational security of the system under complex operating conditions.

Embodiments provide a memory system capable of avoiding mutual interference between cells, reducing write buffer capacity, and suppressing bit error rate deviation. In the memory system, a memory controller within the memory system: causes a nonvolatile memory to perform first programming so that a threshold region in a memory cell becomes, according to first, second, and fourth bit data, a certain threshold region among a 17th threshold region that indicates an erased state in which data has been erased and 18th to 24th threshold regions that indicate a written state in which data has been written at a voltage level higher than the 17th threshold region, causes the nonvolatile memory to perform second programming so that the threshold region in the memory cell changes, according to third bit data, from a certain threshold region among the 17th to 24th threshold regions to a certain threshold region within two threshold regions among the 1st to 16th threshold regions, and inputs, to the nonvolatile memory, the second and third bit data in a case where the nonvolatile memory is caused to perform the second programming.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing real-time text logging. One of the methods comprises receiving, by a real-time robotics control framework, multiple indications of multiple events associated with multiple log messages. For each log message of the multiple log messages, the method further includes writing, by a real-time thread, characters of the log message into a buffer dedicated to the real-time thread using real-time safe commands, receiving, by a non-real-time thread of the real-time robotics control framework, an indication that the log message has been written into the buffer, and reading the log message and writing to a non-real-time output channel.

The application provides a memory system, an operating method of the memory system, a memory device and a memory controller, and relates to the technical field of semiconductor chips. The memory system comprises a memory device and a memory controller, the memory device is coupled with the memory controller, the memory device comprises a plurality of dies, and each die comprises a first physical block. The memory controller is configured to, in response to a data write instruction, determine a physical block to be written with data, and the number of the physical block to be written with data is less than the number of the first physical block. According to the address of the physical block to be written with data, the memory device is controlled to write data into the physical block to be written with data. The embodiment of the application can reduce the amount of data written each time when data parallel writing is performed, and thus the demand of the memory controller for a write buffer is significantly reduced, the demand for a built-in capacitor for performing a power-off protection function is also reduced, and the design difficulty of a circuit board is reduced.