219 results about "Write buffer" patented technology

The invention discloses a storage and calculation separation key value storage delay optimization method based on prediction driving, and aims to solve the problems of performance bottleneck and high tail delay caused by passive management and high network delay in a key value storage system in a storage and calculation separation scene. The method comprises the following steps: time load prediction: deploying a time sequence prediction model at a client, and predicting a future read-write request based on a historical access sequence; active cache prefetching: according to the predicted read request, actively preloading hotspot data from a server side to a client side for caching so as to improve the cache hit rate and hide network delay; active write-in optimization: according to the predicted write request, executing maintenance at a server side through predictive pre-insertion and active node splitting, and moving high index structure adjustment overhead out of a key request path to eliminate a write delay peak; and structure sensing batch synchronization: pre-fragmenting a local write buffer by using a server index top layer model of a client cache, and combining multiple independent remote insertion operations into one efficient batch update to reduce data synchronization overhead. Compared with an existing passive management system, the characteristics of model prediction and active cooperation are fully utilized, and the average delay and the tail delay of the system are reduced.

Examples described herein provide a computer-implemented method for storing data pages of a database in a remote storage. The method includes receiving a write request associated with one or more data pages of the database. The method further includes storing, in a first storage layer having a write ahead log, the write request associated with the one or more data pages. The method further includes storing, in a first write buffer, the received write request associated with the one or more data pages that each include a legacy data page identifier. The method further includes storing, in a second storage layer having a second write buffer, a sorted string table (SST) of the received write request. The method further includes storing, in a top level of a log structured merge (LSM) tree disposed in the remote storage, the SST from the second write buffer.

A first command including data to be stored in non-volatile random access memory (NVRAM) of a storage device is received from a storage system controller by a storage device controller. In response to receiving the first command, the data is stored in the NVRAM. One or more second commands including a location in flash memory of the storage device for storing the data and an instruction to store the data in the location of the flash memory are received from the storage system controller. In response to receiving the one or more second commands, the data is stored in the location of the flash memory.

A controller manages a plurality of block groups each including one or more blocks among a plurality of blocks provided in a non-volatile memory. The controller assigns one of the plurality of block groups to each of plurality of zones. The controller writes write data which is to be written to a first zone to a shared write buffer and writes write data which is to be written to a second zone to the shared write buffer. When a total size of the write data in the first zone stored in the shared write buffer reaches a capacity of the first zone, the controller copies the write data in the first zone stored in the shared write buffer to the first block group assigned to the first zone.

The invention relates to a method, a device, equipment and a medium for optimizing an SSD (Solid State Disk) write buffer area, and the method comprises the following steps: acquiring a newly written operation request to obtain written data; judging whether the new write-in is host write-in or not; if so, writing the write-in data into a data preparation area; judging whether the data volume in the data preparation area reaches a concurrent write-in threshold value or not; if yes, concurrence data is formed, the concurrence data prepared in the data preparation area is transferred into the data programming area, and the concurrence data is transmitted to a specified Page of each DIE specified WL; whether loading of the Page data corresponding to the WL is completed or not is judged; and if the loading is completed, initiating a programming command of the WL corresponding to each DIE until the data programming is completed. According to the invention, the key data can be processed in time, the delay of data processing is reduced, the idle or excessive allocation of resources is avoided, and the optimal configuration of the resources is realized.

This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes maintaining a list of data segments stored in a write buffer having a single-level cell memory architecture. The list includes, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed. The list is sorted based on the available contiguous memory space. The method includes detecting a flush opportunity and initiating, based on the detecting, a flush operation to write a first data segment that corresponds to a first entry of the list from the write buffer to a memory module having a higher storage density memory architecture. Other aspects and features are also claimed and described.

The invention provides a low-orbit satellite high-capacity software on-orbit reconstruction method and system, and belongs to the field of satellite on-orbit reconstruction, and the method comprises the steps: S1, carrying out the batch and framing processing of an ultra-large-capacity reconstruction packet on the ground; s2, the satellite-borne management software verifies and writes the information service unit DRAM temporary area; s3, the satellite-borne management software carries out continuity verification on the current batch of reconstruction files in the DRAM temporary area, a result is downloaded to the ground, and the ground carries out supplementary injection of an error-missing packet according to telemetering; s4, the spaceborne management software writes the reconstructed file which is verified to be normal into a FLASH buffer area; s5, the satellite-borne management software forwards the complete reconstruction files to a terminal reconstruction unit in batches; and S6, after the terminal reconfiguration unit operates the reconfiguration version for a period of time, the spaceborne management software writes the reconfiguration file into the FLASH solidification area according to a ground instruction, and the reconfiguration file is used as a backspacing version. According to the method, the problem of on-orbit reconstruction of ultra-large-capacity software is solved, and the reconstruction efficiency of the satellite in the controllable arc section is improved.

According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.

A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device (FMD). The HCI is configured to obtain an indication that a size of a particular write buffer (WB) of the FMD is to be increased. The FMD includes a plurality of memory resources that include a plurality of logical units (LUs) and at least the particular WB. The HCI is also configured to select a particular memory resource for write buffer reallocation based at least in part on a particular usage metric of the particular memory resource.

A method for writing data to a shared write buffer, the method includes (i) receiving, by a processing circuit of a compute node of a storage system, a write request for writing to the shared write buffer an information unit associated with an accessing entity located outside the storage system; wherein the shared write buffer is stored in a non-volatile memory of a storage node of the storage system; the storage node is in communication with the compute node; (ii) determining, by the processing circuit whether to (a) store the information unit in a non-shared segment of the shared write buffer, or (b) store the information unit in a shared segment of the shared write buffer while applying a locking mechanism; wherein the determining is based on parameters, the parameters include a writing parameter of the accessing entity, a writing latency parameter associated with the accessing entity, and a locking timing parameter; and (iii) storing the information unit according to the determination.

Methods, systems, and devices for configurable logical-to-physical table storage extension at a memory system are described. The described techniques provide for a memory system to share host write data and logical-to-physical (L2P) extension data within a write buffer. If the memory system triggers L2P extension, the memory system may compare a quantity of available buffer units with an upper bound of a range of buffer units configured for L2P extension. For example, if enough buffer units are available for a full L2P extension, the memory system may allocate a full L2P extension, and if there are not enough buffer units available, the memory system may allocate a partial L2P extension. If the memory system allocates a partial L2P extension, the memory system may begin flushing write data stored to the buffer and may allocate newly available buffer units for the L2P extension.

Methods, systems, and devices for write buffer management for a memory system are described. The described techniques provide for a memory system to receive data associated with multiple applications being executed concurrently and store the data to portions of a write buffer according to whether the data is sequential or non-sequential. For example, the memory system may receive sequential data for a first application between receiving non-sequential data for one or more second applications, and may partition a write buffer such that the sequential data is stored (e.g., sequentially) within a portion the write buffer and the non-sequential data is stored within a different portion of the write buffer. The memory system may flush portions of the write buffer to multiple-level memory cells once a portion is full, thereby storing sequential data to sequential physical addresses within the memory system.

A key-value store is provided, implementing multiple-tiered sorted data structures in memory and storage, including concurrent write buffers in memory, and page-level consolidation of updates on storage, where pages are trivially translated in physical-to-virtual address mapping. The key-value store is built on an indexed sorted data structure on storage, occupying much less storage space and incurring much less disk activity in consolidating updates than a conventional log-structured merge tree organized into files. Concurrent write buffers operate concurrently and independently so that data is committed from memory to storage in an efficient manner, while maintaining chronological sequence of delta pages. Trivial mapping allows mappings of a number of physical pages to be omitted, enabling page mapping tables to occupy less storage space, and simplifying processing workload of read operation retrievals from storage.

A data processing system includes a controller configured to receive a first encoded data item and a write request from a host, the first encoded data item being encoded based on a hamming code. The controller is further configured to store the first encoded data item in a write buffer, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item, encode the first error-corrected data item based on an error correction code to generate a second encoded data item, and transmit the second encoded data item to program the second encoded data item in a non-volatile memory device.

This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes maintaining a list of data segments stored in a write buffer having a single-level cell memory architecture. The list includes, for each entry of the list, a data segment identifier of a respective data segment and an available contiguous memory space in the write buffer if the data segment is flushed. The list is sorted based on the available contiguous memory space. The method includes detecting a flush opportunity and initiating, based on the detecting, a flush operation to write a first data segment that corresponds to a first entry of the list from the write buffer to a memory module having a higher storage density memory architecture. Other aspects and features are also claimed and described.

The invention provides a test method and a test device for a storage chip, and belongs to the technical field of storage. The test method of the memory chip comprises the following steps: writing filling data into the memory chip until a memory is filled with the filling data; starting a cache function of the storage chip, and writing test data into the storage chip, the data format of the test data in each data unit being related to the writing sequence, and the data formats of the test data written in each data unit being the same; when the data volume of the test data written into the storage chip reaches a set threshold value, power supply of the storage chip is cut off in the process of writing the test data into the storage chip; and obtaining the capacity of the write buffer according to the test data which is finally written in the memory and the test data which is finally written in the write buffer. According to the test method and the test device for the memory chip, the capacity of the write buffer can be obtained.

An improved flushing technique controls a draining speed of data from a temporary storage tier to a backend storage tier of a node so that draining logic does not overwhelm an input / output (I / O) workload that is serviced by the storage tiers. Illustratively, the temporary storage tier is a persistent write buffer embodied as an operations log (oplog) and the backend storage tier is persistent physical disk storage embodied as an extent store. The technique improves an oplog flushing algorithm by enabling control of the oplog draining speed (rate) to provide consistent performance when the I / O workload (e.g., a primary ingest I / O stream) is serviced by the extent store and / or oplog during one or more states (e.g., static inertia state, idle state and rebuild state) of the oplog.

Methods, systems, and devices for an intelligent throughput router are described. A memory system may monitor parameters associated with write commands being received. The memory system may select whether to write data to a first block type (e.g., a high density cell block) or a second block type (e.g., a single-level cell block) of a non-volatile memory device based on the parameters. The memory system may store data associated with write commands in a volatile storage area such as a write buffer, and monitor the size of the write buffer. The memory system may select the first block type or the second block type based on thresholds associated with usage of the write buffer. The memory system may estimate a throughput of data associated with the write commands, and select the first block type or the second block type based on thresholds associated with the throughput of data.

The present application relates to a solution to a coherency problem in a logical to physical page translation in a memory subsystem. A write request is received to program data to a memory device of the memory subsystem. An intermediate entry of a data structure is generated, the intermediate entry including a pointer identifying a write buffer associated with an intermediate write operation corresponding to the write request. A read request is received to read the data from the memory device, and a seek operation is performed on the data structure to identify the intermediate entry. The pointer is used to locate the write buffer associated with the intermediate write operation. The write buffer is copied to a read buffer associated with the read request, and the read request is executed using the read buffer.

Examples of the present application provide memory systems, methods of operating thereof, and storage mediums. An example memory system includes at least one memory device and a memory controller; the memory controller is coupled with both a host and the memory device and includes a write buffer and a control section coupled with the write buffer; the control section is configured to: in response to upcoming execution of an erase event of a block in the memory device, configure a portion of an idle storage space of the memory controller as a newly-added storage space of the write buffer; write data received from the host to the newly-added storage space of the write buffer in response to execution of the erase event; and release the newly-added storage space of the write buffer in response to completion of the erase event.

The invention discloses a lightweight rapid serialization method for high-throughput scientific data, which comprises the following steps of: 1) defining a uniform data model for each line station, including a common header field, a state specific field and a line station exclusive field; the common header field records the same information contained in each line station, the state specific field describes the data generation state of the line station, and the line station exclusive field describes the customization attribute contained in the data stream in different data generation states; 2) each line station processes the generated data according to the data model, generates a data stream model and serializes the data stream model, and a generator calculates the initial offset and the number of occupied bytes of each field in a binary stream according to the type, length and sequence of the fields; for a pre-distributed continuous buffer area, generating field write-in logic positioned according to offset, converting each field value into a byte stream according to the data type of the field value, and writing the byte stream into a corresponding position of the buffer area; and splicing the code of the binary data of each field to obtain serialized data.

A memory controller receives a write request and write data from a host, stores first entry information including a write buffer pointer indicating a location where the write data is temporarily stored in a write buffer and a first logical address corresponding to the write request in an entry buffer, stores an entry index generated based on the first entry information in a first storage space corresponding to the first logical address in a logical-to-physical (L2P) mapping information storage circuit, and updates the entry index stored in the first storage space to a physical address newly mapped to the first logical address as the write data is programmed in a memory device.

A data storage device includes a plurality of holding capacitors configured to provide backup power for a non-volatile memory, a controller, and a write cache. The controller is configured to detect one or more failed holding capacitors of the plurality of holding capacitors; and in response to detecting the one or more failed holding capacitors: performing one or more silence operations, and determining a count of the one or more failed holding capacitors. Based on the count of the one or more failed holding capacitors, the controller is configured to reallocate a write buffer of the write cache for use in one or more subsequent write operations.

This invention discloses an edge-side out-of-order write reordering method for consumer-grade partitioned storage, belonging to the field of computer storage systems and flash memory management technology. Addressing the problem of degraded multi-threaded parallel write performance in consumer-grade partitioned storage due to kernel-forced sequential writes, and the insufficient capacity of the edge-side SRAM write buffer to meet large-scale out-of-order reordering requirements, this invention proposes a dynamic processing method with a two-layer reordering architecture. By dividing the high-performance SLC flash memory region in the device into page-level SLC and zone-level SLC as an extended write buffer, when processing write requests, the continuity and temperature label of the data in the SRAM buffer are judged; if the data is continuous and hot data, a direct flushing strategy is executed to the zone-level SLC; if out-of-order data occurs and the buffer is insufficient, a degradation strategy is executed to temporarily store the data in the page-level SLC; and continuity is dynamically restored when subsequent data is supplemented. This invention overcomes the limitations of small edge-side caches while releasing the parallel write potential of the device, significantly improving multi-threaded write IOPS.

The invention discloses a data processing method, electronic equipment and a computer readable storage medium, and the data processing method is applied to a host end and comprises the steps that in response to a data writing command, a corresponding mode index is selected for each logic block address in the data writing command; obtaining first cache data corresponding to each logic block address based on the mode index; in response to the fact that the first cache data corresponding to all the logic block addresses are written into the write buffer area, a data write-in command is sent to the storage device; and in response to completion of execution of the data writing command, caching all the mode indexes corresponding to the data writing command into the memory, the mode indexes being used for performing reading verification during data reading. By means of the mode, due to the fact that the data size of the mode index is small, occupied memory is small, only a small amount of time is needed to be saved in the memory, and the overall speed of data reading and writing can be increased.

According to some embodiments, a replication tool may arrange for a copy of original records from a data source to be written into a read-only replica in an application stack. Write buffer logic in the application stack may determine that information in an original record of the read-only replica has been locally updated at the application stack by application logic. The write buffer logic may then automatically create an updated version of the original record in a write buffer of the application stack based on the local update by the application logic. Moreover, prioritization logic may automatically determine whether information in the original record or the updated record will be accessed.

The present invention discloses a method for reading 4K medical image memory, including: defining a shared memory and a thread control variable step, saving the names of the defined shared memory and the thread control variable in the shared variable segment, an initialization step, applying for a shared memory from the operating system according to the name of the shared memory, and initializing the thread control variable; an image data memory reading step, the GPU calls an interface to read image data from the reading part, processes the image data by the GPU, and sends the processed image data to a display device for display. The 4K medical image memory reading method of the present invention, by opening up multiple shared memories and using a multi-thread synchronization method at the same time, multiple write buffer areas in the writing part are used to alternately receive image data from an image acquisition device, and can efficiently transfer video data into the memory in real time, ensuring that the data will not be in a state of waiting for data.

A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device (FMD). The HCI is configured to obtain an indication that a size of a particular write buffer (WB) of the FMD is to be increased. The FMD includes a plurality of memory resources that include a plurality of logical units (LUs) and at least the particular WB. The HCI is also configured to select a particular memory resource for write buffer reallocation based at least in part on a particular usage metric of the particular memory resource.

Aspects relate to interrupting memory access during background operations of a memory device. In one example a memory device includes a memory controller to initiate a write buffer flush operation. A bus interface is coupled to a main memory and to a write buffer to receive a write command from a host during the write buffer flush operation. The memory controller initiates the write buffer flush operation, suspends the write buffer flush operation in response to the write command, sends a last flushed address of the write buffer from the memory device to the host through the bus interface, and unmaps a portion of the write buffer using the last flushed address.

The application provides a memory particle packaging method and system based on a HIPI protocol, which packages memory particles through the HIPI protocol, and the memory particle packaging method comprises the following steps: receiving all signals sent by a DRAMC through a DRAM interface module, analyzing the signals through semantics, and then packaging the signals to a HIPI channel; synchronizing the bandwidth of the HIPI and the DRAM particle through a read-write buffer module to complete the HIPI packaging; generating a DQS signal and a Clock signal of the DRAM particle based on the access protocol of the DRAM through a DRAM clock signal generation module; and writing data into the DRAM particle or reading data out of the DRAM based on the DQS signal and the Clock signal. In the memory particle packaging process, the DRAMC and the memory particle do not need any modification, and the application is friendly to the development of hardware manufacturers.