40 results about "Memory interface" patented technology

Various aspects relate to a memory module including: a memory interface; a non-volatile storage device for persistently storing data; a non-volatile memory device providing a write first in first out, FIFO, buffer in hardware, the write FIFO buffer being configured to receive, via the memory interface, and to store packets associated with one or more atomic transactions, wherein each of the one or more atomic transactions includes a respective plurality of packets and indicates corresponding data to be written to the memory module; a memory controller configured to write the corresponding data of an atomic transaction of the one or more atomic transactions to the memory module in the case that the write FIFO buffer stores the respective plurality of packets of the atomic transaction.

A computing system is disclosed, comprising a host computer and multiple CGRPs (coarse-grained reconfigurable architecture processors) connected to the host computer through external communication links. Each CGRP includes an internal network, external interface circuits, memory interface circuits, arrays of configurable units, hang detection circuits, force-quit controllers, and a network recovery circuit with control registers. The host computer is programmed to configure and execute applications across the arrays of configurable units in both CGRPs. In case of a hang detection in one CGRP, the network recovery circuit initiates a force quit process and notifies the host computer. Additionally, the network recovery circuit compares application IDs and halts execution in the other CGRP if necessary. This system provides efficient failure tolerance and recovery mechanisms for parallel processing applications.

Techniques are disclosed relating to a shared control bus for communicating between primary control circuitry and multiple distributed graphics processor units. In some embodiments, a set of multiple graphics processor units including at least first and second graphics processors on different semiconductor substrates that are packaged in a multi-chip module, where the first and second graphics processors are coupled to access graphics data via respective memory interfaces. The shared workload distribution bus may include: one or more interfaces between respective graphics processors on the same semiconductor substrate and at least one cross-substrate interface between the different semiconductor substrates. Workload distribution circuitry may transmit, via the shared workload distribution bus, control data that specifies graphics work distribution to the multiple graphics processor units. Packet control circuitry may modify packets from at least one of the one or more interfaces for transmission via the cross-substrate interface.

The present disclosure relates to assistance indication of resource reservation in sidelink. Techniques discussed herein can facilitate assistance indication of resource reservation in sidelink. One example aspect is a user equipment (UE) comprising: a memory interface; and processing circuitry communicatively coupled to the memory interface and configured to: generate a physical sidelink control channel (PSCCH) message related to a first stage sidelink control information (SCI), wherein the first stage SCI comprises a first indication related to a SCI assistance request; and cause transmission of the first stage SCI.

Various aspects relate to a memory module including: a memory interface; a storage device for persistently storing data; a non-volatile memory device providing a memory storage for persistently storing data and providing a write buffer configured to receive, via the memory interface, and to store corresponding data to be written to the memory module; and a memory controller configured to write the corresponding data selectively from the write buffer to the storage device or to the memory storage.

A system includes an interface, a processor, and a memory. The interface is configured to receive a version of a model from a model registry. The processor is configured to store the version of the model, start a process running the version of the model, and update a proxy with version information associated with the version of the model, wherein the updated proxy indicates to redirect an indication to invoke the version of the model to the process. The memory is coupled to the processor and configured to provide the processor with instructions.

Apparatuses and methods for an integrated device with trusted execution environment (TEE) confidential computing support are disclosed. An apparatus and method for extending IO device security protocols to an integrated processor. For example, an example processor package includes: a plurality of cores to execute instructions; an interconnect structure coupled to the plurality of cores; a memory interface circuit coupled to the interconnect structure, the memory interface circuit to couple the plurality of cores to one or more memories; a root complex comprising: a security circuit operable as a root of trust (RoT) and a bridge to the interconnect structure, the security circuit for establishing secure communications with one or more root complex integrated endpoint (RCiEP) devices integrated into the processor package; and a security protocol and data model (SPDM) engine of the security circuit for providing RCiEP encryption and SPDM protocol services to establish a secure communication channel with each RCiEP device.

Systems and methods include a memory device that includes a memory interface configured to receive a data and a clock from a host device. The memory device also includes alignment circuitry configured to sample the data based at least in part on the clock. The alignment circuitry also is configured to count a first number of samples of the data sampled as a current symbol and to count a second number of samples sampled as a previous symbol. The alignment circuitry further sets an amount of delay based on a comparison of the first number and the second number and generates a data strobe as a locally generated data strobe by adding or subtracting the set amount of delay to the clock.

A semiconductor system and a testing method thereof, the semiconductor system comprising an electronic device having a processor and a memory device. The memory device includes an input pad for receiving input signals, an output pad for outputting a first output signal in a first test mode and a second output signal in a second test mode, and a memory interface coupled to the electronic device. The memory interface includes a transceiver and a mode selection circuit. The transceiver communicates with the electronic device. The mode selection circuit selects either a first test mode or a second test mode. The first test mode includes load from the transceiver and the electronic device in the memory interface. The second test mode excludes load from the transceiver and the electronic device in the memory interface.

Systems, methods, and apparatus related to memory devices. In one approach, a memory device includes memories that store data received from a host device. The memory device includes a memory interface to the host device. The memory device further includes one or more processing devices to perform, using a portion of the data stored in one or more of the memories, computations for a neural network. An output of the neural network is stored in one of the memories. The memory device has a controller that controls memory access by the host device and the processing devices to avoid a conflict. The memory device communicates with the host device over the memory interface using a DRAM bus protocol. This communication includes sending the output of the neural network to the host device.

A memory system includes a memory interface including a first sub-channel interface associated with a first plurality of memory banks and a first plurality of processor in memory (PIM) blocks and further including a second sub-channel interface associated with a second plurality of memory banks and a second plurality of PIM blocks. During a particular mode of operation associated with the memory system, the first sub-channel interface is configured to communicate, with a host device, one or more memory access commands associated with the first plurality of memory banks. During the particular mode of operation, the second plurality of PIM blocks are configured to perform, concurrently with communication of the one or more memory access commands, one or more PIM operations associated with the second plurality of memory banks. The second sub-channel interface is configured to be disabled during the particular mode of operation.

This utility model belongs to the field of storage, specifically relating to a multi-cavity distributed storage platform, including a storage platform and a storage mechanism including a plurality of distributed storage boxes installed in the inner cavity of the storage platform; the front end of each distributed storage box is used to insert a memory, and the notch at the rear corresponds to the memory interface at the end of the memory; the memory is distributed and installed in each distributed storage cavity of the storage platform, and each memory is relatively independent with its own storage space and data processing capability, forming a distributed system. When writing and retrieving stored content, it is achieved through a first displacement mechanism, a second displacement mechanism, and a disk reading mechanism. After the disk reading structure moves to the corresponding memory position according to the working requirements, the disk reading interface of the disk reading end is connected to the memory interface to perform writing or retrieval of distributed memory. During access and retrieval, each memory is relatively independent, and the content stored in different memories does not interfere with each other.

This invention relates to the field of radiation-hardened integrated circuit technology, and particularly to a spaceborne computer system with memory space single-event upset (SOME) detection capability. The system includes: a processor, a bus, a memory, a memory interface controller, an error correction and detection module, and a detection module. The memory contains several memory words, each containing several memory bits and several parity bits. The detection module adjusts the duration of the next detection cycle based on the number of memory words with single-bit errors in the current detection cycle, and performs SOME detection and correction on the memory in each detection cycle via the bus, memory interface controller, and error correction and detection module. The error correction and detection module is connected to the memory through the memory interface controller and is used to detect and correct single-bit errors in each memory word. This solution not only does not consume processor computing resources but also adaptively adjusts the detection cycle duration.

The application discloses a programmable non-glitch period delay control circuit based on TSPC and belongs to the technical field of integrated circuits. In order to solve the problems of dynamic node leakage, logic state loss of existing TSPC dynamic circuits under long waiting periods, and easy generation of glitches in high-frequency clock switching, the application adopts a two-stage programmable multi-mode frequency divider architecture, forcibly locks all TSPC dynamic nodes to a fixed low level through a low-level effective asynchronous reset end in a waiting period, and ensures the stable establishment of a gating signal in a clock low-level window through a half-cycle timing constraint design. The application supports independent programmable configuration of waiting periods and release periods, can realize non-glitch clock control under a super-high frequency of more than 5GHz in a full PVT working condition, has super-low standby power consumption and high reliability, and is suitable for clock path management, read-write phase calibration and low-power mode switching of a DDR memory interface and the like.

An electronic substrate implements fault-tolerant signal routing in redistribution layers by pairing aligned conductors in different metal layers and periodically tying the pair with vias so the same signal traverses both paths. The redundant geometry maintains electrical continuity when an open defect occurs in one conductor while preserving target resistance by apportioning the total cross-section between the paired traces. Test access structures enable continuity verification from the top surface, supporting single-sided probing of through-silicon-via connectivity and fabric links. The approach applies to high-density interconnects such as chip-to-chip fabrics and memory interfaces on silicon circuit boards and interposer-class substrates, improving yield and reliability at large layout scales without increasing layer count.

An apparatus and method for extending IO device security protocols to integrated processors. For example, an example processor package comprises: a plurality of cores to execute instructions; an interconnect fabric coupled to the plurality of cores; memory interface circuitry coupled to the interconnect fabric, the memory interface circuitry to couple the plurality of cores to one or more memories; a root complex comprising: security circuitry operable as a root of trust (ROT) and a bridge to the interconnect fabric, the security circuitry to establish secure communication with one or more Root Complex Integrated Endpoint (RCiEP) devices integral to the processor package; and a Security Protocol and Data Model (SPDM) engine of the security circuitry to provide RCiEP encryption and SPDM protocol services to establish secure communication channels with each RCiEP device.

A system and method for managing memory resources. In some embodiments, the system includes a first server including a storage program processing circuit, a first network interface circuit, and a first memory module. The first memory module includes a first memory die and a controller. The controller is connected to the first memory die through a memory interface, connected to the storage program processing circuit through a cache coherency interface, and connected to the first network interface circuit.

Non-volatile memory devices are provided that support a high efficiency I / O interface. The non-volatile memory devices include a first pin to receive a first signal, a second pin to receive a second signal, a third pin to receive a third signal, a fourth pin to receive a write enable signal, an array of memory cells, and a memory interface circuit to obtain commands, addresses, and data from the third signal in a first mode and to obtain commands and addresses from the first and second signals and data from the third signal in a second mode. In the first mode, the memory interface circuit obtains commands from the third signal and obtains addresses from the third signal. In the second mode, the memory interface circuit obtains commands from the first and second signals and obtains addresses from the first and second signals.

Facility (100), comprehensive: a memory interface circuit (130) configured to be coupled to a storage device (150) via an interface (140) having a command bus (144) clocked by a command clock signal (142), the storage device (150) comprising a plurality of banks; and a control circuit (120) coupled and configured with the memory interface circuit (130) to initiate a multi-bank memory operation by scheduling a sequence of bank-specific commands to be sent to the memory device (150) via the command bus (144), wherein the bank-specific commands for a given memory bank (152) include the following: a first activation instruction, followed by a second activation instruction two cycles of the instruction clock signal (142) later; and a read / write command that follows the second activation command by at least one minimum timing parameter specified for the storage device (150), wherein the read / write command specifies a type of operation to be performed; and where it is planned that every second read / write instruction during the multi-bank memory operation will be delayed beyond the minimum timing parameter, and where it is planned that remaining read / write instructions will not be delayed beyond the minimum timing parameter.

An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package. The integrated circuit may include a communication interface including a serializer / deserializer (SerDes) interface; a fabric adapter communicatively coupled to the communication interface; a plurality of inference engine clusters, each inference engine cluster including a respective memory element and / or memory interface; and a data interconnect communicatively coupling each respective memory element and / or memory interfaces of the plurality of inference engine clusters to the fabric adapter. The fabric adapter may be configured to facilitate remote direct memory access (RDMA) read and write services and / or datagram communication over a cell-based switch fabric to and from the respective memory elements and / or memory interfaces of the plurality of inference engine clusters via the data interconnect.

This application provides an eye diagram determination circuit and method for memory interfaces. The circuit includes: a data comparison control module, a training counting module, an eye diagram determination module, a first register, and a second register. The data comparison control module compares the read data and expected data corresponding to each round of training to obtain the number of error bits in the read data, and generates an increment / decrement control signal for the DQS delay value after each round of comparison. The training counting module adjusts the coarse delay and fine delay based on the increment / decrement control signal, and writes the updated coarse delay and fine delay into the first register. The eye diagram determination module determines the DQS delay values ​​corresponding to the left eye, middle eye, and right eye based on the number of error bits in the read data corresponding to each round of training and the DQS delay value, and writes them into the second register. This avoids the problems of slow boot speed, high development, debugging, and driver management difficulty, and excessive storage space consumption caused by software-implemented eye diagram determination.

An apparatus can include a die including a memory interface, a die-to-die (D2D) circuit including a D2D interface, and an intermediate portion connected between the memory interface and the D2D interface, where the intermediate portion includes a transaction translator. The intermediate portion can be configured to transfer data over the D2D interface using a protocol. The D2D interface can be configured to transfer data using flow control. The D2D interface can be configured to transfer data using a native format.

The application belongs to the technical field of memory interface and data transmission, and relates to a high-speed data transmission communication method of a double data rate memory interface. The application extracts traffic characteristics through a neural network to predict a direction switching time and calculate phase synchronization compensation, combines dynamic delay deviation and load ratio to calculate sampling compensation, accurately generates a transceiving cooperative scheduling strategy according to historical average propagation delay and hardware response time, cooperates with a check coding, hierarchical scheduling and avoidance retransmission mechanism, solves core problems such as bus timing step loss, link dynamic jitter offset, control signaling and service data conflict and state synchronization recovery lag in direction switching in high-speed bidirectional transmission, realizes accurate active capture of a transceiving switching boundary and dynamic accurate alignment of a data sampling edge, ensures conflict-free priority mapping transmission of key timing signaling, effectively shortens a fault recovery period, and comprehensively improves high-speed link transmission accuracy and overall cooperative efficiency.

The disclosure provides a memory controller that controls a memory device including a secure storage area, which can include a host interface configured to receive a command from a host, the command including information for requesting authentication for access to the secure storage area, a processor configured to generate a device authentication code based on the information for authentication, and a memory interface configured to access the secure storage area under control of the processor, and the processor can perform at least a part of an operation of the device authentication code when the host interface or the memory interface receives data according to the command.

This invention provides a method and device for retrieving phased array antenna amplitude and phase compensation data, comprising: after the beam control system is powered on, the FPGA sequentially reads the pre-stored phased array antenna amplitude and phase compensation data in the NOR flash memory according to a predetermined storage rule; the NOR flash memory transmits the compensation data back to the FPGA, and the FPGA stores the data through a first-in-first-out (FIFO) pipelined architecture; the FPGA uses a memory interface generator (MIG) IP core to configure communication with DDR3, and temporarily stores the compensation data in DDR3 according to the predetermined storage rule; when the FPGA performs compensation operation, it generates the address of the corresponding frequency channel according to the predetermined storage rule, and reads the compensation data in DDR3 back to the FPGA through the memory interface generator (MIG) IP core; the FPGA performs data compensation calculation on the read-back compensation data to complete beamforming.

This disclosure describes systems, methods, and devices related to enhanced memory integration. The device may include a compute chiplet configured as a System-on-a-Chip (SoC). The device may include a logic die circuitry coupled to the compute chiplet through a high-speed link. The device may include a memory interface that connects the logic die circuitry to on-package memory. The device may include control circuitry within the logic die circuitry configured to treat the on-package memory as a memory-side cache for an off-package memory. The device may dynamically migrate memory pages between the on-package memory and the off-package memory based on memory access patterns. The device may facilitate efficient data management, optimize memory utilization, and support scalable memory architectures for improved performance.

An apparatus is provided that includes a plurality of memory devices and a buffer device that permits use of memory devices having a variety of physical sizes and memory formats in an industry standard memory module format. The buffer device includes memory interface circuitry and at least one first-in-first-out (FIFO) or multiplexer circuit. The apparatus further includes a parallel bus connecting the buffer device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels each coupling the at least one FIFO or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

A memory interface circuit includes an instruction decoder configured to receive an instruction from a processor to generate a corresponding control code. An execution circuit is configured to receive the control code from the instruction decoder and access a memory and generate an arithmetic result according to the control code

A multi-power-domain emulated persistent memory resource system includes a memory interface / data mover subsystem coupled to a second memory subsystem in a second power domain, and a microvisor subsystem coupled to the memory interface / data mover subsystem and a first memory subsystem in a first power domain that is different than the second power domain. The microvisor subsystem presents an emulated persistent memory resource to a client device using the first memory subsystem, and monitors metadata for the first memory subsystem to identify modification(s) of data in the first memory subsystem. In response, the microvisor subsystem uses the memory interface / data mover subsystem to copy the data from the first memory subsystem to the second memory subsystem. Following unavailability of the first power domain and corresponding loss of the data on the first memory subsystem, the memory interface / data mover subsystem copies the data from the second memory subsystem to the first memory subsystem.

A memory system includes an electronic device and a memory device. The memory device includes an input pad for receiving an input signal and an output pad for outputting a first output signal in a first test mode and outputting a second output signal in a second test mode. The memory device further includes memory interface which has a transceiver and a mode selecting circuit. The transceiver communicates with the electronic device, and the mode selecting circuit selects the first test mode or the second test mode. Loading from the transceiver of the memory interface and the electronic device are included in the first test mode, and the loading from the transceiver of the memory interface and the electronic device are excluded in the second test mode. The memory system may compare the first output signal and the second output signal to generate a test result.