375 results about "Memory interface" patented technology

Techniques are described herein for system for preserving memories and experiences through a Non-Fungible Token (NFT) engine. An example system includes one or more memories storing a set of computer-readable instructions including the NFT engine and one or more processors interfacing with the one or more memories. The one or more processors are configured to execute the set of computer-readable instructions to cause the system to: receive data of a user from a time period, and execute the NFT engine to: analyze the data to classify a memory experienced by the user during the time period based on a memory threshold, generate, for display to the user, an NFT based on the memory, and mint the NFT corresponding to the memory to a blockchain, wherein a portion of the data associated with the memory is linked to the NFT.

One embodiment provides a graphics processor comprising a memory interface and a graphics core cluster including a plurality of graphics cores and tensor processing circuitry. The tensor processing circuitry includes a local memory, a tensor accelerator coupled with the local memory, the tensor accelerator configured to perform a matrix multiply and accumulate operation, and a tensor data movement accelerator configured to asynchronously transfer tensor data between a global memory coupled to the memory interface and the local memory. The tensor data movement accelerator includes circuitry configured to translate the tensor data from a first tensor format to a second tensor format.

The invention discloses rendering equipment based on three-dimensional Gaussian sputtering. The hardware architecture includes a memory interface, a pre-processing engine, a cardinality ordering engine, a rasterization engine, and the like. The preprocessing engine converts the three-dimensional Gaussian point into a two-dimensional representation and generates a key value pair containing a tile identifier and depth information; the cardinal number sorting engine performs staged efficient sorting through a parallel processing mechanism and a BRAM alternate working mode; and the rasterization engine performs rendering processing by adopting a full-pipeline design and an early-stage stopping mechanism. According to the method, parallel execution of depth sequencing and rasterization is achieved, memory access and calculation redundancy are reduced through optimized data flow design, an efficient and low-power-consumption hardware acceleration solution is provided for three-dimensional Gaussian sputtering rendering, and the method is particularly suitable for application scenes such as virtual reality, games and scientific visualization requiring real-time rendering.

This disclosure describes systems, methods, and devices related to enhanced memory integration. The device may include a compute chiplet configured as a System-on-a-Chip (SoC). The device may include a logic die circuitry coupled to the compute chiplet through a high-speed link. The device may include a memory interface that connects the logic die circuitry to on-package memory. The device may include control circuitry within the logic die circuitry configured to treat the on-package memory as a memory-side cache for an off-package memory. The device may dynamically migrate memory pages between the on-package memory and the off-package memory based on memory access patterns. The device may facilitate efficient data management, optimize memory utilization, and support scalable memory architectures for improved performance.

The invention discloses a prototype verification method of a DDR4 controller in the technical field of chip verification, the method is applied to a prototype verification platform, a DDR controller and a PHY module in a chip to be verified are matched on the prototype verification platform, and the PHY module integrates a DFI to phy only interface module and a standalone PHY only block module through a python script; the prototype verification method comprises the steps that in response to a verification instruction received by a DDR controller, the DDR controller generates a control instruction according to the verification instruction and sends the control instruction to a DFI to phy only interface module; in response to the control instruction received by the DFI to phy only interface module, the DFI to phy only interface module converts the control instruction from a DFI protocol to a target control instruction of a PHY protocol, and sends the target control instruction to the standalone PHY only block module; in response to the control instruction received by the standalone PHY only block module, the standalone PHY only block module sends a target control instruction to a DDR particle externally connected with the prototype verification platform, so that read-write and verification with the DDR particle are realized; according to the method, the DDR memory interface IP prototype verification code coverage rate can be improved.

An apparatus may include a die including a memory interface, a die-to-die (D2D) circuit comprising a D2D interface, and an intermediate section connected between the memory interface and the D2D interface, wherein the intermediate section comprises a transaction converter. The intermediate section may be configured to transfer data through the D2D interface using a protocol. The D2D interface may be configured to transfer data using flow control. The D2D interface may be configured to transfer data using a raw format.

One embodiment provides a graphics processor comprising a memory interface and a processing cluster array including a plurality of processing resources interconnected via a switched interconnect network, at least one of the plurality of processing resources including a matrix accelerator configured to execute an instruction to perform a multi-dimensional sparse matrix multiply and accumulate operation having input in a sparse microscaling format including merged sparsity and scaling metadata.

A system may include one or more memory devices configured at least in part as system memory; a memory interface; and at least one circuit configured to perform one or more operations including receiving a request to configure memory for the one or more memory devices; using the memory interface to connect a memory device to the one or more memory devices; and configuring the memory device to operate as system memory. In some aspects, using the memory interface includes enabling the memory interface, where enabling the memory interface allows the memory device to be added to the one or more memory devices. In some aspects, using the memory interface and configuring the memory device are performed while the system remains in a powered-on state.

The invention relates to a tensor data movement accelerator. One embodiment provides a graphics processor comprising a memory interface and a graphics core cluster comprising a plurality of graphics cores and tensor processing circuitry. The tensor processing circuit includes: a local memory; a tensor accelerator coupled with the local memory, the tensor accelerator configured to perform a matrix multiply-accumulate operation; and a tensor data movement accelerator configured to asynchronously transfer tensor data between a global memory and a local memory coupled to the memory interface. The tensor data moving accelerator includes circuitry configured to convert tensor data from a first tensor format to a second tensor format.

One embodiment provides a multi-chiplet graphics processor comprising a plurality of chiplets, where a chiplet of the plurality of chiplets comprise a memory interface, processing resources configured to execute threads of a kernel, and thread dispatch circuitry to facilitate dispatch of threads of the kernel to the processing resources. The processing resources are configured to execute threads of a first kernel, receive dispatch of threads of a second kernel for execution before completion of the first kernel as threads of the first kernel retire, execute a first phase of the second kernel during completion of execution of the first kernel, via a thread of the first kernel, signal an event via an uncached write to a global memory, and execute a second phase of the second kernel based on detection of the event via an uncached read from the global memory.

A system in package platform includes a processor chip having a runtime processor core, an accelerator core and a processor-memory interface exposed on a chip-to-chip bonding surface, a first memory chip such as 3D NAND flash memory storing a collection of executable models of inference engines, and a second memory chip storing weights of a selected executable model. The second memory chip can comprise a nonvolatile, random access memory, such as phase change memory. Direct vertical connections such as via-to-via connections, are provided between the processor chip and the second memory chip.

The present disclosure belongs to the technical field of storage chip designs. Disclosed are a memory module and an electronic device. The memory module includes at least two memory expander controller (MXC) chips, a peripheral component Interconnect express (PCIe) golden finger, a multichannel input / output (MCIO) connector, and a dual inline memory module (DIMM), wherein the MXC chips are connected to the DIMM through a double data rate 5 (DDR5) synchronous dynamic random access memory (DRAM) interface controller port, a compute express link (CXL) port of at least one of the MXC chips interacts with an external device through the PCIe golden finger, and the CXL port of at least one of the MXC chips interacts with the external device through the MCIO connector. The present disclosure may improve the memory capacity of the memory module.

The invention discloses a CXL-containing memory page placement system, and relates to the technical field of memories. Comprising a memory cold and hot page detection module and a memory migration module which are connected in sequence; the memory cold and hot page detection module is used for collecting memory access events, generating a page heat map based on the collected memory access events, and analyzing page types and page locality; the memory migration module is used for identifying and distributing cold and hot memory interfaces. According to the method, the use performance of the memory can be optimized and improved, and the method has good market prospects and application value.

A memory system includes a memory interface including a first sub-channel interface associated with a first plurality of memory banks and a first plurality of processor in memory (PIM) blocks and further including a second sub-channel interface associated with a second plurality of memory banks and a second plurality of PIM blocks. During a particular mode of operation associated with the memory system, the first sub-channel interface is configured to communicate, with a host device, one or more memory access commands associated with the first plurality of memory banks. During the particular mode of operation, the second plurality of PIM blocks are configured to perform, concurrently with communication of the one or more memory access commands, one or more PIM operations associated with the second plurality of memory banks. The second sub-channel interface is configured to be disabled during the particular mode of operation.

An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package. The integrated circuit may include a communication interface including a serializer / deserializer (SerDes) interface; a fabric adapter communicatively coupled to the communication interface; a plurality of inference engine clusters, each inference engine cluster including a respective memory element and / or memory interface; and a data interconnect communicatively coupling each respective memory element and / or memory interfaces of the plurality of inference engine clusters to the fabric adapter. The fabric adapter may be configured to facilitate remote direct memory access (RDMA) read and write services and / or datagram communication over a cell-based switch fabric to and from the respective memory elements and / or memory interfaces of the plurality of inference engine clusters via the data interconnect.

A memory device standby procedure can include idling a first memory device in a low-power standby mode, the first memory device coupled to a memory interface that couples multiple memory devices to a host and includes a command line (CA) and a standby exit line (EX), and the first memory device can include a primary die coupled to multiple secondary dies using an intra-package bus. At the first memory device, the procedure can include waking receiver circuitry on the primary die in response to a state change on the standby exit line, and sampling the command line using logic circuitry on the primary die. When a wakeup message on the command line comprises a chip identification that corresponds to the first memory device, the procedure can include initiating a standby exit procedure for the first memory device.

The invention relates to speculative execution of kernel programs in a chiplet-based architecture. One embodiment provides a multi-chiplet graphics processor comprising a plurality of chiplets, where a chiplet of the plurality of chiplets comprises a memory interface; a processing resource configured to execute a thread of the kernel; and a thread dispatch circuitry module to facilitate dispatch of threads of the kernel to the processing resources. The processing resource is configured to: execute a thread of the first core; when the threads of the first core are revolved, receiving the dispatch of the threads of the second core for execution before the first core is completed; executing the first stage of the second core during execution completion of the first core; signaling, via a thread of the first core, an event via an uncached write to the global memory; and performing a second stage of the second kernel based on the detection of the event via the uncached read from the global memory.

A system includes a substrate comprising a first circuit. The system also includes an integrated circuit formed in a first die disposed on the substrate. The integrated circuit includes at least a processor, a controller, and a first memory interface. The first memory interface is located in a first edge of the first die and is configured to couple to the first circuit. The system also includes a first buffer circuit formed in a second die disposed on the interposer substrate adjacent to the first edge of the first die. The first buffer circuit includes a second memory interface configured to couple to the first connection circuit. The system further includes multiple memory modules disposed on the second die. Each of the multiple memory modules at least partially share the second memory interface to communicate with the integrated circuit.

Systems and methods for memory replay protection are disclosed. In an example, a system in the form of a device includes a processor, and a replay protection circuit coupled to the processor and including a memory interface circuit, wherein the replay protection circuit is configured to generate a message authentication code (MAC) from at least one block of data and to access the at least one of block of data via the memory interface circuit using ciphertext that is generated by the replay protection circuit in response to a plaintext memory address received from the processor.

An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package. The integrated circuit may include a communication interface including a serializer / deserializer (SerDes) interface; a fabric adapter communicatively coupled to the communication interface; a plurality of inference engine clusters, each inference engine cluster including a respective memory element and / or memory interface; and a data interconnect communicatively coupling each respective memory element and / or memory interfaces of the plurality of inference engine clusters to the fabric adapter. The fabric adapter may be configured to facilitate remote direct memory access (RDMA) read and write services and / or datagram communication over a cell-based switch fabric to and from the respective memory elements and / or memory interfaces of the plurality of inference engine clusters via the data interconnect.

One embodiment provides a graphics processor comprising a memory interface, a graphics core cluster including a plurality of graphics cores, and an interconnect fabric to interconnect a plurality of hardware clients including the plurality of graphics cores. The interconnect fabric include a plurality of fabric ports coupled with the plurality of graphics cores. A fabric port is configured to limit bandwidth available to an associated graphics core via a bandwidth throttler circuit coupled with the fabric port.

The name of the invention is combining MX and sparsity representation. One embodiment provides a graphics processor comprising a memory interface and a processing cluster array comprising a plurality of processing resources interconnected via a switched interconnect network, at least one of the plurality of processing resources comprising a matrix accelerator, the matrix accelerator is configured to execute instructions to perform multi-dimensional sparse matrix multiplication and accumulation operations with inputs in a sparse microscaling format that includes merged sparsity and scaling metadata.

In a computer-implemented method for a context-aware personal application memory (PAM), using an Application Memory Interface (AMIF) and to create captured data from one or more software applications, data related to user actions with the one or more software applications is captured. Using the AMIF and to create enhanced data, the captured data is enhanced with metadata, data, and semantic relations. Using the AMIF and to create filtered data, the enhanced data is filtered. The filtered data is sent by the AMIF to a personal application memory (PAM).

A storage device includes a nonvolatile memory device including a memory cell array and a storage controller to control the nonvolatile memory device. The memory cell array includes word-lines, memory cells and word-line cut regions dividing the word-lines into memory blocks. The storage controller includes an error correction code (ECC) engine including an ECC encoder and a memory interface. The ECC encoder performs a first ECC encoding operation on each of sub data units in user data to generate parity bits and generate a plurality of ECC sectors, selects outer cell bits to be stored in outer cells to constitute an outer ECC sector including the outer cell bits and performs a second ECC encoding operation on the outer ECC sector to generate outer parity bits. The memory interface transmits, to the nonvolatile memory device, a codeword set including the ECC sectors and the outer parity bits.

One embodiment provides a graphics processor comprising a memory interface and a processing resource coupled with the memory interface. The processing resource including a mixed format functional unit configured to receive an integer input and a floating-point input, perform a fused format conversion multiply operation on the integer input and the floating-point input to generate a floating-point result, and output the floating-point result.

The invention provides a multi-core processor chip and a storage access method and device of the multi-core processor chip, and relates to the technical field of computer processors, the multi-core processor chip comprises at least one processor core, the processor core comprises a general processor core, a first address space mapping module and a first core interconnection interface, the universal processor core supports high-speed cache consistency; at least one input / output core grain, wherein the input / output core grain comprises a memory interface, a directory, a second address space mapping module and a second core grain interconnection interface; both the first address space mapping module and the second address space mapping module store an address space mapping table, and the address space mapping table stores a mapping relationship between a memory address accessed by a processor core grain and a memory interface of an input / output core grain; the directory stores cache consistency information of the cache blocks corresponding to the memory interfaces of the input / output core grain and other input / output core grains corresponding to the directory.

The invention provides a development board based on a secure real-time bus SRB chip, and relates to the technical field of power electronics. The development board comprises any one or more of an SRB real-time single-twisted pair 100M Ethernet interface, an SRB real-time standard gigabit Ethernet interface, an SRB external memory interface EMIF parallel interface, an SRB serial peripheral interface SPI serial interface, an SRB configuration universal asynchronous receiver / transmitter UART serial port, an ARM RS422 serial port, an RS232 serial port, a CAN interface, an ARM UART serial port, an ARM 100M network port, an ARM JTAG interface and a power supply interface. According to the method, not only is the security bus characteristic test of the SRB chip concerned, but also other key function modules (such as an Ethernet interface, a memory interface, a serial peripheral interface and the like) are covered, so that a developer can more comprehensively evaluate the overall performance and reliability of the SRB chip, not just the security bus part.

The invention relates to an AI processor and method based on storage and calculation integration, three-dimensional integration and operator separation. The AI processor comprises a storage layer; the calculation layer and the storage layer are stacked in the vertical direction through a three-dimensional integrated connection structure, and a three-dimensional integrated high-speed channel is generated and used for executing calculation tasks in a large language model; the standardized memory interface is used for being connected with an external main control chip; the calculation task comprises a pre-filling stage and a decoding stage; the scheduling module configures the main control chip to interact data with the storage layer through the standardized memory interface so as to execute the pre-filling stage; the scheduling module configures the computing layer to interact data with the storage layer through the three-dimensional integrated high-speed channel so as to execute the decoding stage, the pre-filling stage is processed by utilizing the large computing power advantage of a main control chip, and the decoding stage is processed by utilizing the three-dimensional stacked high-bandwidth advantage, so that accurate matching of the computing power and the bandwidth is realized; and the large model reasoning efficiency is obviously improved.

The invention provides a memory access system oriented to vector and matrix calculation, the system comprises a vector memory access unit, a matrix memory access unit, a vector register group and a matrix register group, the vector memory access unit is connected with a memory interface and the vector register group, reads elements of a one-dimensional data structure or a two-dimensional data structure from a memory, and stores the elements of the one-dimensional data structure or the two-dimensional data structure; vector data are generated through data reorganization operation, a matrix access unit is connected with a memory interface and a matrix register set, matrix block data of a two-dimensional data structure are read from a memory together with the matrix access unit, matrix data are generated after data reorganization, and the matrix data are broadcasted to one or more computing units according to rows or columns. And performing calculation on the matrix data and the vector data. In the memory access system, the vector memory access unit and the matrix memory access unit can load data in parallel, and the utilization rate is improved through a plurality of computing units, so that the problems of low memory access efficiency and low memory bandwidth utilization rate are solved.

In some aspects, a method may include receiving, at a memory interface of a device configured as a memory, a request using a memory access protocol to make regions of the memory assignable; and processing the request to make the region of the memory allocable. Processing the request may include making at least a portion of a storage medium of the device corresponding to a region of memory assignable and / or assigning a value to at least a portion of the storage medium corresponding to the region of memory. A device may be configured to track allocated addresses on the device, and the method may further include modifying at least one circuit such that addresses corresponding to a region of the memory may be allocated. The method may also include modifying the device to indicate that the region of memory is free, and adding the region of memory to a list of allocable memory locations.