507 results about "Memory interface" patented technology

A memory management method and apparatus, and a computing device. The method is executed by a GMEM system. When receiving a physical memory range, a memory management unit operation function, and an accelerator device address of an accelerator device, the GMEM system configures a memory management unit operation function interface for the accelerator device, and a device where the GMEM system is located is enabled to use a driver of the accelerator device to manage a memory management unit and a physical memory of the accelerator device by means of the memory management unit operation function interface for the accelerator device, so as to read and write data. In the present application, the GMEM system extends a native memory management interface of an operating system into a heterogeneous memory management interface, supporting programming based on a unified virtual address space, and memory management unit operation function interfaces are configured for different types of accelerator devices, so that the device where the GMEM system is located can support the use of different types of accelerator devices, without the need to consider the compatibility of memory interfaces of different types of accelerator devices.

Techniques are described herein for system for preserving memories and experiences through a Non-Fungible Token (NFT) engine. An example system includes one or more memories storing a set of computer-readable instructions including the NFT engine and one or more processors interfacing with the one or more memories. The one or more processors are configured to execute the set of computer-readable instructions to cause the system to: receive data of a user from a time period, and execute the NFT engine to: analyze the data to classify a memory experienced by the user during the time period based on a memory threshold, generate, for display to the user, an NFT based on the memory, and mint the NFT corresponding to the memory to a blockchain, wherein a portion of the data associated with the memory is linked to the NFT.

A computing device performs both read / write operations concurrently to a memory. Queues for read or write operations are maintained on the memory, allowing the computing device to issue concurrent read / write commands, without complex ordering / buffering circuitry. For a read operation, the memory receives the read command and buffers it in a priority order assigned thereto. The memory can perform the read command and respond with the requested response on a data bus disposed to communicate read data. For a write operation, the memory receives the write command and buffers it for processing in a priority order for that command, such as for relatively immediate processing. The memory can perform the write command using write data on a separate data bus disposed to communication write data.

Examples described herein and includes at least one processor and a direct memory access (DMA) device. In some examples, the DMA device is to: access a command from a memory region allocated to receive commands for execution by the DMA device, wherein the command is to access content from a local memory device or remote memory node. In some examples, the DMA device is to: determine if the content is stored in a local memory device or a remote memory node based on a configuration that indicates whether a source address refers to a memory address associated with the local memory device or the remote memory node and whether a destination address refers to a memory address associated with the local memory device or the remote memory node. In some examples, the DMA device is to: copy the content from a local memory device or copy the content to the local memory device using a memory interface.

One embodiment provides a graphics processor comprising a memory interface and a graphics core cluster including a plurality of graphics cores and tensor processing circuitry. The tensor processing circuitry includes a local memory, a tensor accelerator coupled with the local memory, the tensor accelerator configured to perform a matrix multiply and accumulate operation, and a tensor data movement accelerator configured to asynchronously transfer tensor data between a global memory coupled to the memory interface and the local memory. The tensor data movement accelerator includes circuitry configured to translate the tensor data from a first tensor format to a second tensor format.

The embodiment of the invention provides a solid-state memory and a memory management method, and the solid-state memory comprises a computing interconnection interface, a nonvolatile memory interface controller, a cache controller, a dynamic random access memory, a flash memory controller and a flash memory medium, the dynamic random access memory comprises a controller memory buffer area and a plurality of persistent memory areas, and instructions and data can be separated through the controller memory buffer area and the persistent memory areas to realize effective isolation of the data and the instructions.

The invention discloses rendering equipment based on three-dimensional Gaussian sputtering. The hardware architecture includes a memory interface, a pre-processing engine, a cardinality ordering engine, a rasterization engine, and the like. The preprocessing engine converts the three-dimensional Gaussian point into a two-dimensional representation and generates a key value pair containing a tile identifier and depth information; the cardinal number sorting engine performs staged efficient sorting through a parallel processing mechanism and a BRAM alternate working mode; and the rasterization engine performs rendering processing by adopting a full-pipeline design and an early-stage stopping mechanism. According to the method, parallel execution of depth sequencing and rasterization is achieved, memory access and calculation redundancy are reduced through optimized data flow design, an efficient and low-power-consumption hardware acceleration solution is provided for three-dimensional Gaussian sputtering rendering, and the method is particularly suitable for application scenes such as virtual reality, games and scientific visualization requiring real-time rendering.

The invention discloses a memory management method and device and computing equipment. The method is executed by a GMEM system, after the GMEM system receives a physical memory range, a memory management unit operation function and an accelerator device address of the accelerator device, a memory management unit operation function interface is configured for the accelerator device, and the device where the GMEM system is located is enabled to operate the function interface through the accelerator device memory management unit. And managing a memory management unit and a physical memory of the accelerator equipment by utilizing a driver of the accelerator equipment so as to read and write data. According to the GMEM system, a native memory management interface of an operating system is expanded into a heterogeneous memory management interface, programming of a unified virtual address space is supported, and memory management unit operation function interfaces are configured for various types of accelerator devices, so that the device where the GMEM system is located can support the use of the various types of accelerator devices, and the operation efficiency of the accelerator devices is improved. And the compatibility problem of memory interfaces of various types of accelerator equipment does not need to be considered.

This disclosure describes systems, methods, and devices related to enhanced memory integration. The device may include a compute chiplet configured as a System-on-a-Chip (SoC). The device may include a logic die circuitry coupled to the compute chiplet through a high-speed link. The device may include a memory interface that connects the logic die circuitry to on-package memory. The device may include control circuitry within the logic die circuitry configured to treat the on-package memory as a memory-side cache for an off-package memory. The device may dynamically migrate memory pages between the on-package memory and the off-package memory based on memory access patterns. The device may facilitate efficient data management, optimize memory utilization, and support scalable memory architectures for improved performance.

A memory controller includes a scheduler configured to generate an active command and an active address, and determine whether to issue the active command and the active address according to an output control signal; a row-hammer detector configured to generate the output control signal by checking a row-hammer possibility based on the active command and the active address; and a memory interface configured to provide the active command and the active address issued by the scheduler to a memory device.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a common substrate and a first integrated circuit (IC) chip disposed on the common substrate. The first IC chip includes a first memory interface. A second IC chip is disposed on the common substrate and includes a second memory interface. A first memory device is disposed on the common substrate and includes memory and a first port coupled to the memory. The first port is configured for communicating with the first memory interface of the first IC chip. A second port is coupled to the memory and communicates with the second memory interface of the second IC chip. In-memory processing circuitry is coupled to the memory and controls transactions between the first memory device and the first and second IC chips.

The invention discloses a prototype verification method of a DDR4 controller in the technical field of chip verification, the method is applied to a prototype verification platform, a DDR controller and a PHY module in a chip to be verified are matched on the prototype verification platform, and the PHY module integrates a DFI to phy only interface module and a standalone PHY only block module through a python script; the prototype verification method comprises the steps that in response to a verification instruction received by a DDR controller, the DDR controller generates a control instruction according to the verification instruction and sends the control instruction to a DFI to phy only interface module; in response to the control instruction received by the DFI to phy only interface module, the DFI to phy only interface module converts the control instruction from a DFI protocol to a target control instruction of a PHY protocol, and sends the target control instruction to the standalone PHY only block module; in response to the control instruction received by the standalone PHY only block module, the standalone PHY only block module sends a target control instruction to a DDR particle externally connected with the prototype verification platform, so that read-write and verification with the DDR particle are realized; according to the method, the DDR memory interface IP prototype verification code coverage rate can be improved.

An apparatus may include a die including a memory interface, a die-to-die (D2D) circuit comprising a D2D interface, and an intermediate section connected between the memory interface and the D2D interface, wherein the intermediate section comprises a transaction converter. The intermediate section may be configured to transfer data through the D2D interface using a protocol. The D2D interface may be configured to transfer data using flow control. The D2D interface may be configured to transfer data using a raw format.

One embodiment provides a graphics processor comprising a memory interface and a processing cluster array including a plurality of processing resources interconnected via a switched interconnect network, at least one of the plurality of processing resources including a matrix accelerator configured to execute an instruction to perform a multi-dimensional sparse matrix multiply and accumulate operation having input in a sparse microscaling format including merged sparsity and scaling metadata.

A system may include one or more memory devices configured at least in part as system memory; a memory interface; and at least one circuit configured to perform one or more operations including receiving a request to configure memory for the one or more memory devices; using the memory interface to connect a memory device to the one or more memory devices; and configuring the memory device to operate as system memory. In some aspects, using the memory interface includes enabling the memory interface, where enabling the memory interface allows the memory device to be added to the one or more memory devices. In some aspects, using the memory interface and configuring the memory device are performed while the system remains in a powered-on state.

The invention relates to a tensor data movement accelerator. One embodiment provides a graphics processor comprising a memory interface and a graphics core cluster comprising a plurality of graphics cores and tensor processing circuitry. The tensor processing circuit includes: a local memory; a tensor accelerator coupled with the local memory, the tensor accelerator configured to perform a matrix multiply-accumulate operation; and a tensor data movement accelerator configured to asynchronously transfer tensor data between a global memory and a local memory coupled to the memory interface. The tensor data moving accelerator includes circuitry configured to convert tensor data from a first tensor format to a second tensor format.

One embodiment provides a multi-chiplet graphics processor comprising a plurality of chiplets, where a chiplet of the plurality of chiplets comprise a memory interface, processing resources configured to execute threads of a kernel, and thread dispatch circuitry to facilitate dispatch of threads of the kernel to the processing resources. The processing resources are configured to execute threads of a first kernel, receive dispatch of threads of a second kernel for execution before completion of the first kernel as threads of the first kernel retire, execute a first phase of the second kernel during completion of execution of the first kernel, via a thread of the first kernel, signal an event via an uncached write to a global memory, and execute a second phase of the second kernel based on detection of the event via an uncached read from the global memory.

A system in package platform includes a processor chip having a runtime processor core, an accelerator core and a processor-memory interface exposed on a chip-to-chip bonding surface, a first memory chip such as 3D NAND flash memory storing a collection of executable models of inference engines, and a second memory chip storing weights of a selected executable model. The second memory chip can comprise a nonvolatile, random access memory, such as phase change memory. Direct vertical connections such as via-to-via connections, are provided between the processor chip and the second memory chip.

The present disclosure belongs to the technical field of storage chip designs. Disclosed are a memory module and an electronic device. The memory module includes at least two memory expander controller (MXC) chips, a peripheral component Interconnect express (PCIe) golden finger, a multichannel input / output (MCIO) connector, and a dual inline memory module (DIMM), wherein the MXC chips are connected to the DIMM through a double data rate 5 (DDR5) synchronous dynamic random access memory (DRAM) interface controller port, a compute express link (CXL) port of at least one of the MXC chips interacts with an external device through the PCIe golden finger, and the CXL port of at least one of the MXC chips interacts with the external device through the MCIO connector. The present disclosure may improve the memory capacity of the memory module.

The invention discloses a CXL-containing memory page placement system, and relates to the technical field of memories. Comprising a memory cold and hot page detection module and a memory migration module which are connected in sequence; the memory cold and hot page detection module is used for collecting memory access events, generating a page heat map based on the collected memory access events, and analyzing page types and page locality; the memory migration module is used for identifying and distributing cold and hot memory interfaces. According to the method, the use performance of the memory can be optimized and improved, and the method has good market prospects and application value.

A memory system includes a memory interface including a first sub-channel interface associated with a first plurality of memory banks and a first plurality of processor in memory (PIM) blocks and further including a second sub-channel interface associated with a second plurality of memory banks and a second plurality of PIM blocks. During a particular mode of operation associated with the memory system, the first sub-channel interface is configured to communicate, with a host device, one or more memory access commands associated with the first plurality of memory banks. During the particular mode of operation, the second plurality of PIM blocks are configured to perform, concurrently with communication of the one or more memory access commands, one or more PIM operations associated with the second plurality of memory banks. The second sub-channel interface is configured to be disabled during the particular mode of operation.

Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a multi-lane parallel floating-point unit and a multi-lane parallel integer unit. The multi-lane parallel integer unit includes an integer pipeline including a plurality of parallel integer logic units configured to perform integer compute operations on a plurality of input data elements and a format conversion pipeline including a plurality of parallel format conversion units configured to convert a plurality of input data elements from a first one of a plurality of datatype formats to a second one of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.

An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package. The integrated circuit may include a communication interface including a serializer / deserializer (SerDes) interface; a fabric adapter communicatively coupled to the communication interface; a plurality of inference engine clusters, each inference engine cluster including a respective memory element and / or memory interface; and a data interconnect communicatively coupling each respective memory element and / or memory interfaces of the plurality of inference engine clusters to the fabric adapter. The fabric adapter may be configured to facilitate remote direct memory access (RDMA) read and write services and / or datagram communication over a cell-based switch fabric to and from the respective memory elements and / or memory interfaces of the plurality of inference engine clusters via the data interconnect.

A memory device standby procedure can include idling a first memory device in a low-power standby mode, the first memory device coupled to a memory interface that couples multiple memory devices to a host and includes a command line (CA) and a standby exit line (EX), and the first memory device can include a primary die coupled to multiple secondary dies using an intra-package bus. At the first memory device, the procedure can include waking receiver circuitry on the primary die in response to a state change on the standby exit line, and sampling the command line using logic circuitry on the primary die. When a wakeup message on the command line comprises a chip identification that corresponds to the first memory device, the procedure can include initiating a standby exit procedure for the first memory device.

Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a plurality of processing resources. A processing resource of the plurality of processing resources includes a source crossbar communicatively coupled with a register file, the source crossbar to reorder data elements of a source operand and a format conversion pipeline to convert a plurality of input data elements specified by the source operand from a first format of a plurality of datatype formats to a second format of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.

The invention relates to speculative execution of kernel programs in a chiplet-based architecture. One embodiment provides a multi-chiplet graphics processor comprising a plurality of chiplets, where a chiplet of the plurality of chiplets comprises a memory interface; a processing resource configured to execute a thread of the kernel; and a thread dispatch circuitry module to facilitate dispatch of threads of the kernel to the processing resources. The processing resource is configured to: execute a thread of the first core; when the threads of the first core are revolved, receiving the dispatch of the threads of the second core for execution before the first core is completed; executing the first stage of the second core during execution completion of the first core; signaling, via a thread of the first core, an event via an uncached write to the global memory; and performing a second stage of the second kernel based on the detection of the event via the uncached read from the global memory.

A system includes a substrate comprising a first circuit. The system also includes an integrated circuit formed in a first die disposed on the substrate. The integrated circuit includes at least a processor, a controller, and a first memory interface. The first memory interface is located in a first edge of the first die and is configured to couple to the first circuit. The system also includes a first buffer circuit formed in a second die disposed on the interposer substrate adjacent to the first edge of the first die. The first buffer circuit includes a second memory interface configured to couple to the first connection circuit. The system further includes multiple memory modules disposed on the second die. Each of the multiple memory modules at least partially share the second memory interface to communicate with the integrated circuit.

Systems and methods for memory replay protection are disclosed. In an example, a system in the form of a device includes a processor, and a replay protection circuit coupled to the processor and including a memory interface circuit, wherein the replay protection circuit is configured to generate a message authentication code (MAC) from at least one block of data and to access the at least one of block of data via the memory interface circuit using ciphertext that is generated by the replay protection circuit in response to a plaintext memory address received from the processor.

An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package. The integrated circuit may include a communication interface including a serializer / deserializer (SerDes) interface; a fabric adapter communicatively coupled to the communication interface; a plurality of inference engine clusters, each inference engine cluster including a respective memory element and / or memory interface; and a data interconnect communicatively coupling each respective memory element and / or memory interfaces of the plurality of inference engine clusters to the fabric adapter. The fabric adapter may be configured to facilitate remote direct memory access (RDMA) read and write services and / or datagram communication over a cell-based switch fabric to and from the respective memory elements and / or memory interfaces of the plurality of inference engine clusters via the data interconnect.

One embodiment provides a graphics processor comprising a memory interface, a graphics core cluster including a plurality of graphics cores, and an interconnect fabric to interconnect a plurality of hardware clients including the plurality of graphics cores. The interconnect fabric include a plurality of fabric ports coupled with the plurality of graphics cores. A fabric port is configured to limit bandwidth available to an associated graphics core via a bandwidth throttler circuit coupled with the fabric port.