167 results about "Memory interface" patented technology

The present disclosure belongs to the technical field of storage chip designs. Disclosed are a memory module and an electronic device. The memory module includes at least two memory expander controller (MXC) chips, a peripheral component Interconnect express (PCIe) golden finger, a multichannel input / output (MCIO) connector, and a dual inline memory module (DIMM), wherein the MXC chips are connected to the DIMM through a double data rate 5 (DDR5) synchronous dynamic random access memory (DRAM) interface controller port, a compute express link (CXL) port of at least one of the MXC chips interacts with an external device through the PCIe golden finger, and the CXL port of at least one of the MXC chips interacts with the external device through the MCIO connector. The present disclosure may improve the memory capacity of the memory module.

A memory system includes a memory interface including a first sub-channel interface associated with a first plurality of memory banks and a first plurality of processor in memory (PIM) blocks and further including a second sub-channel interface associated with a second plurality of memory banks and a second plurality of PIM blocks. During a particular mode of operation associated with the memory system, the first sub-channel interface is configured to communicate, with a host device, one or more memory access commands associated with the first plurality of memory banks. During the particular mode of operation, the second plurality of PIM blocks are configured to perform, concurrently with communication of the one or more memory access commands, one or more PIM operations associated with the second plurality of memory banks. The second sub-channel interface is configured to be disabled during the particular mode of operation.

The invention provides a multi-core processor chip and a storage access method and device of the multi-core processor chip, and relates to the technical field of computer processors, the multi-core processor chip comprises at least one processor core, the processor core comprises a general processor core, a first address space mapping module and a first core interconnection interface, the universal processor core supports high-speed cache consistency; at least one input / output core grain, wherein the input / output core grain comprises a memory interface, a directory, a second address space mapping module and a second core grain interconnection interface; both the first address space mapping module and the second address space mapping module store an address space mapping table, and the address space mapping table stores a mapping relationship between a memory address accessed by a processor core grain and a memory interface of an input / output core grain; the directory stores cache consistency information of the cache blocks corresponding to the memory interfaces of the input / output core grain and other input / output core grains corresponding to the directory.

The invention relates to an AI processor and method based on storage and calculation integration, three-dimensional integration and operator separation. The AI processor comprises a storage layer; the calculation layer and the storage layer are stacked in the vertical direction through a three-dimensional integrated connection structure, and a three-dimensional integrated high-speed channel is generated and used for executing calculation tasks in a large language model; the standardized memory interface is used for being connected with an external main control chip; the calculation task comprises a pre-filling stage and a decoding stage; the scheduling module configures the main control chip to interact data with the storage layer through the standardized memory interface so as to execute the pre-filling stage; the scheduling module configures the computing layer to interact data with the storage layer through the three-dimensional integrated high-speed channel so as to execute the decoding stage, the pre-filling stage is processed by utilizing the large computing power advantage of a main control chip, and the decoding stage is processed by utilizing the three-dimensional stacked high-bandwidth advantage, so that accurate matching of the computing power and the bandwidth is realized; and the large model reasoning efficiency is obviously improved.

The invention provides a memory access system oriented to vector and matrix calculation, the system comprises a vector memory access unit, a matrix memory access unit, a vector register group and a matrix register group, the vector memory access unit is connected with a memory interface and the vector register group, reads elements of a one-dimensional data structure or a two-dimensional data structure from a memory, and stores the elements of the one-dimensional data structure or the two-dimensional data structure; vector data are generated through data reorganization operation, a matrix access unit is connected with a memory interface and a matrix register set, matrix block data of a two-dimensional data structure are read from a memory together with the matrix access unit, matrix data are generated after data reorganization, and the matrix data are broadcasted to one or more computing units according to rows or columns. And performing calculation on the matrix data and the vector data. In the memory access system, the vector memory access unit and the matrix memory access unit can load data in parallel, and the utilization rate is improved through a plurality of computing units, so that the problems of low memory access efficiency and low memory bandwidth utilization rate are solved.

A system with an interface for remote memory. In some embodiments, the system includes: an interface circuit having: a first interface, configured to be connected to a processing circuit; and a second interface, configured to be connected to memory, the first interface including a cache coherent interface, and the second interface being different from the first interface.

The invention discloses a verification system of an FSMC multi-memory interface based on a UVM, and belongs to the technical field of chip verification. The verification system of the FSMC multi-memory interface based on the UVM comprises a test layer, a simulation instruction definition layer, an AHB bus interface component, an assertion inspection component and an external memory interface component. The problems that in the prior art, a single memory is mainly connected for verification, only a single protocol can be verified, the verification means is limited, and the efficiency and the coverage rate are not high are solved, the transmission type of the AHB is defined in the environment configuration component, therefore, the verification diversity is improved, the verification requirements for verifying different memory interfaces are well met, and the verification efficiency is improved. According to the interface protocol verification method and device, the randomized excitation and self-checking function conforming to the protocol can be generated, the verification comprehensiveness is greatly improved, the pertinence and correctness of the verified module are greatly improved, the verification efficiency is improved, the code cost is reduced, and the accuracy of interface protocol verification is improved.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, an integrated circuit (IC) base die is disclosed. The IC base die is configured to couple to a stack of memory die and includes a first port including a die-to-die (D2D) interface to couple to an IC device. A second port includes a memory interface to access a memory other than the stack of memory die. Memory control circuitry controls memory access operations directed to the memory other than the stack of memory die.

Various aspects relate to a memory module including: a memory interface; a non-volatile storage device for persistently storing data; a non-volatile memory device providing a write first in first out, FIFO, buffer in hardware, the write FIFO buffer being configured to receive, via the memory interface, and to store packets associated with one or more atomic transactions, wherein each of the one or more atomic transactions includes a respective plurality of packets and indicates corresponding data to be written to the memory module; a memory controller configured to write the corresponding data of an atomic transaction of the one or more atomic transactions to the memory module in the case that the write FIFO buffer stores the respective plurality of packets of the atomic transaction.

Techniques discussed herein can facilitate the use of reference signals in active TCI switching. One example aspect is a user equipment (UE), comprising: a memory interface; and processing circuitry communicatively coupled to the memory interface and configured to: receive a physical downlink shared channel (PDSCH) message that includes an activation command indicating a target transmission configuration indicator (TCI) state; decode the activation command within a decoding period, where the decoding period is a time period allocated for the UE to decode the activation command; receive a TCI resource where the TCI resource is a reference signal; perform time and frequency tracking associated with the target TCI state according the TCI resource; and switch to the target TCI state after performing time and frequency tracking.

A computing system is disclosed, comprising a host computer and multiple CGRPs (coarse-grained reconfigurable architecture processors) connected to the host computer through external communication links. Each CGRP includes an internal network, external interface circuits, memory interface circuits, arrays of configurable units, hang detection circuits, force-quit controllers, and a network recovery circuit with control registers. The host computer is programmed to configure and execute applications across the arrays of configurable units in both CGRPs. In case of a hang detection in one CGRP, the network recovery circuit initiates a force quit process and notifies the host computer. Additionally, the network recovery circuit compares application IDs and halts execution in the other CGRP if necessary. This system provides efficient failure tolerance and recovery mechanisms for parallel processing applications.

Techniques are disclosed relating to a shared control bus for communicating between primary control circuitry and multiple distributed graphics processor units. In some embodiments, a set of multiple graphics processor units including at least first and second graphics processors on different semiconductor substrates that are packaged in a multi-chip module, where the first and second graphics processors are coupled to access graphics data via respective memory interfaces. The shared workload distribution bus may include: one or more interfaces between respective graphics processors on the same semiconductor substrate and at least one cross-substrate interface between the different semiconductor substrates. Workload distribution circuitry may transmit, via the shared workload distribution bus, control data that specifies graphics work distribution to the multiple graphics processor units. Packet control circuitry may modify packets from at least one of the one or more interfaces for transmission via the cross-substrate interface.

Methods and apparatus for on-package accelerator complex (AC) for integrating accelerator and IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.

The present disclosure relates to assistance indication of resource reservation in sidelink. Techniques discussed herein can facilitate assistance indication of resource reservation in sidelink. One example aspect is a user equipment (UE) comprising: a memory interface; and processing circuitry communicatively coupled to the memory interface and configured to: generate a physical sidelink control channel (PSCCH) message related to a first stage sidelink control information (SCI), wherein the first stage SCI comprises a first indication related to a SCI assistance request; and cause transmission of the first stage SCI.

Memory module, computing device, and methods of reading and writing data to the memory module are disclosed. A memory module, comprises one or more dynamic random-access memories (DRAMs); and a processor configured to select a Central Processing Unit (CPU) or the processor to communicate with the one or more DRAMs via a memory interface.

Techniques discussed herein can facilitate generation of performance managements associated with one or more of PDU (Protocol Data Unit) session(s) and / or N4 session(s). One example embodiment is an apparatus configured to be employed in a service provider for a component of a Fifth Generation Core Network (5GC), comprising: a memory interface; and processing circuitry configured to: obtain one or more raw performance measurements from the component of the 5GC; and generate one or more performance measurements for the component of the 5GC based on the one or more raw performance measurements, wherein the one or more raw performance measurements and the one or more performance measurements are associated with one or more of a PDU (Protocol Data Unit) session or a N4 session.

The utility model relates to a memory and an electronic device, the memory comprises a memory chip and a logic chip, the memory chip and the logic chip are packaged by adopting a three-dimensional packaging technology, the memory further comprises an interface circuit, the interface circuit is used for realizing communication between the memory and an external system, and the interface circuit is used for realizing communication between the memory and the external system. The interface circuit is arranged on the storage chip. Compared with an implementation mode that an interface circuit is generally arranged in a logic chip in the prior art, the memory provided by the utility model has the advantages that the interface circuit is arranged in the memory chip, and the interface circuit is a standard memory interface, so that the design based on the memory chip does not need process migration; the design complexity and design difficulty caused by interface circuit process migration can be avoided, and the architecture iteration speed is greatly increased.

Disclosed is a SoC. The SoC communicating with a memory device includes a memory interface that exchanges a command and data with the memory device, and a control logic circuit that transmits a clock signal and a plurality of data signals to the memory device through the memory interface. The control logic circuit sequentially transmits pieces of first data with different delay times to the memory device through the memory interface based on a pre-stored first edge code, continuously transmits, to the memory device, a plurality of read commands for reading the pieces of first data stored in the memory device from the memory device, and obtains a first delay value including an extent, to which the pieces of first data are delayed, based on a data pattern of each of pieces of first reception data read from the memory device in response to the plurality of read commands.

A video conference system, device, and method are disclosed. The device comprises a memory, an interface, and one or more processors. The one or more processors comprise a first neural network configured to operate according to a first machine learning (ML) model. The one or more processors are configured to obtain audio data. The one or more processors are configured to process, using the first neural network, the audio data for provision of a first model output comprising a direction of arrival estimation. The one or more processors are configured to obtain camera data. The one or more processors are configured to process the camera data for provision of a video output. The one or more processors are configured to determine an uncertainty parameter based on the first model output and control the processing of the camera data for provision of the video output based on the uncertainty parameter.

Various aspects relate to a memory module including: a memory interface; a storage device for persistently storing data; a non-volatile memory device providing a memory storage for persistently storing data and providing a write buffer configured to receive, via the memory interface, and to store corresponding data to be written to the memory module; and a memory controller configured to write the corresponding data selectively from the write buffer to the storage device or to the memory storage.

The application discloses a kind of arbitration methods for memory interface, including detecting the state of memory interface;If the state of memory interface is idle state, when receiving at least one host sent access request, according to the priority level of each host self, the request of highest priority is executed first, after executing current access request, if there is other access request, the state of memory interface is converted from idle state to non-idle state;If the state of memory interface is non-idle state, for each host's access request, in addition to the priority of host self, there is also a software configurable access intensity that drops with access time, according to the continuous request blocking bit selected by user, the request of host currently executed, the access intensity corresponding to access request blocks the response of other host and / or allows to be higher priority request of other host to be robbed. So that arbitration mechanism function is more powerful, with real-time, more easily meet user demand.

A reconfigurable inference platform implemented in a system-in-package configuration is provided. The system in the reconfigurable inference platform includes a processor chip, a first memory chip storing a set of executable models for inference engines, and a second memory chip storing weights for a selected executable model. The processor chip has a running processor core, an accelerator core, and a processor-memory interface exposed on a chip-to-chip bonding surface. The first memory chip is, for example, a three-dimensional NAND flash memory. The second memory chip can include a non-volatile random access memory, such as a phase change memory. A direct vertical connection structure, such as a via-to-via connection structure, is provided between the processor chip and the second memory chip.

A memory device including a memory interface chip and an operating method thereof are provided. In some embodiments, the memory device includes a controller integrated circuit, a first memory die, and a first converter integrated circuit having a first external interface and a second external interface, the first external interface being a serial interface, the first external interface being connected to the controller integrated circuit, and the second external interface being a memory interface connecting the first converter integrated circuit to the first memory die.

DOA estimation methods, apparatuses, and systems utilizing uncertainty quantification are disclosed. The apparatus includes a memory, an interface, and one or more processors. The one or more processors include a first neural network configured to operate according to a first machine learning (ML) model. The one or more processors are configured to obtain audio data. The one or more processors are configured to process the audio data using the first neural network to provide a first model output containing a direction of arrival estimate. The one or more processors are configured to obtain camera data. The one or more processors are configured to process the camera data to provide a video output. The one or more processors are configured to determine an uncertainty parameter based on the first model output and control the processing of the camera data to provide the video output based on the uncertainty parameter.

A large language model (LLM)-based machine learning (ML) system-on-chip (SoC) is described. The LLM-based SoC includes a first LLM processing block. The LLM-based SoC also includes a first memory controller coupled to the first LLM processing block. The LLM-based SoC further includes a first physical layer (PHY) memory interface coupled to the first LLM processing block through the first memory controller. The LLM-based SoC further includes a memory coupled to the first PHY memory interface as a first data channel.

A non-volatile main memory subsystem includes a main memory interface for communicating with a host system; static random-access memory (SRAM); first non-volatile memory (NVM); and second NVM having storage capacity that is at least ten times the storage capacity of the first NVM. The first NVM has write endurance that is at least ten times, and typically at least one hundred times, the write endurance of the second NVM, erase speed that is at least twice as fast as erase speed of the first NVM, and / or programming speed that is at least ten times as fast, and typically at least a hundred times as fast, as programming speed of the second NVM. The main memory subsystem includes a first level cache resident in the SRAM, a second level cache resident in the first NVM, and a controller for read / write control and maintaining one or more address mapping tables.

Methods, systems, and devices for an interface layout for stacked memory architectures are described. A memory interface block may interface a plurality of memory dies to a host controller. The memory interface block may include an interface block coupled with multiple memory dies, which may be stacked on the memory interface block using through-silicon-vias. The memory interface block may include controllers, datapath blocks, and interface blocks associated with each memory die. As such, the memory interface block may perform functions such as queueing, ECC, and performing row repair and column repair procedures. In some examples, a layout for the memory interface block may include pairing controllers for at least two memory devices, such that a pair of controllers may share a command port to a pair of memory dies. Further, the memory interface block may include interfaces to the host controller that are different from the interface to each memory die.

A system includes an interface, a processor, and a memory. The interface is configured to receive a version of a model from a model registry. The processor is configured to store the version of the model, start a process running the version of the model, and update a proxy with version information associated with the version of the model, wherein the updated proxy indicates to redirect an indication to invoke the version of the model to the process. The memory is coupled to the processor and configured to provide the processor with instructions.

The embodiment of the invention relates to the technical field of integrated circuit design, in particular to an access system, a memory system and an access method for three-dimensional data access. The access system comprises a configuration register unit, an address generation unit, a data assembling and splitting unit and a double-pipeline controller, the address generation unit is connected with the configuration register unit and the double-pipeline controller, and is used for calculating a one-dimensional physical address based on a target index value input by a user and sending the one-dimensional physical address to the double-pipeline controller; the dual-pipeline controller is connected to the memory interface and is used for independently managing a read flow and a write flow based on a user read-write request so as to perform read-write in the memory based on a one-dimensional physical address; the data assembling and splitting unit is connected to the double-assembly-line controller and used for carrying out data assembling and splitting in the read-write process and then sending the data to the double-assembly-line controller. According to the scheme, three-dimensional data indexing is achieved in a hardware mode, and the data processing efficiency and the system flexibility can be improved.

An integrated circuit formed on (i) a single semiconductor die or (ii) a plurality semiconductor dies that are integrated into a single package. The integrated circuit may include a communication interface including a serializer / deserializer (SerDes) interface; a fabric adapter communicatively coupled to the communication interface; a plurality of inference engine clusters, each inference engine cluster including a respective memory element and / or memory interface; and a data interconnect communicatively coupling each respective memory element and / or memory interfaces of the plurality of inference engine clusters to the fabric adapter. The fabric adapter may be configured to facilitate remote direct memory access (RDMA) read and write services and / or datagram communication over a cell¬ based switch fabric to and from the respective memory elements and / or memory interfaces of the plurality of inference engine clusters via the data interconnect.