65 results about "Circuit delay" patented technology

A switching modulation circuit generates a first control signal with a duty ratio. A delay circuit delays the first control signal to generate a second control signal. A zero crossing detector detects whether an output current of a DC / DC converter is smaller than a threshold in a rectification interval, and generates a third control signal. A monitoring circuit detects a reverse-flow possibility of the output current, and generates a fourth control signal. A delay time of the delay circuit is set shorter than the delay time of the zero crossing detector. When the reverse-flow possibility does not exist, and the third control signal has transitioned to indicate that the output current is smaller than the threshold, a driver circuit turns off both first and second switching elements. When the reverse-flow possibility exists, and the second control signal has transitioned from an ON state to an OFF state, the driver circuit turns off both the first and second switching elements.

The invention belongs to the technical field of laser precision machining and control, and particularly relates to a femtosecond laser single-point trigger control system and method based on subnanosecond synchronization, and the method comprises the following steps: S1, building a system synchronization clock locked with a femtosecond laser pulse signal phase; the specific mode of establishing the system synchronous clock is that phase locking is carried out on pulse synchronous signals or frequency division signals output by an internal high-frequency clock source and a femtosecond laser source through a digital phase-locked loop technology, and the low-jitter system synchronous clock which is strictly synchronous with a laser pulse sequence is generated. According to the invention, a system clock locked with a laser pulse phase can be generated through a digital phase-locked loop, and the influence of inherent frequency drift of a laser and circuit delay temperature drift is effectively overcome by combining real-time delay calculation based on a prediction algorithm and a high-resolution DDS delay line technology; the synchronization precision between the triggering moment of the single pulse and the external instruction is stabilized at the subnanosecond level, and the requirement of leading-edge application for the extreme time sequence precision is met.

To prevent power supply interruption during fail-safe control when a microcomputer of a power supply control device malfunctions.SOLUTION: The power supply control device includes a controller and a delay circuit. The controller outputs a first power hold signal to a power relay to control the power relay that supplies power to multiple control devices upon receiving either the first power hold signal or a second power hold signal. The delay circuit delays the first power hold signal for at least the time required for an external device to detect the controller malfunction when the power relay receives the second power hold signal from the external device as a fail-safe control during the controller malfunction.SELECTED DRAWING: Figure 1

A phase interpolator may include a decoding logic circuit. The decoding logic circuit may take as input an input control code and an update clock. The decoding logic circuit may generate one or more outputs which may be input to a retiming circuit. The retiming circuit may generate retimed outputs which may be input to a delay modulation circuit. The delay modulation circuit may generate a delayed clock select control signal and a delayed phase select control signal. The delayed clock select control signal and delayed phase select control signal may be input to a phase interpolator circuit and may generate an output clock based on two or more multi-phase input clocks. The delayed clock select control signal and delayed phase select control signal may eliminate overshoot and undershoot events in the output clock.

The invention provides a multilayer solving method for accelerating circuit simulation, electronic equipment and a storage medium, and the method comprises the steps: carrying out the recursion division of a circuit into sub-circuits of a plurality of hierarchies, and forming a hierarchical structure from fine to coarse; on the basis of circuit delay attributes, marking and simplifying inactive parts in each level of sub-circuit, and constructing a mapping relation between levels at the same time; based on the hierarchical structure and the mapping relation, assembling a to-be-solved linear equation set; a multi-layer class method is adopted to solve the linear equation set, and the multi-layer class method comprises the steps that smoothing is carried out on a fine layer before iteration, a residual error is transmitted to a coarse layer, a direct method is adopted to solve the coarsest layer, and then a solving result is extended back to the fine layer and smoothing is carried out after iteration; and repeating the solving step of the multi-layer class method until the linear equation set converges. The system of linear equations is established based on a multi-level circuit structure and is solved by using a multi-level method, so that the solving time and memory occupation of the system of linear equations in circuit simulation are greatly reduced.

The invention belongs to the technical field of display, and particularly relates to a display control method, a time schedule controller and a display panel. Comprising the following steps: acquiring a current starting voltage value and a current common voltage value output by a power management circuit in a startup or shutdown process of the display panel; when the current starting voltage value is the valid voltage and the current common voltage value is the invalid voltage, obtaining a target time difference of the current common voltage value from the invalid voltage to the valid voltage; a clock driving signal is adjusted according to the target time difference, so that the gate driving circuit delays opening of pixel rows in the display panel according to the clock driving signal; or / and adjusting the data output time sequence according to the target time difference, so that the data driving circuit delays the output of the data signal according to the data output time sequence. According to the invention, the splash screen phenomenon of the display panel during startup and shutdown is effectively improved.

A phase-locked loop (PLL) circuit, an optoelectronic system, and an electronic device are disclosed. The PLL circuit includes: a signal processing circuit for converting the output signal of the laser into a difference frequency signal; a dual frequency and phase detector circuit configured to output a first error correction signal and a second error correction signal with opposite polarity to the first error correction signal based on the difference frequency signal output by the signal processing circuit; and a modulation circuit configured to perform calculations on the pre-correction signal and either the first or second error correction signal to obtain a modulation signal, the modulation signal being used to control the driving of the laser to modulate the laser output. By using two frequency and phase detectors to output the first and second error correction signals with only opposite polarities, the polarity reversal circuit in the prior art is eliminated, reducing the overall circuit delay and improving circuit performance.

A power supply semiconductor integrated circuit includes a first abnormality detection circuit, a second abnormality detection circuit, a delay circuit that delays an output of the first abnormality detection circuit and an output of the second abnormality detection circuit, and a latch circuit that takes in and holds an output of the delay circuit. The delay circuit includes a constant current source that charges a delay capacitor, a switching unit that discharges the delay capacitor, and a voltage comparison circuit that compares a charged voltage of the delay capacitor with a predetermined voltage. The charging of the delay capacitor is started in accordance with a change in a state indicating an abnormality in the output of the first abnormality detection circuit or an abnormality in the output of the second abnormality detection circuit. When the voltage comparison circuit determines that the charged voltage of the delay capacitor reaches the predetermined voltage, an output is changed, and the delay capacitor is discharged by taking the output into the latch circuit.

The invention discloses a communication circuit and a communication system. The communication circuit comprises a controller, a serial transceiver chip, a signal conversion circuit, a unidirectional conductive circuit, a delay circuit and a bias circuit. The signal conversion circuit outputs an inversion signal of the serial sending pin. And the delay circuit is used for delaying the signal and the inversion signal of the serial sending pin. The rising time of the signal for receiving the enable pin is earlier than the rising time of the signal for transmitting the enable pin, the rising time of the signal for transmitting the enable pin is earlier than the falling time of the signal for transmitting the data input pin, and the falling time of the signal for transmitting the enable pin is later than the rising time of the signal for transmitting the data input pin. The falling time of the signal receiving the enable pin is later than the falling time of the signal transmitting the enable pin. The biasing circuit pulls up the first differential signal pin and pulls down the second differential signal pin. Through the above mode, serial communication can be realized based on the two pins of the controller so as to save I / O resources.

The invention discloses a half-cycle time sequence repairing method and system of a circuit delay locked storage device. The method comprises the following steps: detecting whether installation time violation or holding time violation exists in the digital circuit design or not; when the time sequence violation exists and cannot be conventionally repaired, verifying whether the time sequence margin of the violation path meets a calling condition or not; if yes, part of clock cycle time is called through the barrier-free passing characteristic of the circuit delay lock storage device in the high-level stationary circuit period, and half-cycle cycle time calling repair based on the circuit delay lock storage device is carried out on a violation path, specifically, for installation time violation, an end device is replaced; for holding time violation, a reverse trigger device is inserted. Through the half-cycle period time calling and differentiation strategy, the technical bottleneck of a traditional method is broken through, and a final solution is provided for time sequence violation which cannot be repaired by a conventional method in an extreme design environment.

The application provides a signal delay setting circuit, an isolation integrated circuit and a power conversion circuitry. The isolation integrated circuit receives a first power voltage, receives a first input signal and a second input signal via two signal input terminals respectively, and outputs an output signal generated according to the first input signal and the second input signal. When the first power voltage is within a predetermined voltage range, the signal delay setting circuit generates a voltage difference across the two signal input terminals and calculates a delay time according to the voltage difference. When the first power voltage is greater than an upper limit of the predetermined voltage range, the signal delay setting circuit delays the first input signal or the second input signal according to the delay time to control the duty ratio of the output signal.

The air conditioner comprises an alternating current input port, a rectifying circuit, a PFC circuit, a load and a sampling circuit used for collecting the current of the PFC circuit, the PFC circuit comprises a switching device, the controlled end of the switching device receives a PWM signal from a controller, the sampling circuit comprises a filtering device, and the controller is configured to receive the PWM signal through the filtering device. When the duty ratio of the PWM signal is larger than a first preset threshold value and smaller than a second preset threshold value, it is judged that the difference between the sampling current and the working current in the reference time exceeds a set threshold value, the deviation time is set as a first parameter, and the starting time of the first level of the PWM signal is defined as a starting point; the sampling circuit samples the current of the switching device based on the starting point passing through the reference time and the deviation time for controlling the PFC circuit. By judging the size of the duty ratio and the circuit delay condition, the current sampling moment is dynamically adjusted, the difference between a sampling value and an actual value is reduced, and the sampling accuracy is improved.

The utility model provides a three-phase circuit for contact arc extinction. The three-phase circuit comprises a contact delay circuit and three trigger circuits, the contact delay circuit comprises a coil MJ; the three trigger circuits are respectively and correspondingly arranged on an A-phase circuit, a B-phase circuit and a C-phase circuit of the power distribution system; each trigger circuit is connected with the three-phase circuit corresponding to each trigger circuit through two terminals; a contact switch KM1 is arranged between the two terminals; the contact switches KM1 of the A-phase circuit, the B-phase circuit and the C-phase circuit correspond to the coil MJ in position; when the three-phase circuit carries out power supply, the three trigger circuits are conducted before the contact delay circuit, and after the contact delay circuit is conducted, the coil MJ can close the contact switch KM1 of the A-phase circuit, the B-phase circuit and the C-phase circuit. According to the embodiment of the invention, the contact switch KM1 of the A-phase circuit, the B-phase circuit and the C-phase circuit can be delayed to be closed through the contact delay circuit, and the conversion from soft switching to hard switching of the three-phase circuit is realized through the three trigger circuits, so that the arc discharge phenomenon is eliminated.

The invention discloses a clock generation circuit for a time-interleaved ADC, and belongs to the technical field of integrated circuits. Comprising a delay circuit Delay, a frequency division module and a pulse width adjusting circuit CLKsample, the pulse width adjusting circuit CLKsample is used for generating a sampling clock signal CLKS with adjustable pulse width and inputting the sampling clock signal CLKS into the second AND gate group; the frequency division module performs frequency division on an external clock signal CLK into multiple paths, inputs the multiple paths of signals into the first AND gate group to obtain multiple intermediate clock signals, and inputs the multiple intermediate clock signals into the second AND gate group; the second AND gate group performs AND operation on the sampling clock signal CLKS and each intermediate clock signal to obtain a plurality of multi-phase clock sampling signals, and inputs the multi-phase clock sampling signals into each sub-ADC module for time-interleaved sampling and analog-to-digital conversion; and combining and synchronizing to obtain a final signal. The circuit is simple in structure, smaller in area and lower in power consumption, extremely small phase deviation exists between interleaved sampling clock signals, and meanwhile the pulse width of the sampling clock signals can be freely adjusted.

The invention discloses a high-speed Miller platform detection circuit for a GaN half-bridge gate driving chip, and relates to the technical field of power device driving. The circuit comprises a detection node, an RC series circuit, a positive pulse discharge path, a negative pulse voltage stabilization path and a signal isolation circuit. The RC series circuit couples the voltage jump delay of the floating ground to the detection node so as to generate a voltage pulse representing the starting point of the Miller platform; the positive pulse discharge module and the negative pulse clamping module are respectively connected in parallel between the detection node and the floating ground, and are used for rapidly discharging positive interference pulses and clamping negative pulses at safe voltage; and the signal isolation module is used for isolating a post-stage circuit load. The circuit is simple in structure, high in response speed and easy to integrate, the problems that a traditional detection scheme is large in delay and complex in circuit are solved, and key support is provided for a high-frequency GaN driving chip to achieve accurate active driving.

The invention discloses a signal output device with an adjustable conversion rate. The signal output device comprises a plurality of output units. The output units are connected in parallel between the input end and the output end, respectively correspond to the adjustable signal delay amount, and each output unit comprises a delay path and an output circuit. The delay path is configured to provide an adjustable signal delay amount to receive an input signal from an input end and delay the input signal, thereby generating a delayed signal. The output circuit receives the delay signal and generates an output signal to the output end. Wherein the output end outputs a total output signal according to the output signals generated by the output circuits of all the output units, and the conversion rate of the total output signal is determined by the combination of the adjustable signal delays of the output units.

The invention discloses a method for testing the DC internal resistance of a supercapacitor, and belongs to the technical field of supercapacitors. According to the scheme, the voltage value of the super capacitor is continuously collected and recorded before the super capacitor stops discharging, the sampling frequency and the preset sampling point number are determined through repeated experiments, the whole process from collection to discharging stop to discharging rebound is ensured, collection is stopped after the preset sampling point number is collected, and the sampling efficiency is improved. And obtaining a discharge cut-off voltage and a discharge rebound voltage according to the collected data, and calculating the DC internal resistance of the supercapacitor. According to the invention, single-point acquisition is replaced by continuous acquisition, errors caused by capacitor charge adjustment after circuit delay and discharge stop are avoided, and the DC internal resistance test precision of the supercapacitor is improved.

The invention provides an RGMII delay automatic compensation system and method, and the system comprises an Ethernet MAC circuit which is used for receiving and transmitting data through an RGMII interface; the sampling circuit is connected with the RGMII interface and is used for sampling a plurality of signal lines of the RGMII to obtain phase information among signals; and the delay compensation circuit is respectively connected with the high-precision sampling circuit and the Ethernet MAC circuit, and is used for calculating the delay time of each signal line according to the phase information and controlling the Ethernet MAC circuit to carry out delay compensation. According to the RGMII delay automatic compensation system provided by the invention, the problem of inconsistent signal delay caused by PCB wiring length difference is solved, and the signal integrity and the system stability of RGMII interface communication are effectively improved.

The memory device that includes a planes with memory blocks that have memory cells arranged in word lines. The memory device also includes circuitry that is configured to receive a read command for a selected memory block of the plurality of planes. The circuitry is also configured to determine a count of planes of the plurality of planes that have memory blocks undergoing a block activation process, which includes ramping the plurality of word lines to a pass voltage. In response to the count being below or equal to a predetermined threshold, the circuitry begins the block activation process for the selected memory block. In response to the count being above the predetermined threshold, the circuitry delays the block activation process for the selected memory block until the number of planes that have memory blocks undergoing the block activation process is below the predetermined threshold.

The present invention provides a signal generating circuit and operating system for waking up a specific circuit. The circuit includes a detection circuit, a delay circuit, and a judgment circuit. The detection circuit detects whether a wake-up event has occurred and generates a detection signal. The delay circuit delays the detection signal to generate a delayed signal. The judgment circuit determines whether the wake-up event is compliant based on the delayed signal and a power-off signal. If the wake-up event is compliant, the judgment circuit enables a wake-up signal to wake up the specific circuit. If the wake-up event is not compliant, the judgment circuit resets the detection circuit.

A digital-to-time converter (DTC) is disclosed. In some embodiments, the DTC includes a bias circuit, a delay circuit, and a replica. The delay circuit is operably connected to the bias circuit. Furthermore, a replica circuit is operably connected to the bias circuit, wherein the bias circuit is operable to output a supply signal for the delay circuit and the replica circuit that has a negative slope with respect to a signal level of the supply signal and temperature.

Provided are a sigma-type analog-to-digital converter and an optical sensor which are capable of suppressing an increase in sampling frequency, suppressing an increase in measurement time, and having high sensitivity. An analog / digital conversion device includes: a [sigma]-type analog / digital converter that converts an analog signal into a digital signal having a pulse width corresponding to a size of the analog signal; first to n-th delay circuits, the first delay circuit delays the digital signal to generate a first delay signal, the i-th delay circuit delays an (i-1)-th delay signal to generate an i-th delay signal, i is an integer of 2 or more and n is an integer of 2 or more; and a signal processing circuit that acquires a signal value corresponding to the magnitude from the digital signal and the first to n-th delayed signals.

A memory and its non-race high-speed single-ended readout circuit. The memory readout circuit of the memory includes a bit line pre-charge circuit, a bit line high level holding circuit, a sampling circuit, a latch and a driver. The bit line high level holding circuit is controlled by a delay control signal, so that during the process of the memory cell pulling down the bit line, the bit line high level holding circuit is delayed to turn on, thereby effectively eliminating charge competition and accelerating the bit line discharge. In addition, the data transmission path from the bit line to the output signal only passes through the sampling circuit and the driver, forming a very fast two-stage logic readout path. This application also discloses a multi-column shared architecture, which can share the latch, driver and ground switch transistor through time division multiplexing gating mechanism, while achieving high-speed reading and greatly saving chip layout area.

This invention belongs to the field of integrated circuit technology and relates to a method for fabricating a radiation-hardened fault-tolerant trigger. The method includes constructing a radiation-hardened fault-tolerant trigger using three conventional D flip-flops, an XOR gate, a 2-to-1 selector, and two delay circuits. Input data is simultaneously written to both the primary and backup D flip-flops. After a specified delay, the input data is written to the third D flip-flop and compared with the data stored in the primary D flip-flop. If they match, the data stored in the primary D flip-flop is correct, and the 2-to-1 selector chooses the data stored in the primary D flip-flop as the output data. If they differ, the data stored in the primary D flip-flop is incorrect, and the 2-to-1 selector chooses the data stored in the backup D flip-flop as the output data. With this invention, regardless of which D flip-flop malfunctions due to radiation, the radiation-hardened fault-tolerant trigger can still output the correct value.

A technique capable of improving accuracy of an amount of delay of a sampling clock is provided. A semiconductor device includes: a communication device for wired communication; a delay adder circuit capable of adjusting an amount of delay of a clock to be received or transmitted by the communication device; and a control circuit controlling the amount of delay of the delay adder circuit. The communication device is configured to set a reception period or a transmission period of a normal frame and a reception period or a transmission period of a check frame in time division, and to confirm timing margins of setup and hold between data and a clock in the reception period or the transmission period of the check frame. The control circuit is configured to set the amount of delay in the normal frame, based on a confirmation result of the timing margins.

A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.

The invention relates to a power supply control circuit with double USB (Universal Serial Bus) power supplies. The power supply control circuit comprises a USB female head connector Main USB-A with a Type-A, a USB female head connector SUB USB-C with a Type-C, a restorable fuse PTC (Positive Temperature Coefficient), an overvoltage protection chip EFUSE with an OVP (Open Voltage Platform) set to be 5.6 V, a delay circuit Delay Switch logic with a hardware delay function, a protocol chip BC1.2 supporting a USB charge of BC1.2, and a double-pole double-throw switch USB2.0 SWITCH. The Type A and the Type C can be used for power supply at the same time, and power supply of the Type C is preferential (when the double USBs are in place, the Type C is mainly used for power supply, and the Type A uses the USB2.0 data service).

An output control circuit and a voltage output circuit are provided. The output control circuit includes: a first output terminal and a second output terminal connected to a first switch and a second switch respectively, an input terminal, a first level shift circuit, a delay circuit that outputs a signal received after a delay time set longer than a delay time of the first level shift circuit, a second level shift circuit that level-shifts a signal received by an input port connected to an output port of the delay circuit and outputs a level-shifted signal, and a control circuit that outputs a signal with a signal level determined to be either a first level or a second level based on signal levels of signals received from two input ports.

The invention discloses a two-phase non-overlapping clock circuit, an application method, equipment and a storage medium. The two-phase non-overlapping clock circuit comprises a delay circuit and a clock shaping circuit, the delay circuit is used for delaying an accessed clock signal, the clock signal comprises a reference clock signal and an inverted reference clock signal, the delay circuit at least comprises a first delay circuit and a second delay circuit, and the first delay circuit and the second delay circuit comprise a delay inverter and a load capacitor connected with the delay inverter; the first delay circuit is used for generating a first delay clock signal, and the second delay circuit is used for generating a second delay clock signal; and the clock shaping circuit is connected with the first delay circuit and the second delay circuit, and is used for carrying out logic interlocking and shaping processing on the clock signal, the first delay clock signal and the second delay clock signal, and outputting a first non-overlapping clock signal and a second non-overlapping clock signal. And the non-overlapping time between the two-phase clocks can be effectively controlled.

The power converter circuit includes a control circuit, a pulse generating circuit and a power stage circuit. The power stage circuit generates an output signal at an output node in response to a pulse signal outputted from the pulse generating circuit. The control circuit includes an error amplifier circuit, a comparison circuit, a delay circuit and a detection circuit. The error amplifier circuit outputs a compensation signal in response to a reference signal and a feedback signal related to the output signal. The comparison circuit outputs a duty signal to the pulse generating circuit in response to the compensation signal and a ramp signal. The detection circuit detects a sudden change of the output signal in response to the output signal and a delayed signal generated by the delay circuit from the delayed output signal to generate a reaction signal. The control circuit uses the reaction signal to control the error amplifier circuit or the comparison circuit to change a pulse period of the pulse signal, thereby adjusting the sudden change of the output signal. By generating the reaction signal in response to the sudden change of the output signal, the control circuit changes the pulse period of the pulse signal early to avoid the output signal from having an undershoot or an overshoot.