128 results about "Circuit delay" patented technology

A clock generation circuit includes a delay-locked circuit and a duty correction circuit. The delay-locked circuit generates a delay clock signal by delaying an input clock signal and update the delay time of the input clock signal. The duty correction circuit generates a first phase clock signal and a second phase clock signal by delaying the delay clock signal, and updates the delay time of the delay clock signal. The duty correction circuit can prevent or mitigate the delay time of the input clock signal and the delay time of the delay clock signal from being updated simultaneously.

A switching modulation circuit generates a first control signal with a duty ratio. A delay circuit delays the first control signal to generate a second control signal. A zero crossing detector detects whether an output current of a DC / DC converter is smaller than a threshold in a rectification interval, and generates a third control signal. A monitoring circuit detects a reverse-flow possibility of the output current, and generates a fourth control signal. A delay time of the delay circuit is set shorter than the delay time of the zero crossing detector. When the reverse-flow possibility does not exist, and the third control signal has transitioned to indicate that the output current is smaller than the threshold, a driver circuit turns off both first and second switching elements. When the reverse-flow possibility exists, and the second control signal has transitioned from an ON state to an OFF state, the driver circuit turns off both the first and second switching elements.

A delay control circuit includes: a delay cell including a plurality of bias inverters, first RC circuits, and second RC circuits, the delay cell activates a number of first RC circuits in response to a step code, delays a signal by a delay time based on the number of the activated first RC circuits, and outputs the delayed signal; a ZQ calibrator including pull-up and pull-down circuits, the ZQ calibrator adjusts a number of activated pull-up and pull-down circuits, and inputs a pull-up and pull-down voltage, based on a calibration code to the bias inverters; and a step adjuster including a first ring oscillator including test delay cells, the step adjuster determining characteristics of the first and second RC circuits and activates a number of second RC circuits based on the characteristics and an operating frequency of the delay control circuit.

The application provides a signal delay setting circuit, an isolation integrated circuit and a power conversion circuitry. The isolation integrated circuit receives a first power voltage, receives a first input signal and a second input signal via two signal input terminals respectively, and outputs an output signal generated according to the first input signal and the second input signal. When the first power voltage is within a predetermined voltage range, the signal delay setting circuit generates a voltage difference across the two signal input terminals and calculates a delay time according to the voltage difference. When the first power voltage is greater than an upper limit of the predetermined voltage range, the signal delay setting circuit delays the first input signal or the second input signal according to the delay time to control the duty ratio of the output signal.

The invention belongs to the technical field of laser precision machining and control, and particularly relates to a femtosecond laser single-point trigger control system and method based on subnanosecond synchronization, and the method comprises the following steps: S1, building a system synchronization clock locked with a femtosecond laser pulse signal phase; the specific mode of establishing the system synchronous clock is that phase locking is carried out on pulse synchronous signals or frequency division signals output by an internal high-frequency clock source and a femtosecond laser source through a digital phase-locked loop technology, and the low-jitter system synchronous clock which is strictly synchronous with a laser pulse sequence is generated. According to the invention, a system clock locked with a laser pulse phase can be generated through a digital phase-locked loop, and the influence of inherent frequency drift of a laser and circuit delay temperature drift is effectively overcome by combining real-time delay calculation based on a prediction algorithm and a high-resolution DDS delay line technology; the synchronization precision between the triggering moment of the single pulse and the external instruction is stabilized at the subnanosecond level, and the requirement of leading-edge application for the extreme time sequence precision is met.

The embodiment of the invention discloses a clock signal adjusting circuit. The clock signal adjusting circuit comprises a delay phase-locked loop circuit, a duty ratio correction circuit and a quadrant error correction circuit. And the delay phase-locked loop circuit is configured to receive the initial input clock signal and perform delay adjustment based on the initial input clock signal to obtain a plurality of phase-locked output clock signals. And the duty ratio correction circuit is connected with the delay phase-locked loop circuit and is configured to adjust the duty ratio of each output clock signal. And the quadrant error correction circuit is connected with the duty ratio correction circuit and is configured to adjust the phase difference between different output clock signals. Wherein the delay phase-locked loop circuit, the duty ratio correction circuit and the quadrant error correction circuit respond to a delay phase-locked loop reset command and start to operate at the same time.

Described is a system for modulating power to one or more radio frequency (RF) amplifiers to suppress undesired output signal components, improve linearity and reduce noise. The described systems and techniques enable shaping of spectral components introduced via an amplifier bias voltage owing to transitions among bias discrete states. The systems and techniques facilitate operation of multilevel, RF amplifiers under a wider range of operating conditions. In embodiments, the system includes modulators coupled to a supply terminal port of each of the one or more amplifiers to modulate the voltage levels supplied to the one or more amplifiers. The outputs of the modulators may be combined to provide a combined signal coupled to the amplifiers. A delay circuit delays switching of at least one of the power modulators relative to other modulator, by a variable time delay. This results in suppression of undesired output signal components of the amplifier output.

The invention provides an instruction sampling circuit and a memory. The instruction sampling circuit comprises a sampling circuit and a delay circuit. The sampling circuit receives a memory instruction and a sampling clock, respectively responds to a first sampling edge and a second sampling edge of the sampling clock, samples the memory instruction, and outputs a first cycle instruction and a second cycle instruction; the sampling circuit is provided with a first output end and a second output end; the time delay circuit delays the instruction output by the first output end of the sampling circuit and then outputs the instruction; the instruction decoding circuit receives the output clock, decodes the instruction output by the sampling circuit, responds to the output edge of the output clock, and outputs the current decoding result as decoding information of the memory instruction; and the address output circuit receives the output clock, responds to the output edge, and outputs the instruction currently output by the second output end of the sampling circuit as address information of the memory instruction. According to the scheme, the instruction sampling efficiency can be improved.

The invention discloses a physical layer interface circuit, a time delay compensation method and electronic equipment, the physical layer interface circuit is connected to storage equipment, and the physical layer interface circuit comprises a detection module used for detecting the access type of a received access request for the storage equipment; the signal transmission path comprises a time delay module, and the time delay module carries out time delay processing on a sampling clock signal for reading data from the storage device based on a time delay parameter; and the switching module is used for responding to the access type being a data writing type and controlling a parameter compensation path to be formed between the signal transmission path and the detection module, the parameter compensation path is used for obtaining a target compensation parameter, and the target compensation parameter is used for compensating the time delay parameter.

The invention relates to a lighting device (41) for an optoelectronic sensor having at least one lighting path (45a, 45b), wherein the lighting path (45a, 45b) comprises at least one light-emitting unit (46a, 46b) for emitting transmitted light and a detector (50a, 50b) for detecting the transmitted light or a current driving the light-emitting unit, and wherein the lighting device (41) comprises at least one driver (49a, 49b) with a driver output, which is connected to the light-emitting unit (46a, 46b) for control by means of a current signal, and a modulator (55) connected to a driver input for modulating the current signal, and with a delay detection circuit (53) and at least one delay compensation circuit (47a, 47b), and wherein - The detector (50a, 50b) is connected to the delay detection circuit (53) for providing a detector signal, - The delay detection circuit (53) is designed and arranged to measure a time delay of the detector signal relative to the modulation signal (Mod), - The delay compensation circuit (47a, 47b) is designed and configured to adjust a signal propagation time of the modulation signal (Mod) as a function of the detected time delay. Furthermore, a method for operating a corresponding lighting device (41) is specified.

The present application provides a delay circuit and electronic equipment, and relates to the field of circuit delay technology. The delay circuit includes an input module, a trigger module, an AND gate, and a delay module, the input module is used to receive an input signal, and the output end of the input module is respectively connected to the trigger module and the first input end of the AND gate, the output end of the trigger module is respectively electrically connected to the second input end of the AND gate and the delay module, and the delay module is respectively electrically connected to the input module and the third input end of the AND gate; wherein, when the input module receives a delay signal, the input module and the delay module are used to delay the delay signal, and output the delayed signal through the AND gate. The delay circuit and electronic equipment provided by the present application have the advantages of reducing a large amount of capacitor area and reducing the chip production cost.

To prevent power supply interruption during fail-safe control when a microcomputer of a power supply control device malfunctions.SOLUTION: The power supply control device includes a controller and a delay circuit. The controller outputs a first power hold signal to a power relay to control the power relay that supplies power to multiple control devices upon receiving either the first power hold signal or a second power hold signal. The delay circuit delays the first power hold signal for at least the time required for an external device to detect the controller malfunction when the power relay receives the second power hold signal from the external device as a fail-safe control during the controller malfunction.SELECTED DRAWING: Figure 1

Processing unit circuitry of one or more computer devices that includes transistors configured to a first voltage threshold, and digital voltage sensor circuitry (160) of the computer devices that inc

The utility model discloses a pulse width adaptive delay modulation circuit suitable for an erbium glass laser, which comprises an erbium glass laser, an input signal shaping circuit, an optical signal detection shaping circuit, a delay trigger circuit and a logic control output circuit, the input signal shaping circuit receives and shapes an external input signal and then outputs a driving signal to the logic control output circuit; the optical signal detection shaping circuit collects an optical signal, shapes the optical signal into a digital signal and transmits the digital signal to the delay trigger circuit, and the delay trigger circuit delays the received signal and transmits the signal to the logic control circuit; and the logic control circuit performs logic operation on the received two paths of signals and outputs a final driving signal to the erbium glass laser to form closed-loop control. According to the utility model, the light emitting condition of the erbium glass laser can be simply and effectively identified, a signal output by the input signal shaping circuit and a signal shaped during light emitting of the erbium glass laser are logically processed and then a driving signal is output, self-adaptive judgment control is realized, complex operation is not needed, the applicability of the driving circuit is improved, and the cost is reduced. And the driving application of the erbium glass laser is greatly simplified.

An electronic device and a method of operating the same are provided. The electronic device comprises a power-up circuit, a delay circuit and a plurality of power supply circuits. The power-up circuit is configured to control a power-up signal in accordance with a power supply voltage. The delay circuit is configured to provide a plurality of enable signals by delaying the power-up signal by different delay times. The plurality of power supply circuits are configured to be enabled by the plurality of enable signals, respectively.

A phase interpolator may include a decoding logic circuit. The decoding logic circuit may take as input an input control code and an update clock. The decoding logic circuit may generate one or more outputs which may be input to a retiming circuit. The retiming circuit may generate retimed outputs which may be input to a delay modulation circuit. The delay modulation circuit may generate a delayed clock select control signal and a delayed phase select control signal. The delayed clock select control signal and delayed phase select control signal may be input to a phase interpolator circuit and may generate an output clock based on two or more multi-phase input clocks. The delayed clock select control signal and delayed phase select control signal may eliminate overshoot and undershoot events in the output clock.

The invention provides a signal delay setting circuit, an isolated integrated circuit and a power conversion circuit system. The isolated integrated circuit receives a first power supply voltage, receives a first input signal and a second input signal through two signal input ends, and outputs an output signal generated according to the first input signal and the second input signal. When the first power supply voltage is within a preset voltage range, the signal delay setting circuit generates a voltage difference between the two signal input ends and calculates delay time according to the voltage difference. When the first power supply voltage is larger than the upper limit value of the preset voltage range, the signal delay setting circuit delays the first input signal or the second input signal according to the delay time so as to control the duty ratio of the output signal. The duty ratio of the output signal of the isolated integrated circuit is controlled through the signal delay setting circuit, the power conversion circuit system effectively generates dead time to protect the high-side switch and the low-side switch, and the power conversion circuit system has the advantages of being low in deviation, high in reliability, small in circuit area requirement and the like.

The invention provides a multilayer solving method for accelerating circuit simulation, electronic equipment and a storage medium, and the method comprises the steps: carrying out the recursion division of a circuit into sub-circuits of a plurality of hierarchies, and forming a hierarchical structure from fine to coarse; on the basis of circuit delay attributes, marking and simplifying inactive parts in each level of sub-circuit, and constructing a mapping relation between levels at the same time; based on the hierarchical structure and the mapping relation, assembling a to-be-solved linear equation set; a multi-layer class method is adopted to solve the linear equation set, and the multi-layer class method comprises the steps that smoothing is carried out on a fine layer before iteration, a residual error is transmitted to a coarse layer, a direct method is adopted to solve the coarsest layer, and then a solving result is extended back to the fine layer and smoothing is carried out after iteration; and repeating the solving step of the multi-layer class method until the linear equation set converges. The system of linear equations is established based on a multi-level circuit structure and is solved by using a multi-level method, so that the solving time and memory occupation of the system of linear equations in circuit simulation are greatly reduced.

A quantum circuit generator for a quantum computer includes: a controller; and a plurality of analog conversion units (ACUs) operably connected to the controller, each ACU being operably connected to a corresponding qubit in a plurality of qubits, wherein each ACU is configured to convert a digital input from the controller into an analog input at a microwave frequency to control the quantum state of the corresponding qubit. The controller is configured to generate a quantum circuit using at least two qubits in the plurality of qubits, the at least two qubits being selected by the controller based on corresponding classical bits mapped by the controller and based on a delay of the generated quantum circuit, such that the generated quantum circuit has a delay less than a delay threshold.

The invention belongs to the technical field of display, and particularly relates to a display control method, a time schedule controller and a display panel. Comprising the following steps: acquiring a current starting voltage value and a current common voltage value output by a power management circuit in a startup or shutdown process of the display panel; when the current starting voltage value is the valid voltage and the current common voltage value is the invalid voltage, obtaining a target time difference of the current common voltage value from the invalid voltage to the valid voltage; a clock driving signal is adjusted according to the target time difference, so that the gate driving circuit delays opening of pixel rows in the display panel according to the clock driving signal; or / and adjusting the data output time sequence according to the target time difference, so that the data driving circuit delays the output of the data signal according to the data output time sequence. According to the invention, the splash screen phenomenon of the display panel during startup and shutdown is effectively improved.

A phase-locked loop (PLL) circuit, an optoelectronic system, and an electronic device are disclosed. The PLL circuit includes: a signal processing circuit for converting the output signal of the laser into a difference frequency signal; a dual frequency and phase detector circuit configured to output a first error correction signal and a second error correction signal with opposite polarity to the first error correction signal based on the difference frequency signal output by the signal processing circuit; and a modulation circuit configured to perform calculations on the pre-correction signal and either the first or second error correction signal to obtain a modulation signal, the modulation signal being used to control the driving of the laser to modulate the laser output. By using two frequency and phase detectors to output the first and second error correction signals with only opposite polarities, the polarity reversal circuit in the prior art is eliminated, reducing the overall circuit delay and improving circuit performance.

The present application provides a circuit optimization method for satisfying multi-voltage operation. The method includes: obtaining a plurality of preset circuits that satisfy the principle of circuit function equivalence; obtaining the operating probability, circuit delay, and circuit power consumption of a first preset circuit under various preset voltage conditions, where the first preset circuit is any one of the plurality of preset circuits, and the various preset voltage conditions are a plurality of operating voltages that satisfy the normal operation of the first preset circuit; calculating the product of the circuit power consumption and delay of the first preset circuit according to the operating probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions; and determining a preferred circuit from the plurality of preset circuits according to the product of the circuit power consumption and delay of the first preset circuit. Thus, an optimization method is provided for a circuit with a large operating voltage variation range, improving the operating performance of a circuit that satisfies multi-voltage operation.

A power supply semiconductor integrated circuit includes a first abnormality detection circuit, a second abnormality detection circuit, a delay circuit that delays an output of the first abnormality detection circuit and an output of the second abnormality detection circuit, and a latch circuit that takes in and holds an output of the delay circuit. The delay circuit includes a constant current source that charges a delay capacitor, a switching unit that discharges the delay capacitor, and a voltage comparison circuit that compares a charged voltage of the delay capacitor with a predetermined voltage. The charging of the delay capacitor is started in accordance with a change in a state indicating an abnormality in the output of the first abnormality detection circuit or an abnormality in the output of the second abnormality detection circuit. When the voltage comparison circuit determines that the charged voltage of the delay capacitor reaches the predetermined voltage, an output is changed, and the delay capacitor is discharged by taking the output into the latch circuit.

A delay control circuit provided herein includes a DLL control circuit, a delay line circuit, and an N-value detection circuit. The DLL control circuit determines the delay amount based on the phase difference between the input and output clock signals. The delay line circuit delays the input clock signal based on the delay amount to generate an output clock signal. The N-value detection circuit performs an N-value detection operation for detecting the number of delayed clock cycles from the input clock signal to the output clock signal. When it is determined to be in an overflow state, the DLL control circuit outputs a signal indicating an overflow state to the N-value detection circuit. When the signal indicating the overflow state is received, the N-value detection circuit does not perform the N-value detection operation, but instead sets the number of delayed clock cycles to a predetermined value.

The invention discloses a communication circuit and a communication system. The communication circuit comprises a controller, a serial transceiver chip, a signal conversion circuit, a unidirectional conductive circuit, a delay circuit and a bias circuit. The signal conversion circuit outputs an inversion signal of the serial sending pin. And the delay circuit is used for delaying the signal and the inversion signal of the serial sending pin. The rising time of the signal for receiving the enable pin is earlier than the rising time of the signal for transmitting the enable pin, the rising time of the signal for transmitting the enable pin is earlier than the falling time of the signal for transmitting the data input pin, and the falling time of the signal for transmitting the enable pin is later than the rising time of the signal for transmitting the data input pin. The falling time of the signal receiving the enable pin is later than the falling time of the signal transmitting the enable pin. The biasing circuit pulls up the first differential signal pin and pulls down the second differential signal pin. Through the above mode, serial communication can be realized based on the two pins of the controller so as to save I / O resources.

The invention discloses a half-cycle time sequence repairing method and system of a circuit delay locked storage device. The method comprises the following steps: detecting whether installation time violation or holding time violation exists in the digital circuit design or not; when the time sequence violation exists and cannot be conventionally repaired, verifying whether the time sequence margin of the violation path meets a calling condition or not; if yes, part of clock cycle time is called through the barrier-free passing characteristic of the circuit delay lock storage device in the high-level stationary circuit period, and half-cycle cycle time calling repair based on the circuit delay lock storage device is carried out on a violation path, specifically, for installation time violation, an end device is replaced; for holding time violation, a reverse trigger device is inserted. Through the half-cycle period time calling and differentiation strategy, the technical bottleneck of a traditional method is broken through, and a final solution is provided for time sequence violation which cannot be repaired by a conventional method in an extreme design environment.

The application provides a signal delay setting circuit, an isolation integrated circuit and a power conversion circuitry. The isolation integrated circuit receives a first power voltage, receives a first input signal and a second input signal via two signal input terminals respectively, and outputs an output signal generated according to the first input signal and the second input signal. When the first power voltage is within a predetermined voltage range, the signal delay setting circuit generates a voltage difference across the two signal input terminals and calculates a delay time according to the voltage difference. When the first power voltage is greater than an upper limit of the predetermined voltage range, the signal delay setting circuit delays the first input signal or the second input signal according to the delay time to control the duty ratio of the output signal.

The air conditioner comprises an alternating current input port, a rectifying circuit, a PFC circuit, a load and a sampling circuit used for collecting the current of the PFC circuit, the PFC circuit comprises a switching device, the controlled end of the switching device receives a PWM signal from a controller, the sampling circuit comprises a filtering device, and the controller is configured to receive the PWM signal through the filtering device. When the duty ratio of the PWM signal is larger than a first preset threshold value and smaller than a second preset threshold value, it is judged that the difference between the sampling current and the working current in the reference time exceeds a set threshold value, the deviation time is set as a first parameter, and the starting time of the first level of the PWM signal is defined as a starting point; the sampling circuit samples the current of the switching device based on the starting point passing through the reference time and the deviation time for controlling the PFC circuit. By judging the size of the duty ratio and the circuit delay condition, the current sampling moment is dynamically adjusted, the difference between a sampling value and an actual value is reduced, and the sampling accuracy is improved.

To provide a method and an apparatus for clock recovery of communication via a multi-wire, multi-phase interface.SOLUTION: The method includes generating a combinational signal that includes transition pulses. Each transition pulse is generated in response to a transition in a differential signal that represents a difference in the signaling state of a pair of wires in a three-wire bus. The method also provides a logic circuit with the combinational signal. The logic circuit provides a clock signal as its output. Here, a pulse in the combinational signal causes the clock signal to be driven to a first state. The method further receives a reset signal derived from the clock signal by the logic circuit delaying the transition to the first state and passing the transition from the first state without any additional delay. The clock signal is driven from the first state after passing the transition of the clock signal to the first state.SELECTED DRAWING: Figure 20

The utility model provides a three-phase circuit for contact arc extinction. The three-phase circuit comprises a contact delay circuit and three trigger circuits, the contact delay circuit comprises a coil MJ; the three trigger circuits are respectively and correspondingly arranged on an A-phase circuit, a B-phase circuit and a C-phase circuit of the power distribution system; each trigger circuit is connected with the three-phase circuit corresponding to each trigger circuit through two terminals; a contact switch KM1 is arranged between the two terminals; the contact switches KM1 of the A-phase circuit, the B-phase circuit and the C-phase circuit correspond to the coil MJ in position; when the three-phase circuit carries out power supply, the three trigger circuits are conducted before the contact delay circuit, and after the contact delay circuit is conducted, the coil MJ can close the contact switch KM1 of the A-phase circuit, the B-phase circuit and the C-phase circuit. According to the embodiment of the invention, the contact switch KM1 of the A-phase circuit, the B-phase circuit and the C-phase circuit can be delayed to be closed through the contact delay circuit, and the conversion from soft switching to hard switching of the three-phase circuit is realized through the three trigger circuits, so that the arc discharge phenomenon is eliminated.