102 results about "Circuit delay" patented technology

A clock generation circuit includes a delay-locked circuit and a duty correction circuit. The delay-locked circuit generates a delay clock signal by delaying an input clock signal and update the delay time of the input clock signal. The duty correction circuit generates a first phase clock signal and a second phase clock signal by delaying the delay clock signal, and updates the delay time of the delay clock signal. The duty correction circuit can prevent or mitigate the delay time of the input clock signal and the delay time of the delay clock signal from being updated simultaneously.

A switching modulation circuit generates a first control signal with a duty ratio. A delay circuit delays the first control signal to generate a second control signal. A zero crossing detector detects whether an output current of a DC / DC converter is smaller than a threshold in a rectification interval, and generates a third control signal. A monitoring circuit detects a reverse-flow possibility of the output current, and generates a fourth control signal. A delay time of the delay circuit is set shorter than the delay time of the zero crossing detector. When the reverse-flow possibility does not exist, and the third control signal has transitioned to indicate that the output current is smaller than the threshold, a driver circuit turns off both first and second switching elements. When the reverse-flow possibility exists, and the second control signal has transitioned from an ON state to an OFF state, the driver circuit turns off both the first and second switching elements.

The invention belongs to the technical field of laser precision machining and control, and particularly relates to a femtosecond laser single-point trigger control system and method based on subnanosecond synchronization, and the method comprises the following steps: S1, building a system synchronization clock locked with a femtosecond laser pulse signal phase; the specific mode of establishing the system synchronous clock is that phase locking is carried out on pulse synchronous signals or frequency division signals output by an internal high-frequency clock source and a femtosecond laser source through a digital phase-locked loop technology, and the low-jitter system synchronous clock which is strictly synchronous with a laser pulse sequence is generated. According to the invention, a system clock locked with a laser pulse phase can be generated through a digital phase-locked loop, and the influence of inherent frequency drift of a laser and circuit delay temperature drift is effectively overcome by combining real-time delay calculation based on a prediction algorithm and a high-resolution DDS delay line technology; the synchronization precision between the triggering moment of the single pulse and the external instruction is stabilized at the subnanosecond level, and the requirement of leading-edge application for the extreme time sequence precision is met.

The embodiment of the invention discloses a clock signal adjusting circuit. The clock signal adjusting circuit comprises a delay phase-locked loop circuit, a duty ratio correction circuit and a quadrant error correction circuit. And the delay phase-locked loop circuit is configured to receive the initial input clock signal and perform delay adjustment based on the initial input clock signal to obtain a plurality of phase-locked output clock signals. And the duty ratio correction circuit is connected with the delay phase-locked loop circuit and is configured to adjust the duty ratio of each output clock signal. And the quadrant error correction circuit is connected with the duty ratio correction circuit and is configured to adjust the phase difference between different output clock signals. Wherein the delay phase-locked loop circuit, the duty ratio correction circuit and the quadrant error correction circuit respond to a delay phase-locked loop reset command and start to operate at the same time.

Described is a system for modulating power to one or more radio frequency (RF) amplifiers to suppress undesired output signal components, improve linearity and reduce noise. The described systems and techniques enable shaping of spectral components introduced via an amplifier bias voltage owing to transitions among bias discrete states. The systems and techniques facilitate operation of multilevel, RF amplifiers under a wider range of operating conditions. In embodiments, the system includes modulators coupled to a supply terminal port of each of the one or more amplifiers to modulate the voltage levels supplied to the one or more amplifiers. The outputs of the modulators may be combined to provide a combined signal coupled to the amplifiers. A delay circuit delays switching of at least one of the power modulators relative to other modulator, by a variable time delay. This results in suppression of undesired output signal components of the amplifier output.

The invention provides an instruction sampling circuit and a memory. The instruction sampling circuit comprises a sampling circuit and a delay circuit. The sampling circuit receives a memory instruction and a sampling clock, respectively responds to a first sampling edge and a second sampling edge of the sampling clock, samples the memory instruction, and outputs a first cycle instruction and a second cycle instruction; the sampling circuit is provided with a first output end and a second output end; the time delay circuit delays the instruction output by the first output end of the sampling circuit and then outputs the instruction; the instruction decoding circuit receives the output clock, decodes the instruction output by the sampling circuit, responds to the output edge of the output clock, and outputs the current decoding result as decoding information of the memory instruction; and the address output circuit receives the output clock, responds to the output edge, and outputs the instruction currently output by the second output end of the sampling circuit as address information of the memory instruction. According to the scheme, the instruction sampling efficiency can be improved.

The invention discloses a physical layer interface circuit, a time delay compensation method and electronic equipment, the physical layer interface circuit is connected to storage equipment, and the physical layer interface circuit comprises a detection module used for detecting the access type of a received access request for the storage equipment; the signal transmission path comprises a time delay module, and the time delay module carries out time delay processing on a sampling clock signal for reading data from the storage device based on a time delay parameter; and the switching module is used for responding to the access type being a data writing type and controlling a parameter compensation path to be formed between the signal transmission path and the detection module, the parameter compensation path is used for obtaining a target compensation parameter, and the target compensation parameter is used for compensating the time delay parameter.

To prevent power supply interruption during fail-safe control when a microcomputer of a power supply control device malfunctions.SOLUTION: The power supply control device includes a controller and a delay circuit. The controller outputs a first power hold signal to a power relay to control the power relay that supplies power to multiple control devices upon receiving either the first power hold signal or a second power hold signal. The delay circuit delays the first power hold signal for at least the time required for an external device to detect the controller malfunction when the power relay receives the second power hold signal from the external device as a fail-safe control during the controller malfunction.SELECTED DRAWING: Figure 1

Processing unit circuitry of one or more computer devices that includes transistors configured to a first voltage threshold, and digital voltage sensor circuitry (160) of the computer devices that inc

The utility model discloses a pulse width adaptive delay modulation circuit suitable for an erbium glass laser, which comprises an erbium glass laser, an input signal shaping circuit, an optical signal detection shaping circuit, a delay trigger circuit and a logic control output circuit, the input signal shaping circuit receives and shapes an external input signal and then outputs a driving signal to the logic control output circuit; the optical signal detection shaping circuit collects an optical signal, shapes the optical signal into a digital signal and transmits the digital signal to the delay trigger circuit, and the delay trigger circuit delays the received signal and transmits the signal to the logic control circuit; and the logic control circuit performs logic operation on the received two paths of signals and outputs a final driving signal to the erbium glass laser to form closed-loop control. According to the utility model, the light emitting condition of the erbium glass laser can be simply and effectively identified, a signal output by the input signal shaping circuit and a signal shaped during light emitting of the erbium glass laser are logically processed and then a driving signal is output, self-adaptive judgment control is realized, complex operation is not needed, the applicability of the driving circuit is improved, and the cost is reduced. And the driving application of the erbium glass laser is greatly simplified.

A phase interpolator may include a decoding logic circuit. The decoding logic circuit may take as input an input control code and an update clock. The decoding logic circuit may generate one or more outputs which may be input to a retiming circuit. The retiming circuit may generate retimed outputs which may be input to a delay modulation circuit. The delay modulation circuit may generate a delayed clock select control signal and a delayed phase select control signal. The delayed clock select control signal and delayed phase select control signal may be input to a phase interpolator circuit and may generate an output clock based on two or more multi-phase input clocks. The delayed clock select control signal and delayed phase select control signal may eliminate overshoot and undershoot events in the output clock.

The invention provides a multilayer solving method for accelerating circuit simulation, electronic equipment and a storage medium, and the method comprises the steps: carrying out the recursion division of a circuit into sub-circuits of a plurality of hierarchies, and forming a hierarchical structure from fine to coarse; on the basis of circuit delay attributes, marking and simplifying inactive parts in each level of sub-circuit, and constructing a mapping relation between levels at the same time; based on the hierarchical structure and the mapping relation, assembling a to-be-solved linear equation set; a multi-layer class method is adopted to solve the linear equation set, and the multi-layer class method comprises the steps that smoothing is carried out on a fine layer before iteration, a residual error is transmitted to a coarse layer, a direct method is adopted to solve the coarsest layer, and then a solving result is extended back to the fine layer and smoothing is carried out after iteration; and repeating the solving step of the multi-layer class method until the linear equation set converges. The system of linear equations is established based on a multi-level circuit structure and is solved by using a multi-level method, so that the solving time and memory occupation of the system of linear equations in circuit simulation are greatly reduced.

The invention belongs to the technical field of display, and particularly relates to a display control method, a time schedule controller and a display panel. Comprising the following steps: acquiring a current starting voltage value and a current common voltage value output by a power management circuit in a startup or shutdown process of the display panel; when the current starting voltage value is the valid voltage and the current common voltage value is the invalid voltage, obtaining a target time difference of the current common voltage value from the invalid voltage to the valid voltage; a clock driving signal is adjusted according to the target time difference, so that the gate driving circuit delays opening of pixel rows in the display panel according to the clock driving signal; or / and adjusting the data output time sequence according to the target time difference, so that the data driving circuit delays the output of the data signal according to the data output time sequence. According to the invention, the splash screen phenomenon of the display panel during startup and shutdown is effectively improved.

A phase-locked loop (PLL) circuit, an optoelectronic system, and an electronic device are disclosed. The PLL circuit includes: a signal processing circuit for converting the output signal of the laser into a difference frequency signal; a dual frequency and phase detector circuit configured to output a first error correction signal and a second error correction signal with opposite polarity to the first error correction signal based on the difference frequency signal output by the signal processing circuit; and a modulation circuit configured to perform calculations on the pre-correction signal and either the first or second error correction signal to obtain a modulation signal, the modulation signal being used to control the driving of the laser to modulate the laser output. By using two frequency and phase detectors to output the first and second error correction signals with only opposite polarities, the polarity reversal circuit in the prior art is eliminated, reducing the overall circuit delay and improving circuit performance.

The present application provides a circuit optimization method for satisfying multi-voltage operation. The method includes: obtaining a plurality of preset circuits that satisfy the principle of circuit function equivalence; obtaining the operating probability, circuit delay, and circuit power consumption of a first preset circuit under various preset voltage conditions, where the first preset circuit is any one of the plurality of preset circuits, and the various preset voltage conditions are a plurality of operating voltages that satisfy the normal operation of the first preset circuit; calculating the product of the circuit power consumption and delay of the first preset circuit according to the operating probability, circuit delay, and circuit power consumption of the first preset circuit under various preset voltage conditions; and determining a preferred circuit from the plurality of preset circuits according to the product of the circuit power consumption and delay of the first preset circuit. Thus, an optimization method is provided for a circuit with a large operating voltage variation range, improving the operating performance of a circuit that satisfies multi-voltage operation.

A power supply semiconductor integrated circuit includes a first abnormality detection circuit, a second abnormality detection circuit, a delay circuit that delays an output of the first abnormality detection circuit and an output of the second abnormality detection circuit, and a latch circuit that takes in and holds an output of the delay circuit. The delay circuit includes a constant current source that charges a delay capacitor, a switching unit that discharges the delay capacitor, and a voltage comparison circuit that compares a charged voltage of the delay capacitor with a predetermined voltage. The charging of the delay capacitor is started in accordance with a change in a state indicating an abnormality in the output of the first abnormality detection circuit or an abnormality in the output of the second abnormality detection circuit. When the voltage comparison circuit determines that the charged voltage of the delay capacitor reaches the predetermined voltage, an output is changed, and the delay capacitor is discharged by taking the output into the latch circuit.

A delay control circuit provided herein includes a DLL control circuit, a delay line circuit, and an N-value detection circuit. The DLL control circuit determines the delay amount based on the phase difference between the input and output clock signals. The delay line circuit delays the input clock signal based on the delay amount to generate an output clock signal. The N-value detection circuit performs an N-value detection operation for detecting the number of delayed clock cycles from the input clock signal to the output clock signal. When it is determined to be in an overflow state, the DLL control circuit outputs a signal indicating an overflow state to the N-value detection circuit. When the signal indicating the overflow state is received, the N-value detection circuit does not perform the N-value detection operation, but instead sets the number of delayed clock cycles to a predetermined value.

The invention discloses a communication circuit and a communication system. The communication circuit comprises a controller, a serial transceiver chip, a signal conversion circuit, a unidirectional conductive circuit, a delay circuit and a bias circuit. The signal conversion circuit outputs an inversion signal of the serial sending pin. And the delay circuit is used for delaying the signal and the inversion signal of the serial sending pin. The rising time of the signal for receiving the enable pin is earlier than the rising time of the signal for transmitting the enable pin, the rising time of the signal for transmitting the enable pin is earlier than the falling time of the signal for transmitting the data input pin, and the falling time of the signal for transmitting the enable pin is later than the rising time of the signal for transmitting the data input pin. The falling time of the signal receiving the enable pin is later than the falling time of the signal transmitting the enable pin. The biasing circuit pulls up the first differential signal pin and pulls down the second differential signal pin. Through the above mode, serial communication can be realized based on the two pins of the controller so as to save I / O resources.

The invention discloses a half-cycle time sequence repairing method and system of a circuit delay locked storage device. The method comprises the following steps: detecting whether installation time violation or holding time violation exists in the digital circuit design or not; when the time sequence violation exists and cannot be conventionally repaired, verifying whether the time sequence margin of the violation path meets a calling condition or not; if yes, part of clock cycle time is called through the barrier-free passing characteristic of the circuit delay lock storage device in the high-level stationary circuit period, and half-cycle cycle time calling repair based on the circuit delay lock storage device is carried out on a violation path, specifically, for installation time violation, an end device is replaced; for holding time violation, a reverse trigger device is inserted. Through the half-cycle period time calling and differentiation strategy, the technical bottleneck of a traditional method is broken through, and a final solution is provided for time sequence violation which cannot be repaired by a conventional method in an extreme design environment.

The application provides a signal delay setting circuit, an isolation integrated circuit and a power conversion circuitry. The isolation integrated circuit receives a first power voltage, receives a first input signal and a second input signal via two signal input terminals respectively, and outputs an output signal generated according to the first input signal and the second input signal. When the first power voltage is within a predetermined voltage range, the signal delay setting circuit generates a voltage difference across the two signal input terminals and calculates a delay time according to the voltage difference. When the first power voltage is greater than an upper limit of the predetermined voltage range, the signal delay setting circuit delays the first input signal or the second input signal according to the delay time to control the duty ratio of the output signal.

The air conditioner comprises an alternating current input port, a rectifying circuit, a PFC circuit, a load and a sampling circuit used for collecting the current of the PFC circuit, the PFC circuit comprises a switching device, the controlled end of the switching device receives a PWM signal from a controller, the sampling circuit comprises a filtering device, and the controller is configured to receive the PWM signal through the filtering device. When the duty ratio of the PWM signal is larger than a first preset threshold value and smaller than a second preset threshold value, it is judged that the difference between the sampling current and the working current in the reference time exceeds a set threshold value, the deviation time is set as a first parameter, and the starting time of the first level of the PWM signal is defined as a starting point; the sampling circuit samples the current of the switching device based on the starting point passing through the reference time and the deviation time for controlling the PFC circuit. By judging the size of the duty ratio and the circuit delay condition, the current sampling moment is dynamically adjusted, the difference between a sampling value and an actual value is reduced, and the sampling accuracy is improved.

The utility model provides a three-phase circuit for contact arc extinction. The three-phase circuit comprises a contact delay circuit and three trigger circuits, the contact delay circuit comprises a coil MJ; the three trigger circuits are respectively and correspondingly arranged on an A-phase circuit, a B-phase circuit and a C-phase circuit of the power distribution system; each trigger circuit is connected with the three-phase circuit corresponding to each trigger circuit through two terminals; a contact switch KM1 is arranged between the two terminals; the contact switches KM1 of the A-phase circuit, the B-phase circuit and the C-phase circuit correspond to the coil MJ in position; when the three-phase circuit carries out power supply, the three trigger circuits are conducted before the contact delay circuit, and after the contact delay circuit is conducted, the coil MJ can close the contact switch KM1 of the A-phase circuit, the B-phase circuit and the C-phase circuit. According to the embodiment of the invention, the contact switch KM1 of the A-phase circuit, the B-phase circuit and the C-phase circuit can be delayed to be closed through the contact delay circuit, and the conversion from soft switching to hard switching of the three-phase circuit is realized through the three trigger circuits, so that the arc discharge phenomenon is eliminated.

The invention discloses a clock generation circuit for a time-interleaved ADC, and belongs to the technical field of integrated circuits. Comprising a delay circuit Delay, a frequency division module and a pulse width adjusting circuit CLKsample, the pulse width adjusting circuit CLKsample is used for generating a sampling clock signal CLKS with adjustable pulse width and inputting the sampling clock signal CLKS into the second AND gate group; the frequency division module performs frequency division on an external clock signal CLK into multiple paths, inputs the multiple paths of signals into the first AND gate group to obtain multiple intermediate clock signals, and inputs the multiple intermediate clock signals into the second AND gate group; the second AND gate group performs AND operation on the sampling clock signal CLKS and each intermediate clock signal to obtain a plurality of multi-phase clock sampling signals, and inputs the multi-phase clock sampling signals into each sub-ADC module for time-interleaved sampling and analog-to-digital conversion; and combining and synchronizing to obtain a final signal. The circuit is simple in structure, smaller in area and lower in power consumption, extremely small phase deviation exists between interleaved sampling clock signals, and meanwhile the pulse width of the sampling clock signals can be freely adjusted.

The present disclosure provides a command sampling circuit and a memory. The command sampling circuit includes a sampling circuit and a delay circuit. The sampling circuit samples a memory command separately in response to a first sampling edge and a second sampling edge of a sampling clock, and outputs a first cycle command and a second cycle command; the delay circuit delays a command output at a first output end of the sampling circuit and then outputs a delayed command; a command decoding circuit receives an output clock, decodes the commands output by the sampling circuit, and outputs a current decoded result as decoding information of the memory command; an address output circuit receives the output clock and outputs, in response to the output edge, a command currently output at a second output end of the sampling circuit as address information of the memory command.

The invention provides a multi-gear knob which comprises a control panel and a wiring panel, a rotating shaft is arranged on the control panel, a plurality of gears are arranged around the rotating shaft, a plurality of binding posts are arranged on the wiring panel, the multi-gear knob is externally connected to a control system through the binding posts, and the multi-gear knob further comprises a time delay circuit. A power supply end and a relay switch are arranged; the trigger device is provided with a first normally open contact and a second normally open contact corresponding to each gear, the first normally open contact is connected between the power supply end of the time delay circuit and the power supply, and the power supply is controlled to supply power to the time delay circuit through the conduction state of the first normally open contact; the second type of normally open contacts are connected between the plurality of binding posts and the relay switch; when the rotating shaft is located at the positions corresponding to different gears, the first type of normally open contacts are short-circuited, and the second type of normally open contacts corresponding to the gears are short-circuited after the time delay circuit delays the set time, so that circuit paths corresponding to the gears are formed.

The invention discloses a high-speed Miller platform detection circuit for a GaN half-bridge gate driving chip, and relates to the technical field of power device driving. The circuit comprises a detection node, an RC series circuit, a positive pulse discharge path, a negative pulse voltage stabilization path and a signal isolation circuit. The RC series circuit couples the voltage jump delay of the floating ground to the detection node so as to generate a voltage pulse representing the starting point of the Miller platform; the positive pulse discharge module and the negative pulse clamping module are respectively connected in parallel between the detection node and the floating ground, and are used for rapidly discharging positive interference pulses and clamping negative pulses at safe voltage; and the signal isolation module is used for isolating a post-stage circuit load. The circuit is simple in structure, high in response speed and easy to integrate, the problems that a traditional detection scheme is large in delay and complex in circuit are solved, and key support is provided for a high-frequency GaN driving chip to achieve accurate active driving.

The invention discloses a signal output device with an adjustable conversion rate. The signal output device comprises a plurality of output units. The output units are connected in parallel between the input end and the output end, respectively correspond to the adjustable signal delay amount, and each output unit comprises a delay path and an output circuit. The delay path is configured to provide an adjustable signal delay amount to receive an input signal from an input end and delay the input signal, thereby generating a delayed signal. The output circuit receives the delay signal and generates an output signal to the output end. Wherein the output end outputs a total output signal according to the output signals generated by the output circuits of all the output units, and the conversion rate of the total output signal is determined by the combination of the adjustable signal delays of the output units.

The invention discloses a method for testing the DC internal resistance of a supercapacitor, and belongs to the technical field of supercapacitors. According to the scheme, the voltage value of the super capacitor is continuously collected and recorded before the super capacitor stops discharging, the sampling frequency and the preset sampling point number are determined through repeated experiments, the whole process from collection to discharging stop to discharging rebound is ensured, collection is stopped after the preset sampling point number is collected, and the sampling efficiency is improved. And obtaining a discharge cut-off voltage and a discharge rebound voltage according to the collected data, and calculating the DC internal resistance of the supercapacitor. According to the invention, single-point acquisition is replaced by continuous acquisition, errors caused by capacitor charge adjustment after circuit delay and discharge stop are avoided, and the DC internal resistance test precision of the supercapacitor is improved.

The present application discloses a duty cycle adjustment circuit, a delay locked loop circuit and a memory, wherein a duty cycle adjustment link in the duty cycle adjustment circuit receives an input clock signal and adjusts the duty cycle of the input clock signal to generate an output clock signal; a duty cycle detection circuit is coupled to the duty cycle adjustment link and generates a corresponding first detection signal based on the detected duty cycle of the output clock signal; an initial state confirmation circuit is coupled to the duty cycle adjustment link and is used to detect the duty cycle of the output clock signal in the initial state of the duty cycle adjustment link and generate a corresponding second detection signal based on the duty cycle of the output clock signal; an adjustment circuit is coupled to the duty cycle detection circuit and the initial state confirmation circuit and is used to generate a corresponding control signal based on the first detection signal and the second detection signal, and generate a control code based on the control signal, so that the duty cycle adjustment link adjusts the duty cycle of the input clock signal to generate an output clock signal.

The invention provides an RGMII delay automatic compensation system and method, and the system comprises an Ethernet MAC circuit which is used for receiving and transmitting data through an RGMII interface; the sampling circuit is connected with the RGMII interface and is used for sampling a plurality of signal lines of the RGMII to obtain phase information among signals; and the delay compensation circuit is respectively connected with the high-precision sampling circuit and the Ethernet MAC circuit, and is used for calculating the delay time of each signal line according to the phase information and controlling the Ethernet MAC circuit to carry out delay compensation. According to the RGMII delay automatic compensation system provided by the invention, the problem of inconsistent signal delay caused by PCB wiring length difference is solved, and the signal integrity and the system stability of RGMII interface communication are effectively improved.