41 results about "Circuit delay" patented technology

The invention belongs to the technical field of laser precision machining and control, and particularly relates to a femtosecond laser single-point trigger control system and method based on subnanosecond synchronization, and the method comprises the following steps: S1, building a system synchronization clock locked with a femtosecond laser pulse signal phase; the specific mode of establishing the system synchronous clock is that phase locking is carried out on pulse synchronous signals or frequency division signals output by an internal high-frequency clock source and a femtosecond laser source through a digital phase-locked loop technology, and the low-jitter system synchronous clock which is strictly synchronous with a laser pulse sequence is generated. According to the invention, a system clock locked with a laser pulse phase can be generated through a digital phase-locked loop, and the influence of inherent frequency drift of a laser and circuit delay temperature drift is effectively overcome by combining real-time delay calculation based on a prediction algorithm and a high-resolution DDS delay line technology; the synchronization precision between the triggering moment of the single pulse and the external instruction is stabilized at the subnanosecond level, and the requirement of leading-edge application for the extreme time sequence precision is met.

The invention provides a multilayer solving method for accelerating circuit simulation, electronic equipment and a storage medium, and the method comprises the steps: carrying out the recursion division of a circuit into sub-circuits of a plurality of hierarchies, and forming a hierarchical structure from fine to coarse; on the basis of circuit delay attributes, marking and simplifying inactive parts in each level of sub-circuit, and constructing a mapping relation between levels at the same time; based on the hierarchical structure and the mapping relation, assembling a to-be-solved linear equation set; a multi-layer class method is adopted to solve the linear equation set, and the multi-layer class method comprises the steps that smoothing is carried out on a fine layer before iteration, a residual error is transmitted to a coarse layer, a direct method is adopted to solve the coarsest layer, and then a solving result is extended back to the fine layer and smoothing is carried out after iteration; and repeating the solving step of the multi-layer class method until the linear equation set converges. The system of linear equations is established based on a multi-level circuit structure and is solved by using a multi-level method, so that the solving time and memory occupation of the system of linear equations in circuit simulation are greatly reduced.

The invention belongs to the technical field of display, and particularly relates to a display control method, a time schedule controller and a display panel. Comprising the following steps: acquiring a current starting voltage value and a current common voltage value output by a power management circuit in a startup or shutdown process of the display panel; when the current starting voltage value is the valid voltage and the current common voltage value is the invalid voltage, obtaining a target time difference of the current common voltage value from the invalid voltage to the valid voltage; a clock driving signal is adjusted according to the target time difference, so that the gate driving circuit delays opening of pixel rows in the display panel according to the clock driving signal; or / and adjusting the data output time sequence according to the target time difference, so that the data driving circuit delays the output of the data signal according to the data output time sequence. According to the invention, the splash screen phenomenon of the display panel during startup and shutdown is effectively improved.

A power supply semiconductor integrated circuit includes a first abnormality detection circuit, a second abnormality detection circuit, a delay circuit that delays an output of the first abnormality detection circuit and an output of the second abnormality detection circuit, and a latch circuit that takes in and holds an output of the delay circuit. The delay circuit includes a constant current source that charges a delay capacitor, a switching unit that discharges the delay capacitor, and a voltage comparison circuit that compares a charged voltage of the delay capacitor with a predetermined voltage. The charging of the delay capacitor is started in accordance with a change in a state indicating an abnormality in the output of the first abnormality detection circuit or an abnormality in the output of the second abnormality detection circuit. When the voltage comparison circuit determines that the charged voltage of the delay capacitor reaches the predetermined voltage, an output is changed, and the delay capacitor is discharged by taking the output into the latch circuit.

The invention discloses a communication circuit and a communication system. The communication circuit comprises a controller, a serial transceiver chip, a signal conversion circuit, a unidirectional conductive circuit, a delay circuit and a bias circuit. The signal conversion circuit outputs an inversion signal of the serial sending pin. And the delay circuit is used for delaying the signal and the inversion signal of the serial sending pin. The rising time of the signal for receiving the enable pin is earlier than the rising time of the signal for transmitting the enable pin, the rising time of the signal for transmitting the enable pin is earlier than the falling time of the signal for transmitting the data input pin, and the falling time of the signal for transmitting the enable pin is later than the rising time of the signal for transmitting the data input pin. The falling time of the signal receiving the enable pin is later than the falling time of the signal transmitting the enable pin. The biasing circuit pulls up the first differential signal pin and pulls down the second differential signal pin. Through the above mode, serial communication can be realized based on the two pins of the controller so as to save I / O resources.

The invention discloses a half-cycle time sequence repairing method and system of a circuit delay locked storage device. The method comprises the following steps: detecting whether installation time violation or holding time violation exists in the digital circuit design or not; when the time sequence violation exists and cannot be conventionally repaired, verifying whether the time sequence margin of the violation path meets a calling condition or not; if yes, part of clock cycle time is called through the barrier-free passing characteristic of the circuit delay lock storage device in the high-level stationary circuit period, and half-cycle cycle time calling repair based on the circuit delay lock storage device is carried out on a violation path, specifically, for installation time violation, an end device is replaced; for holding time violation, a reverse trigger device is inserted. Through the half-cycle period time calling and differentiation strategy, the technical bottleneck of a traditional method is broken through, and a final solution is provided for time sequence violation which cannot be repaired by a conventional method in an extreme design environment.

The application provides a signal delay setting circuit, an isolation integrated circuit and a power conversion circuitry. The isolation integrated circuit receives a first power voltage, receives a first input signal and a second input signal via two signal input terminals respectively, and outputs an output signal generated according to the first input signal and the second input signal. When the first power voltage is within a predetermined voltage range, the signal delay setting circuit generates a voltage difference across the two signal input terminals and calculates a delay time according to the voltage difference. When the first power voltage is greater than an upper limit of the predetermined voltage range, the signal delay setting circuit delays the first input signal or the second input signal according to the delay time to control the duty ratio of the output signal.

The air conditioner comprises an alternating current input port, a rectifying circuit, a PFC circuit, a load and a sampling circuit used for collecting the current of the PFC circuit, the PFC circuit comprises a switching device, the controlled end of the switching device receives a PWM signal from a controller, the sampling circuit comprises a filtering device, and the controller is configured to receive the PWM signal through the filtering device. When the duty ratio of the PWM signal is larger than a first preset threshold value and smaller than a second preset threshold value, it is judged that the difference between the sampling current and the working current in the reference time exceeds a set threshold value, the deviation time is set as a first parameter, and the starting time of the first level of the PWM signal is defined as a starting point; the sampling circuit samples the current of the switching device based on the starting point passing through the reference time and the deviation time for controlling the PFC circuit. By judging the size of the duty ratio and the circuit delay condition, the current sampling moment is dynamically adjusted, the difference between a sampling value and an actual value is reduced, and the sampling accuracy is improved.

The utility model provides a three-phase circuit for contact arc extinction. The three-phase circuit comprises a contact delay circuit and three trigger circuits, the contact delay circuit comprises a coil MJ; the three trigger circuits are respectively and correspondingly arranged on an A-phase circuit, a B-phase circuit and a C-phase circuit of the power distribution system; each trigger circuit is connected with the three-phase circuit corresponding to each trigger circuit through two terminals; a contact switch KM1 is arranged between the two terminals; the contact switches KM1 of the A-phase circuit, the B-phase circuit and the C-phase circuit correspond to the coil MJ in position; when the three-phase circuit carries out power supply, the three trigger circuits are conducted before the contact delay circuit, and after the contact delay circuit is conducted, the coil MJ can close the contact switch KM1 of the A-phase circuit, the B-phase circuit and the C-phase circuit. According to the embodiment of the invention, the contact switch KM1 of the A-phase circuit, the B-phase circuit and the C-phase circuit can be delayed to be closed through the contact delay circuit, and the conversion from soft switching to hard switching of the three-phase circuit is realized through the three trigger circuits, so that the arc discharge phenomenon is eliminated.

The invention discloses a high-speed Miller platform detection circuit for a GaN half-bridge gate driving chip, and relates to the technical field of power device driving. The circuit comprises a detection node, an RC series circuit, a positive pulse discharge path, a negative pulse voltage stabilization path and a signal isolation circuit. The RC series circuit couples the voltage jump delay of the floating ground to the detection node so as to generate a voltage pulse representing the starting point of the Miller platform; the positive pulse discharge module and the negative pulse clamping module are respectively connected in parallel between the detection node and the floating ground, and are used for rapidly discharging positive interference pulses and clamping negative pulses at safe voltage; and the signal isolation module is used for isolating a post-stage circuit load. The circuit is simple in structure, high in response speed and easy to integrate, the problems that a traditional detection scheme is large in delay and complex in circuit are solved, and key support is provided for a high-frequency GaN driving chip to achieve accurate active driving.

The invention discloses a method for testing the DC internal resistance of a supercapacitor, and belongs to the technical field of supercapacitors. According to the scheme, the voltage value of the super capacitor is continuously collected and recorded before the super capacitor stops discharging, the sampling frequency and the preset sampling point number are determined through repeated experiments, the whole process from collection to discharging stop to discharging rebound is ensured, collection is stopped after the preset sampling point number is collected, and the sampling efficiency is improved. And obtaining a discharge cut-off voltage and a discharge rebound voltage according to the collected data, and calculating the DC internal resistance of the supercapacitor. According to the invention, single-point acquisition is replaced by continuous acquisition, errors caused by capacitor charge adjustment after circuit delay and discharge stop are avoided, and the DC internal resistance test precision of the supercapacitor is improved.

The memory device that includes a planes with memory blocks that have memory cells arranged in word lines. The memory device also includes circuitry that is configured to receive a read command for a selected memory block of the plurality of planes. The circuitry is also configured to determine a count of planes of the plurality of planes that have memory blocks undergoing a block activation process, which includes ramping the plurality of word lines to a pass voltage. In response to the count being below or equal to a predetermined threshold, the circuitry begins the block activation process for the selected memory block. In response to the count being above the predetermined threshold, the circuitry delays the block activation process for the selected memory block until the number of planes that have memory blocks undergoing the block activation process is below the predetermined threshold.

This invention belongs to the field of integrated circuit technology and relates to a method for fabricating a radiation-hardened fault-tolerant trigger. The method includes constructing a radiation-hardened fault-tolerant trigger using three conventional D flip-flops, an XOR gate, a 2-to-1 selector, and two delay circuits. Input data is simultaneously written to both the primary and backup D flip-flops. After a specified delay, the input data is written to the third D flip-flop and compared with the data stored in the primary D flip-flop. If they match, the data stored in the primary D flip-flop is correct, and the 2-to-1 selector chooses the data stored in the primary D flip-flop as the output data. If they differ, the data stored in the primary D flip-flop is incorrect, and the 2-to-1 selector chooses the data stored in the backup D flip-flop as the output data. With this invention, regardless of which D flip-flop malfunctions due to radiation, the radiation-hardened fault-tolerant trigger can still output the correct value.

A technique capable of improving accuracy of an amount of delay of a sampling clock is provided. A semiconductor device includes: a communication device for wired communication; a delay adder circuit capable of adjusting an amount of delay of a clock to be received or transmitted by the communication device; and a control circuit controlling the amount of delay of the delay adder circuit. The communication device is configured to set a reception period or a transmission period of a normal frame and a reception period or a transmission period of a check frame in time division, and to confirm timing margins of setup and hold between data and a clock in the reception period or the transmission period of the check frame. The control circuit is configured to set the amount of delay in the normal frame, based on a confirmation result of the timing margins.

A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.

The invention relates to a power supply control circuit with double USB (Universal Serial Bus) power supplies. The power supply control circuit comprises a USB female head connector Main USB-A with a Type-A, a USB female head connector SUB USB-C with a Type-C, a restorable fuse PTC (Positive Temperature Coefficient), an overvoltage protection chip EFUSE with an OVP (Open Voltage Platform) set to be 5.6 V, a delay circuit Delay Switch logic with a hardware delay function, a protocol chip BC1.2 supporting a USB charge of BC1.2, and a double-pole double-throw switch USB2.0 SWITCH. The Type A and the Type C can be used for power supply at the same time, and power supply of the Type C is preferential (when the double USBs are in place, the Type C is mainly used for power supply, and the Type A uses the USB2.0 data service).

The invention discloses a two-phase non-overlapping clock circuit, an application method, equipment and a storage medium. The two-phase non-overlapping clock circuit comprises a delay circuit and a clock shaping circuit, the delay circuit is used for delaying an accessed clock signal, the clock signal comprises a reference clock signal and an inverted reference clock signal, the delay circuit at least comprises a first delay circuit and a second delay circuit, and the first delay circuit and the second delay circuit comprise a delay inverter and a load capacitor connected with the delay inverter; the first delay circuit is used for generating a first delay clock signal, and the second delay circuit is used for generating a second delay clock signal; and the clock shaping circuit is connected with the first delay circuit and the second delay circuit, and is used for carrying out logic interlocking and shaping processing on the clock signal, the first delay clock signal and the second delay clock signal, and outputting a first non-overlapping clock signal and a second non-overlapping clock signal. And the non-overlapping time between the two-phase clocks can be effectively controlled.

This invention enables multiple external devices connected in parallel to be correctly synchronized and driven. The FPGA 30 includes a delay control circuit that delays PWM1, PWM2, and PWM3 based on Sync1, Sync2, and Sync3. The delay control circuit includes: a phase difference detection circuit 40 (phase difference detection unit) that detects the phase difference of Sync1, Sync2, and Sync3 (input signals) input from the gate driver SiC 100; a phase difference time measurement circuit 50 (phase difference time measurement unit) that measures the phase difference time detected by the phase difference detection circuit 40; a correction rate integrator circuit 60 (integrator unit) that calculates an integrator value by adding / subtracting the previous phase difference time from the current phase difference time measured by the phase difference time measurement circuit 50; a delay time determination circuit 70 (delay time determination unit) that determines the delay time of PWM1, PWM2, and PWM3 (output signals) based on the integrator value calculated by the correction rate integrator circuit 60; and a delay circuit 80 (delay unit) that delays PWM1, PWM2, and PWM3 based on the determined delay time.

The application discloses a clock synchronization method, a clock synchronization device and high-speed communication equipment, and relates to the technical field of clock synchronization. In the clock synchronization method, first, a current clock input signal is compensated based on a first phase error signal predicted from a previous clock signal; then, a current phase error of the compensated current clock input signal is determined; a first clock adjustment signal for adjusting the current phase error is generated by a first compensation loop, and there is a circuit delay; a second compensation loop predicts a new phase error generated during the circuit delay of the first compensation loop, and generates a second clock adjustment signal for the new phase error; a third clock adjustment signal representing a current real clock phase deviation is calculated and synthesized based on the double clock adjustment signals; and finally, a next clock input signal is adjusted based on the third clock adjustment signal. Through the double compensation loops, the application eliminates the phase lag caused by the circuit delay, and significantly improves the clock synchronization accuracy.

The invention discloses an improved structure of a gate drive circuit, which comprises an input stage circuit, two groups of SR latches, a level migration circuit, a delay matching module, a buffer and a narrow pulse generator, the level migration circuit is composed of two parts of a main body circuit and a control circuit, the two groups of SR latches are used for generating non-overlapping signals, and the delay matching module is used for outputting the non-overlapping signals. The voltage is fed back to the grid electrode of the power tube by the level migration circuit, so that the high side is switched off before the low side is switched on, and the low side is also switched off before the high side is switched on to form sufficient dead time; a high-side PMOS (P-channel Metal Oxide Semiconductor) framework is matched with two groups of latches to guarantee dead time to improve the robustness of the driving circuit, so that the safety and the reliability of the circuit are improved, a skew latch is arranged on the high side, logic errors caused by dV / dt noise are fundamentally avoided, a capacitance coupling structure is added in the level shifting circuit to feed back voltage, and the circuit is simple in structure and convenient to operate. And the circuit enters a normal working state.

The invention relates to an integrated circuit performing loopback operation and a method of operating the same. An integrated circuit may include first to Nth data receiving circuits configured to receive first to Nth data through first to Nth data terminals based on a multi-phase clock to generate first to Nth multi-phase data, respectively, where N is an integer equal to or greater than 2; first to Nth delay circuits configured to delay first to Nth data having a selected phase among the first to Nth multi-phase data, respectively; a clock delay circuit configured to delay a clock having a selected phase in the multi-phase clock; and a loopback circuit configured to transfer the clock delayed by the clock delay circuit to a loopback clock terminal, and transfer one of the first to Nth data having the selected phase delayed by the first to Nth delay circuits to a loopback data terminal based on the clock delayed by the clock delay circuit.

The present disclosure provides a design method, device and equipment of an input-output circuit and a storage medium. The design method of the input-output circuit comprises: constructing a parameterized circuit unit corresponding to the input-output circuit; obtaining a circuit configuration parameter; and forming an input-output circuit of a memory according to the parameterized circuit unit and the circuit configuration parameter; wherein the input-output circuit is used to write data into the memory after delaying the data when the memory receives a data write operation instruction, and read data from the memory when the memory receives a data read operation instruction. In the present disclosure, the input-output circuit delays the written data, so that the time of data arrival matches the write clock inside the memory, and the problem of incorrect data writing is solved under the condition of reducing the power consumption of the memory. The input-output circuit keeps the time of data reading unchanged, avoiding the problem of incorrect data reading, thereby improving the reliability of the memory operation.

The application provides a test system and method for power electronic devices in extreme irradiation scenes, the system comprises: a current measurement module, comprising a plurality of parallel resistance paths, which converts real-time current flowing through the power electronic device to be tested into a voltage signal; a current judgment module, which compares the voltage signal with a set voltage threshold, and outputs a first control signal when the voltage signal exceeds the set voltage threshold; a circuit delay module, which receives the first control signal and starts counting, and outputs a second control signal when the duration of the first control signal reaches a preset delay parameter; a circuit selection module, which receives the second control signal and performs logical decoding to generate a path selection instruction, controls the conduction state of each resistance path in the current measurement module, adjusts the current flowing through the power electronic device to be tested, and limits the real-time current to a preset level; and an interactive control module, which is used for setting parameters in the test process and resetting the state of the test system.

The application discloses an optimization method and device of an integer divider. The optimization method comprises an integer division optimization method for division by 3. The integer division optimization method for division by 3 comprises: establishing a lookup table of quotient values and remainder values corresponding to division of a binary number with different bit powers 2^k by 3; wherein k is a non-negative integer; using a dividend to make a mask to extract quotient values and remainder values from the lookup table of quotient values and remainder values; summing all the extracted quotient values to obtain an initial quotient; summing all the extracted remainder values to obtain an initial remainder; according to the value of the initial remainder, correcting the initial remainder and simultaneously adjusting the initial quotient to output a final quotient and a final remainder meeting the requirements. The application can solve the technical problems of excessive resource consumption, huge circuit delay and complex implementation logic of existing high-precision integer dividers in the scenarios of division by 3, division by (2^n) * 3 and the like, and is especially suitable for the scenarios of specific integer division by 3, division by (2^n) * 3 and the like in FPGA / ASIC.

The invention provides a current control circuit of a power supply chip and a vehicle-mounted terminal, and the current control circuit comprises a control circuit which is connected with the power supply chip; the anti-backflow circuit is connected with the control circuit and an external load; the current limiting circuit is connected with the anti-backflow circuit and a power supply end; the time delay circuit is connected with the current limiting circuit and the power supply chip; wherein when the output current of the power supply end is greater than an over-current threshold value, the current limiting circuit is switched on and the anti-backflow circuit is switched off so as to control the time delay circuit to be switched on, the time delay circuit outputs a feedback signal to the power supply chip after delaying a preset time, and the power supply chip outputs a control signal according to the feedback signal. And the control circuit controls the anti-backflow circuit to stop outputting current according to the control signal. The technical problem of repeated opening and closing of the device in the current limiting process is solved, and the service life is prolonged.

The application discloses a low-power single-precision floating-point multiplier based on a logarithmic approximation algorithm and belongs to the technical field of integrated circuits.The application approximates and optimizes an accurate floating-point multiplier in multiple aspects, mainly including a preprocessing module and a mantissa multiplier.The application adopts a hybrid precision architecture combining a logarithmic approximation algorithm and probability statistical truncation compensation, and divides mantissa multiplication into high-weight segmented array multiplication and low-weight segmented logarithmic multiplication.The application retains accurate calculation of high-weight segments and realizes low-weight segment calculation at a low cost, and errors of various approximate circuits can be offset to each other.The approximate multiplier provided by the application can significantly improve accuracy and can achieve a better balance between hardware overhead and accuracy requirements.The floating-point multiplier has reconfigurability and can be reconfigured and designed according to accuracy requirements to realize fine-grained adjustment of accuracy.The application is suitable for fault-tolerant applications with requirements for circuit delay and power consumption.

Embodiments of the present application provide a clock frequency conversion system, method, processor, chip and electronic device, wherein the system comprises: a clock generation circuit, a delay phase-locked loop circuit and a clock selection circuit; the clock generation circuit is configured to generate a source clock signal; the delay phase-locked loop circuit is configured to perform delay processing for multiple iterations based on the source clock signal to obtain multiple delay clock signals with different phases; wherein the last delay clock signal is aligned with the source clock signal, and the phase difference between adjacent delay clock signals is uniformly changed; the source clock signal and part of the delay clock signals form multiple candidate clock signals input to the clock selection circuit; and the clock selection circuit is configured to select a signal edge from the multiple candidate clock signals, and a target clock signal after frequency conversion is formed by the selected signal edge. The embodiments of the present application can improve the frequency change speed of the clock signal and improve the performance of the chip.

An integrated circuit delay determination method and apparatus, and a device, a medium and a product. The method comprises: acquiring a directed acyclic graph of a clock net of a target integrated circuit, a preset timing path set and a preset timing exception rule set, wherein the timing exception rule set comprises a sub-graph rule corresponding to at least one timing exception rule (S202); on the basis of a plurality of key nodes in the sub-graph rule, determining an affected region corresponding to each timing exception rule, and on the basis of a preset microinstruction compiling method, determining microinstructions of a plurality of affected nodes within the affected regions (S204); on the basis of the microinstructions, performing classified discussion on each affected node, and on the basis of classified discussion results, determining one or more tags corresponding to each affected node, so as to obtain a timing exception tag graph on the basis of the tags and the affected regions (S206); and on the basis of a GPU platform and the timing exception tag graph, determining a delay corresponding to each timing path in the preset timing path set, so as to determine the maximum delay value and the minimum delay value of the target integrated circuit (S208).

A delay control circuit includes a delay circuit. The delay circuit is configured to receive an initial command signal, and to perform a non-clock-triggered delay processing on the initial command signal to obtain a target command signal. The initial command signal is generated based on an ECS operation mode, a time interval between the target command signal and the initial command signal meets a preset timing condition, the initial command signal is used for performing a first operation and the target command signal is used for performing a second operation.

A successive approximation register analog to digital converter includes a capacitor array circuit, a quantizer circuit, a delay adjustment circuit, a control logic circuit, and a detector circuitry. The capacitor array circuit samples input signals to generate first signals and is sequentially switched according to a first digital code. The quantizer circuit quantizes the first signals according to a first control signal to generate second signals and receives the first control signal via a signal path. The delay adjustment circuit is coupled in parallel with the signal path and selectively adjusts a propagation delay of the first control signal. The control logic circuit generates the first digital code according to the second signals. The detector circuitry detects whether a quantization of the quantizer circuit is completed to generate the first control signal.