479 results about "Cell design" patented technology

An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels / yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and then sensitivities of each performance variable to 15 each of the circuit parameters are determined. The memory cell design parameters and / or operating conditions of the memory cells are then adjusted in conformity with the sensitivities, resulting in improved memory yield and / or performance. Once a performance level is attained, the sensitivities can then be used to alter the probability distributions of the performance variables to achieve a higher yield. Multiple cell designs can be compared for performance, yield and sensitivity of performance variables to circuit parameters over particular environmental conditions in order to select the best cell design.

A magnetic memory cell comprises in-plane anisotropy tunneling magnetic junction (TMJ) and two fixed in-plane storage-stabilized layers, which splits on the both side of the data storage layer of the TMJ. The magnetizations of the said fixed in-plane storage-stabilized layers are all normal to that of the reference layer of TMJ but point to opposite direction. The existing of the storage-stabilized layers not only enhances the stability of the data storage, but also can reduce the critical current needed to flip the data storage layer via some specially added features.

A new magnetic memory cell comprises a perpendicular-anisotropy tunneling magnetic junction (TMJ) and a fixed in-plane spin-polarizing layer, which is separated from the perpendicular-anisotropy data storage layer of tunneling magnetic junction by a non-magnetic layer. The non-magnetic layer can be made of metallic or dielectric materials.

The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines on a 3F-pitch arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.

The invention relates to electrochemical cells having a jellyroll electrode assembly that includes a lithium-based negative electrode, a positive electrode with a coating comprising greater than about 94 wt. % of iron disulfide.

Disclosed are methods and devices for detection of bacteria based on recognition and infection of one or more selected strains of bacteria with bacteriophage genetically modified to cause production of an inducer molecule in the bacterium following phage infection. The inducer molecule is released from the infected bacterium and is detected by genetically modified bacterial bioreporter cells designed to emit bioluminescence upon stimulation by the inducer. Autoamplification of the bioluminescent signal permits detection of low levels of bacteria without sample enrichment. Also disclosed are methods of detection for select bacteria, and kits for detection of select bacteria based on the described technology.

Code compression techniques and decompression architectures for embedded systems are disclosed, providing good compression ratio while improving decompression time for VLIW instructions and reducing bus power consumption. The invention includes two fixed-to-variable (F2V) length code compression schemes based on a reduced arithmetic code compression algorithm combining arithmetic coding with probability models; a static probability model using static coding and semi-adaptive coding using a Markov model. Multi-bit decompression methods for the F2V techniques are presented, together with a parallel decompression scheme that tags and divides a compressed block into smaller sub-blocks. The Markov model provides better compression ratio, but the static model has a less complicated decompression unit design. The invention also includes two variable-to-fixed (V2F) length coding algorithms, one based on Tunstall coding and another on arithmetic coding. The V2F algorithms are also combined with a static model and a Markov model.

The invention discloses an address information feature extraction method based on a deep neural network model. According to the method, tasks such as text feature extraction, address standardization construction and semantic space fusion are converted into quantifiable deep neural network model construction and training optimization problems by utilizing a deep neural network architecture. Characters in an address are used as basic input units, a language model is designed to express the characters in a vectorization mode, and then the key technology of place name and address standardized construction is achieved through a neural network target task. Meanwhile, considering place name address space expression characteristics, proposing an address semantic-space characteristic fusion scheme,designing a weighted clustering method and a characteristic fusion model, and extracting a fusion vector fused with semantic characteristics and space characteristics from an address text of a natural language. The feature content extraction of the address information can be realized. The structure has high expansibility. The solution thinking of address information tasks can be unified. The method is of great significance to urban construction.

A toggle MTJ cell is disclosed that has a nearly balanced SAF free layer with two major sub-layers separated by an anti-parallel coupling layer. Within each major sub-layer, there is a plurality of minor sub-layers wherein adjacent minor sub-layers are separated by a parallel coupling layer. The parallel coupling layer is a non-magnetic layer that may be a one or more of Ta, Cu, Cr, Ru, Os, Re, Rh, Nb, Mo, W, Ir, and V, a metal oxide, or dusting of NiCr, Ta, Cu, or NiFeCr. Magnetic moments of major sub-layers are made to be nearly equal so that the net moment of the SAF free layer is essentially zero. The MTJ cell and SAF free layer preferably have an aspect ratio of from 1 to 5. Ferromagnetic coupling between minor sub-layers enables a lower write current and lower power consumption than conventional toggle cell designs.

A compact, robust, multifunctional and highly manufacturable rechargeable battery cell is provided. The cell design dedicates minimal internal volume to inert components of the cell. This is accomplished, in part, by providing multiple functionalities to individual cell components.

Intrinsic variations and challenging leakage control in current bulk-Si MOSFETs force undesired tradeoffs to be made and limit the scaling of SRAM circuits. Circuits and mechanisms are taught herein which improve leakage and noise margin in SRAM cells, such as those comprising either six-transistor (6-T) SRAM cell designs, or four-transistor (4-T) SRAM cell designs. The inventive SRAM cells utilize a feedback means coupling a portion of the storage node to a back-gate of an access transistor. Preferably feedback is coupled in this manner to both access transistors. SRAM cells designed with this built-in feedback achieve significant improvements in cell static noise margin (SNM) without area penalty. Use of the feedback scheme also results in the creation of a practical 4-T FinFET-based SRAM cell that achieves sub-100 pA per-cell standby current and offers similar improvements in SNM as the 6-T cell with feedback.

Roughly described, a memory device has a multilevel stack of conductive layers. Pillars oriented orthogonally to the substrate each include series-connected memory cells at cross-points between the pillars and the conductive layers. String select lines (SSLs) are disposed above the conductive layers, and bit lines are disposed above the SSLs. The pillars are arranged on a regular grid having a unit cell which is a non-rectangular parallelogram. The pillars may be arranged so as to define a number of parallel pillar lines, each having an acute angle θ>° relative to the bit line conductors, each line of pillars having n>1 pillars intersecting a common one of the SSL. The arrangement permits higher bit line density, a higher data rate due to increased parallelism, and a smaller number of SSLs, thereby reducing disturbance, reducing power consumption and reducing unit cell capacitance.

A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.

An electrolytic cell for generating a mixed oxidant that is rich in ozone is disclosed. The cell disassociates a brine solution to generate ozone and chlorine based oxidants. The improved cell design allows the ratio of ozone to the other oxidants to be optimized, thereby providing a more efficient sterilization solution. The ozone production is adjusted by adjusting the residence time of the brine solution in the cell and the orientation of the cell.

A lithium-ion battery including an electrodeposited anode material having a micron-scale, three-dimensional porous foam structure separated from interpenetrating cathode material that fills the void space of the porous foam structure by a thin solid-state electrolyte which has been reductively polymerized onto the anode material in a uniform and pinhole free manner, which will significantly reduce the distance which the Li-ions are required to traverse upon the charge / discharge of the battery cell over other types of Li-ion cell designs, and a procedure for fabricating the battery are described. The interpenetrating three-dimensional structure of the cell will also provide larger energy densities than conventional solid-state Li-ion cells based on thin-film technologies. The electrodeposited anode may include an intermetallic composition effective for reversibly intercalating Li-ions.

A photovoltaic element (110) is proposed for conversion of electromagnetic radiation to electrical energy and has a tandem-cell design. The tandem-cell design comprises the following: a dye solar cell (126) with a first electrode (118), an n-semiconductive metal oxide (120), a dye (122) which absorbs electromagnetic radiation in a first spectral range and a solid p-semiconductor (124); and an organic solar cell (130) with an acceptor material (132) and a donor material (134), with the acceptor material (132) and / or the donor material (134) comprising an organic material, with the organic solar cell (130) also comprising a second electrode (138) on a side opposite the dye solar cell (126), with the organic solar cell being designed to absorb electromagnetic radiation in a second spectral range, which is at least partially different from the first spectral range, with the first electrode (118) and / or the second electrode (138) being at least partially transparent for the electromagnetic radiation.

The present invention provides a method for producing a reversible solid oxide fuel cell, comprising the steps of: —providing a metallic support layer; —forming a cathode precursor layer on the metallic support layer; —forming an electrolyte layer on the cathode precursor layer; —sintering the obtained multilayer structure; —impregnating the cathode precursor layer so as to form a cathode layer; and —forming an anode layer on top of the electrolyte layer. Furthermore, a reversible SOFC is provided which is obtainable by said method. The method advantageously allows for a greater choice of anode materials, resulting in more freedom in cell design, depending on the desired application.

The present invention discloses a pixel display configuration by providing a voltage controller in each pixel control circuit for controlling the voltage inputted to the pixel electrodes. The controller includes a function of multiplexing the voltage input to the pixel electrodes and also a bit buffering and decoupling function to decouple and flexible change the input voltage level to the pixel electrodes. The controller further includes a first switching stage and a second switching stage and each stage has a P-type transistor and a N-type transistor to expand the range of the switching voltages such that the improvement of the pixel control is further enhanced. The rate of DC balancing can be increased to one KHz and higher to mitigate the possibility of DC offset effects and the image sticking problems caused by slow DC balancing rates. This invention further discloses an enabling technology for switching from one DC balance state to another without rewriting the data onto the panels. Therefore, it is not required to implement a high voltage CMOS designs and standard CMOS technologies can be applied to manufacture the storage cells and control panel for the LCOS displays with lower production cost and higher yields.

A driver assistance system for avoiding collisions comprisesa proximity sensor (8) for detecting an obstacle (3) on a predicted trajectory (14) of a vehicle (1);a computer unit (12) for searching for a first evasive trajectory (15), on which the vehicle can drive around the obstacle (3) without colliding, and for searching for a second evasive trajectory (19), which branches off the predicted trajectory (14) at a future point in time (18) and on which the vehicle can drive around the obstacle without colliding,a steering system (22) that can be activated by the computer unit (12) in order to steer the vehicle (1) along one of the evasive trajectories (15, 19),wherein the computer unit (12) is designed for only activating the steering system (22) and steering the vehicle (1) along the first evasive trajectory (15) if the search for the second evasive trajectory (19) is unsuccessful.

A battery electrode design and a flat stack battery cell design preferably include structure and / or manufacturing steps whereby a battery electrode plate has a frame, and a grid-array of elements disposed interiorly of the frame. A first collector pole access channel is disposed interiorly of the frame and orthogonal with respect to the grid-array of elements, and a second collector pole access channel is also disposed interiorly of the frame and orthogonal with respect to the grid-array of elements. Preferably, the collector pole access channels are made by hole-punching lead slugs integrally disposed in the grid-array. Preferably, the electrode plates are a standard size, and may be disposed in a common jar; thus, the battery capacity is determined by the number of electrode plates in the jar, the jar being trimmed per the number of electrode plates.

The invention discloses a zeroth-order resonator and a low-profile zeroth-order resonator omnidirectional circularly polarized antenna. The zero-order resonator is composed of a dielectric substrate, a metal patch, a metal floor and a short-circuit pin. The metal patch and the metal floor are respectively adhered on the two relatively parallel surfaces of the dielectric substrate. One end of the short-circuit pin is connected with the metal patch, and the other end is connected with the metal floor. The zeroth-order resonators are arranged at the external side of the radiation type feed network of the antenna in a surrounding way. Phase difference between two polarizations is enabled to be fixed at 90 degrees by the zeroth-order resonators, electric dipoles and magnetic dipoles are constructed by using a mode of circular ring group arrays, and the design of the zeroth-order resonator units and optimization of the circular ring array circularly polarized antenna are separated without considering the phase problem of two mutually perpendicular linear polarization components so that optimization efficiency can be enhanced, system resources can be saved and design efficiency can be enhanced. Besides, the designed omnidirectional circularly polarized antenna has the low-profile characteristic and can be applied to systems with the requirement for the antenna profile.

An SRAM design evaluation circuit topology has the gates of the SRAM cell pass Gate Field Effect Transistors (FETs) connected to the cross-coupled gates of the inverter pair of the SRAM cell. This evaluation circuit typology is used in a full cell implementation. A series of full cells are interconnected one to another in a loop to form a ring oscillator. The output of the ring is frequency divided and measured to study the read and write behavior of the cell design. Similarly, half-cells, with the gates of their pass gates grounded, are interconnected one to another to form a ring oscillator, the output of which is frequency divided and measured to help isolate pass gate impact on memory function. The modified SRAM cell topology, connected as a ring oscillator in hardware, can be used to fully characterize an SRAM cell design, without the use of peripheral read / write circuitry.

The invention is directed to an electrochemical cell having at least one of its electrodes produced by coating a slurry mixture of an active material, possibly a conductive additive, and a binder dispersed in a solvent and contacted to a perforated current collector foil. It is particularly important that the active slurry does not move through the perforations of the current collector. For this reason, a barrier is placed against the opposite side of the current collector to block the perforations as the current collector is being coated with the slurry. After volatilizing the solvent, a second, different active material is coated to the opposite side of the current collector, either as a slurry, a pressed powder, a pellet or a free standing sheet. An example of this is a cathode having a configuration of: SVO / current collector CFx. The opposed active materials on the current collector can also be of the same chemistry.

An efficient method and system for the electrochemical treatment of waste water comprising organic and / or inorganic pollutants is disclosed. The system comprises an electrolytic cell comprising a solid polymer, proton exchange membrane electrolyte operating without catholyte or other supporting electrolyte. The cell design and operating conditions chosen provide for significantly greater operating efficiency.

The invention discloses an online monitoring unit oriented to ultrawide voltage and a monitoring window self-adaptive adjusting system. Based on a traditional prediction type online time sequence monitoring unit, the online monitoring unit with an adjustable monitoring window is designed so as to adapt to the change of circuit delay at ultrawide voltage within a larger range. The invention further discloses the adjusting system, with the self-adaptive adjusting function, of the monitoring window. The window value can be adjusted in a self-adaptive mode within the ultrawide voltage range according to the monitored PVT (Process-Voltage-Temperature) state of a circuit, and therefore the reserved time sequence margin in traditional design can be fully reduced, and power consumption of the circuit is effectively reduced.

A electrochemical cell design, with particular applicability to lithium-iron disulfide batteries, is disclosed. The cell includes a spirally wound electrode assembly with a central core. The core causes uniform expansion within the cathode. The core may also collapse and / or possess a cross sectional shape that differs from the cross sectional shape of the cylindrical container which houses the electrode assembly.

The invention relates to the technical field of batteries, and provides a battery cell performance parameter acquisition method and device. The battery cell performance parameter acquisition method comprises the following steps: acquiring corrected parameters of a related battery; and obtaining cell performance parameters which are related to the battery and outputted by an electrochemical-thermalcoupling model of the battery according to the pre-established electrochemical-thermal coupling model and the correction parameters of the relevant battery. The battery cell performance parameters obtained through the battery cell performance parameter acquisition method is high in precision, the performance prediction at the early stage of cell design and data verification at the later stage ofcell design can be carried out, and the purposes of reducing test resources and accelerating the battery research and development progress can be achieved.