A method (100) for forming a
nanosheet-based
transistor device is provided. The method (100) comprises forming (105) a
shallow trench isolation, STI, structure (212) in a substrate (202), forming (110) a fin-shaped structure (214) from the substrate (202), a bottom sacrificial layer (204), and a stack of
layers (208, 210), forming (115) a dummy
gate stack (216) over a channel region of the fin-shaped structure (214), forming (120) a source / drain, S / D, recess (218) at a S / D region (218) of the fin-shaped structure (214), the S / D recess (218) extending through the stack of
layers (208, 210) and the bottom sacrificial layer (204), removing (125) the bottom sacrificial layer (204) thereby forming a
void space, depositing (130) a bottom
dielectric insulation, BDI, layer (220) in the
void space, extending (135) the S / D recess (218) further into the substrate (202), depositing (140) a via buried power rail, VBPR, plug (222) in the extended S / D recess (218), forming (145) an epitaxial, EPI, structure (224) to form a S / D feature (224) above the VBPR plug (222) in the S / D recess (218), removing (150) the dummy
gate stack (216), selectively removing (155) the plurality of sacrificial
layers (210) in the channel region, forming (160) a replacement
metal gate, RMG, structure (226) around each of the plurality of released channel layers (208),
thinning (165) the substrate (202) from a backside thereof, selectively
etching (170) the VBPR plug (222) to
expose the S / D feature (224), and forming a backside S / D electrical contact (238) at the S / D feature (224).