115 results about "Digital line" patented technology

The invention discloses a multi-agent collaborative short play digital production system, which belongs to the technical field of artificial intelligence, and comprises a data and state management module driven by a digital thread, which uniformly manages and synchronizes data, states and decisions of all production links through a throughout digital thread; the full-process intelligent production module takes an intelligent control center as a core, decomposes and dispatches a complex task to five professional intelligent agents for cooperative execution, and covers a complete production link from script generation, visual preview, video shooting and special effects to intelligent editing and final sound and picture synthesis; the man-machine collaborative evaluation and feedback closed-loop module provides an interactive interface for human experts to supervise, guide and correct key production nodes and records artificial decisions as feedback to form a closed loop of a continuous optimization system; according to the multi-agent collaborative short play digital production system provided by the invention, the digital thread penetrates through multi-agent collaboration, so that data tracing and state synchronization of the whole process of short play production can be realized, challenges such as narrative continuity, cross-modal consistency and physical authenticity are effectively solved, and the quality of generated content and the production efficiency are remarkably improved.

Methods and systems for generating live digital documents are provided. The method includes receiving a static document file including human-readable data. Then, parsing the static document file into a plurality of subunits. Then, generating a sharable document splice of the static document file. The sharable document splice includes access to a subset of the plurality of subunits, and the access is provided through an Application Programming Interface (API) or Software Development Kit (SDK) endpoint for each subunit in the subset. Then, executing a digital thread script to generate the live digital document from the sharable document splice and an input digital model representation, using API or SDK endpoints in the sharable document splice. The live digital document is configured through the digital thread script to reflect changes in the input digital model representation. Finally, adding execution metadata for the execution of the digital thread script to the live digital document.

A reference blade that allows a user to attach a reference surface to the body of a tape measuring device to allow for integrated measuring and marking / scribing a full line. The tape measuring device may be a digital linear tape measure. The reference blade couples to the body of the tape measure, which both secures the blade to the body as well as allows it to be removably detached and thereafter re-attached to the body at a specific and repeatable working location. The reference blade comes in a variety of sizes, shapes, and geometries and may be stored (in a different mounting state or attached) to the tape measure or externally. The reference blade addresses the need to provide the user with a sufficiently long surface that can be used for marking.

The invention provides a full-life-cycle health management system and method for radar security and protection equipment, belongs to the technical field of equipment monitoring, and solves the technical problems of low equipment health state precision and lack of security and protection maintenance decisions caused by incapability of monitoring the full life cycle of radar equipment in the prior art. The system comprises a data acquisition module used for acquiring and recording full life cycle data of equipment; the digital thread data processing module is used for constructing a time sequence feature sequence and carrying out data association to obtain a digital thread data chain; a health prediction module which carries a CNN time sequence prediction model and carries out health state prediction on the time sequence feature sequence; the full life cycle state management module is used for adjusting life cycle stages of the equipment; and the visual interaction and decision support module is used for displaying the real-time state of the equipment, performing visual analysis and generating a maintenance decision. The method is applied to health monitoring and maintenance decision making of radar security and protection equipment.

Some embodiments include an integrated assembly having a memory array over a substrate. The memory array includes a three-dimensional arrangement of memory cells. A sense amplifier is associated with the substrate and directly below the memory array. A vertically extending digit line passes through the arrangement of memory cells and is coupled with the sense amplifier. Some embodiments include an integrated assembly having a memory bank containing 64 memory data blocks arranged in a 16x4 configuration. Some embodiments include an integrated assembly having a memory bank containing 512 megabytes divided among 64 memory data blocks, each memory data block having 8 megabytes. The 64 memory data blocks are arranged in a configuration having a plurality of rows, each row containing two or more of the memory data blocks.

The application discloses a digital thread driven intelligent management system for a clinical laboratory, which comprises a system body, and the system body is operated through the following method, and the specific method comprises the following steps: obtaining patient historical records and same batch sample data from a pre-established database by collecting current test result data, and obtaining multimodal information containing original images, detection curves and trend deviations; determining potential abnormal patterns by processing the original images and the detection curves through an abnormality detection algorithm according to the multimodal information; if the abnormal patterns are inconsistent with historical comparison results, comparing previous results of the patient through a trend analysis algorithm to judge the trend deviation degree; obtaining critical project specific threshold values according to the trend deviation degree to obtain key clue recognition results; and the application aims to solve the problem that in the prior art, when facing critical value projects, comprehensive verification and rapid release cannot be balanced, resulting in poor quality control and efficiency of the clinical laboratory.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source / drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source / drain region and vertically oriented digit lines coupled to the first source / drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source / drain region and the vertically oriented digit lines by a dielectric.

A method used in forming memory circuitry comprising memory cells comprises forming vertically-alternating insulative tiers and memory-cell tiers. The memory cells individually comprise a horizontal transistor comprising a gate that comprises part of one of a plurality of horizontal conductive access lines that individually directly electrically couple together multiple of the gates of different ones of the horizontal transistors that are in the same memory-cell tier. The access lines extend horizontally from the memory-array region into a connection region. Over a same time period and using the same processing steps, digitlines are formed in the memory-array region that individually directly electrically couple to the horizontal transistors in different ones of the memory-cell tiers and conductive-via constructions are formed in the connection region that individually directly electrically couple to individual of the access lines. Other embodiments, including structure, are disclosed.

Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. Memory cells in the memory cell tiers individually comprise a horizontal transistor having a gate, a capacitor side, and a digitline side. The capacitor is electrically coupled with the horizontal transistor on the capacitor side. A digitline is electrically coupled with the horizontal transistor on the digitline side. The insulative tiers comprise an insulative material that is vertically between immediately-vertically-adjacent of the memory-cell tiers. The insulative material extends laterally beyond the digitline side and the capacitor side of the gates of immediately-vertically-adjacent of the memory cells. The insulative material is vertically thinnest laterally outward of the digitline side of the gates than at the capacitor side of the gates. Methods are disclosed.

A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices. The additional microelectronic device structure assembly is attached to the microelectronic device structure assembly by bonding the additional isolation material to the isolation material and by bonding the further contact structures to the contact structures and the additional contact structures. Microelectronic devices and electronic systems are also described.

A microelectronic device includes a memory array structure and a control circuitry structure overlying and bonded to the memory array structure. The memory array structure includes memory cells, digit lines, and word lines. The control circuitry structure includes a control circuitry region, digit line contact sections, and word line contact sections. The control circuitry region includes sense amplifier sections including sense amplifiers, and sub-word line driver sections including sub-word line drivers. The digit line contact sections are horizontally adjacent to the sense amplifier sections in a first direction and include contact structures coupled to the sense amplifiers and the digit lines. The word line contact sections are horizontally adjacent to the sub-word line driver sections in a second direction orthogonal to the first direction and include additional contact structures coupled to the sub-word line drivers and the word lines. Additional microelectronic devices, memory devices, and electronic systems are also described.

The present application relates to the technical field of equipment life cycle management, and specifically includes an aviation equipment full life cycle management method and system based on digital threads, the method comprising: acquiring process parameters of each stage, determining first digital thread master data and a first layer of associated test sequences, second digital thread master data and a second layer of associated test sequences, mapping the deviation of the physical equipment state and the virtual simulation state, and identifying the performance difference point under the cross-stage data correlation link; setting a management strategy for collaborative optimization. The technical problem of being unable to identify the cross-stage performance difference point equipment performance fluctuation root cause positioning in real time, causing the reliability of aviation equipment to be limited is solved, the first and second digital thread master data and the associated test sequences are constructed, the deviation of the physical equipment and the virtual simulation state is accurately mapped, the management strategy is set in combination with the double thread data and the performance difference point, and full life cycle collaborative optimization is performed, and the technical effect of effectively improving the equipment reliability is achieved.

This application discloses a power training end-to-end management system and method based on digital threads, belonging to the field of power training information management. The system uses a digital thread engine as its core hub, connecting data and business flows across modules such as training resources, information, examinations, and points. It anchors the entire lifecycle behavior trajectory of trainees through unique identifiers and timestamps, achieving dynamic mapping and real-time traceability of all elements. The digital thread engine incorporates an AI-MLP neural network and a lightweight GNN module, automatically identifying inflection points in skill development and knowledge gaps, accurately attributing them to long-term skill evolution. The examination management module employs an AI anti-cheating mechanism, enabling seamless post-exam learning. The training resource module connects to a digital twin model, supporting AR immersive practical training. This invention constructs a closed loop of "learning-practice-examination-evaluation-application," improving the accuracy and practicality of training, addressing pain points such as low efficiency in new energy operation and maintenance talent training and fragmented training management, and providing solid talent support for the new energy industry.

A variety of applications can include an apparatus having a memory device, where the memory device includes a digit line coupled to a access transistor of a memory device. The digit line can be at least partially buried below a top surface of substrate cell contacts to the access transistor. The top surface of the substrate cell contacts can be located at the surface of the substrate. The digit line can be formed in a separation of cell contacts first formation process flow or a digit line first formation process.

A supply voltage may be set using a local voltage regulator, such as a Digital Linear Voltage Regulators (DLVR). A DLVR may include a compensator, and the performance of the compensator may be affected by a dropout (DO) voltage. To improve the performance of a compensator, a number of compensator calculations may be pre-calculated to reduce the complexity of remaining real-time computations and enable compensator calculations to be completed within a single DLVR clock cycle. A DLVR may include a sense filter, and the DLVR transfer function (TF) may be modified using dynamic shaping of open loop gain and pole locations of a sense filter. The DO range associated with the DLVR TF may be changed according to a monitored DO(t) to reduce the sensitivity of a domain VMIN on dropout, which reduces power consumption, increases performance, and enables simplification of test flows.

The invention discloses a distributed cross-screen display method and system based on a digital thread, and relates to the field of distributed computing resource management.The method comprises the steps that in response to cross-screen operation of a user, a first device captures and generates an operation context information packet; the digital thread scheduler receives the operation context information packet and creates a digital thread instance corresponding to the screen-crossing task; the digital thread scheduler gathers user interaction event streams from the digital thread instance associated equipment, and models and analyzes the user interaction event streams based on a preset focus analysis rule base; when the residual signal intensity of the node with the highest priority in the attention migration priority list exceeds a preset threshold value, triggering a pre-scheduling decision process; and performing dynamic resource pre-scheduling and preheating operation on the target equipment and the target content area according to the resource state table. According to the invention, the target device can realize instant rendering and response directly based on the pre-heating ready resources, so that real non-perceptual cross-screen experience is realized on the system level.

This application relates to microelectronic devices including semiconductive pillar structures, and related methods and electronic systems. A microelectronic device includes semiconductive pillar structures each individually including a digit line contact region laterally disposed between two storage node contact regions. At least one of the semiconductive pillar structures includes a first end portion including a first storage node contact region, a second end portion including a second storage node contact region, and an intermediate portion between the first and second end portions and including a digit line contact region, a longitudinal axis of the first end portion being angularly oriented relative to a longitudinal axis of the intermediate portion. Related microelectronic devices, electronic systems, and methods are also described.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source / drain regions and a second source / drain regions separated by channel regions. Gates at the channel regions formed fully around every surface of the channel region as gate-all-around (GAA) structures separated from channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes connected to the second source / drain regions and digit lines connected to the first source / drain regions.

In some implementations, a memory device may receive, from a host device, an erase command associated with erasing host data from a portion of a memory. The memory device may determine that the portion of the memory is associated with a reliability risk. The memory device may perform, based on determining that the portion of the memory is associated with the reliability risk, an alternative erase scheme to erase the host data from the portion of the memory, wherein during a first portion of the alternative erase scheme, a first voltage is applied to even word lines and a second voltage, that is different from the first voltage, is applied to odd word lines, and wherein during a second portion of the alternative erase scheme, a third voltage is applied to the even word lines and a fourth voltage is applied to the odd word lines.

Some embodiments include an integrated component having a memory array on a substrate. A first sense amplifier circuitry is associated with the substrate and includes a sense amplifier located directly beneath the memory array. A vertically extending digital line is associated with the memory array and coupled to the first sense amplifier circuitry. A second sense amplifier circuitry is associated with the substrate and offset from the first sense amplifier circuitry. A control circuitry is configured to selectively couple the digital line to a voltage supply terminal or the second sense amplifier circuitry.

This application relates to a memory array with multiplexed select lines. In some cases, a memory cell of a memory device can include a storage component, a first transistor coupled with a word line, and a second transistor coupled with a first select line to selectively couple the memory cell with a first digit line. A third transistor can be coupled with the first digit line and a sensing component common to a set of digit lines and a set of select lines. A second select line can be coupled with the third transistor and configured to couple the sensing component with the first digit line and to couple the sensing component with a second digit line. The sensing component can determine a logic state stored by the memory cell based on a signal from the first digit line and a signal from the second digit line.

The present disclosure provides a dynamic random access memory (DRAM)-based one-time programming (OTP) memory device and a semiconductor package. The one-time programming memory device based on the dynamic random access memory comprises at least one memory bank which comprises a plurality of memory array blocks (MATs) arranged as a matrix. Each of the plural numbers MAT includes: a complex number line extending in a row direction; a plurality of bit lines extending in a column direction; and a plurality of memory cells located at corresponding intersections of the plurality of digital lines and the plurality of bit lines, each of the plurality of memory cells including a capacitor node. The capacitance nodes of the plurality of memory cells along the column direction in the memory bank are divided into a plurality of capacitance node sections, wherein at least two of the plurality of capacitance node sections are separately controllable.

Methods, systems, and devices for sensing a memory with shared sense components are described. A device may activate a word line and a plate line each coupled with a set of memory cells, where each memory cell of the set of memory cells is coupled with a respective digit line of a set of digit lines. The device may activate a set of switching components to couple each digit line of the set of digit lines with a respective sense component of a set of sense components, where each switching component of the set of switching components is coupled with a respective memory cell of the set of memory cells. The device may sense the set of memory cells based on activating the word line and the plate line and based on coupling the set of digit lines with the set of sense components.

The invention discloses a building full life cycle monitoring management system and method, and relates to the technical field of engineering management, and the method comprises the steps: constructing a digital thread topology, building an object passport and an object identifier, and forming a digital thread topology table; when a business document is formed in an engineering business link, uniformly packaging a thread event shell and associating the digital thread topology table to form a thread event flow, and updating object passport information at the same time; and according to the thread event flow, maintaining a full-cycle state record table compiled according to the object identifier, and executing permission check and precondition check to generate an instruction list and a gap exception list. According to the method, the full-cycle state record table is generated through the thread event flow, the ready item field and the event track field are compared and verified, the instruction list or the gap exception list is formed in combination with permission verification and precondition verification, and the certainty and interpretability of process propulsion are achieved.

The present invention relates to a computer-implemented method for processing digital line-scan data generated by a line-scan camera, in particular a TDI line-scan camera, by exposing an object that moves at least temporarily relative to the line-scan camera. The data thus generated comprises a plurality of one-dimensional image lines arranged in a temporal sequence.

The invention relates to memory circuitry and methods for forming memory circuitry. A method for forming memory circuitry including memory cells includes forming vertically alternating insulating levels and memory cell levels. The memory cells individually include horizontal transistors including gates including portions of one of a plurality of horizontal conductive access lines that individually, directly and electrically couple together multiple of the gates of different ones of the horizontal transistors located in the same memory cell level. The access lines extend horizontally from the memory array region into the connection region. Within the same time period and using the same processing step, digital lines individually electrically coupled directly to horizontal transistors in different ones of the memory cell levels are formed in the memory array region, and conductive path configurations individually electrically coupled directly to individual ones of the access lines are formed in the connection region. Other embodiments, including structures, are disclosed.

An electronic device may include multiple memory cells, multiple digit lines, and multiple sense amplifiers each coupled to a memory cell through a target digit line and including an output stage. The output stage may be configured to produce an output signal driving the target digit line. The target digit line may be directly adjacent to one or more adjacent digit lines. The output stage may be configured to receive one or more switching signals each indicative of a logic state of an adjacent digit line and to control a slew rate of the output signal in the target digit line using the received one or more switching signals.

The present application belongs to the field of industrial software and digital manufacturing technology, and particularly relates to a wind power equipment full life cycle digital clue construction method. The method comprises the following steps: step 1, constructing a unified data model covering the full life cycle of wind power equipment; step 2, constructing a digital clue framework; and step 3, business cooperation and feedback based on the digital clue. The method breaks through the data barriers among the design, manufacturing and operation stages by constructing a unified data model and a digital clue framework taking BOM as the main line, and realizes accurate mapping of full life cycle data and automatic business cooperation by using BOM dynamic mapping technology based on semantic understanding and a rule engine.

The present disclosure includes apparatuses and methods related to a sense amplifier balancing component in a memory. An example apparatus may include a sense amplifier connected to a first digital line and a second digital line; and a controller configured to: transmit a first activation signal to the first digital line at a first time during a compensation window, and transmit a second activation signal to the second digital line at a second time during the compensation window, wherein the first time and the second time have a time difference corresponding to a threshold voltage difference between the first digital line and the second digital line.

In some implementations, a memory device may receive a single-level cell (SLC) program command. The memory device may determine, based on at least one of a randomized variable associated with the memory or a program-erase cycle count associated with the memory, a program verify scheme to be performed when executing the SLC program command. The program verify scheme may be one of a scheme associated with performing a program verify operation on all of the one or more subblocks of memory, a scheme associated with performing the program verify operation on a subblock associated with each odd word line (WL) to be programmed, or a scheme associated with performing the program verify operation on a subblock associated with each even WL to be programmed. The memory device may execute the SLC program command by implementing the program verify scheme.