971 results about "Equalizer" patented technology

The invention discloses a time-frequency synchronization tracking and judging method based on GFSK (Gaussian Frequency Shift Keying). The method comprises the following steps: S1, positioning the initial position of a synchronization word by detecting a lead code; s2, extracting a fixed synchronization word, completing frame synchronization based on correlation matching, and positioning a starting point of an effective data segment; s3, a range cycle counter collects a central sampling point and two adjacent sampling points to form a candidate sampling point sequence; s4, dynamically and finely adjusting the range cycle counter to form a time sequence calibration sampling point sequence; s5, performing phase difference calculation on the time sequence calibration sampling point sequence, estimating continuous frequency offset and generating a compensation value; s6, applying the compensation value to construct a decision feedback equalizer with delay front and back terms; s7, performing interference suppression on the compensation sampling point sequence by using a decision feedback equalizer with delay front and back items, and outputting a soft decision value; and S8, executing three times of judgment, constructing a sliding reference sequence, and outputting a final bit judgment result. According to the method, the problem of poor GFSK demodulation robustness under Doppler disturbance is solved.

The invention discloses a dual-mode analog front end with a full-speed clock-free decision feedback equalizer (UC-DFE). The dual-mode analog front end comprises a terminating impedance matching network, a linear processing link, the UC-DFE and a signal output module, the terminating impedance matching network realizes broadband impedance matching and electrostatic protection; the linear processing link comprises a CTLE and a VGA and is used for compensating channel attenuation and expanding signal bandwidth; the UC-DFE comprises a summator, a static comparator, a delay unit and a feedback tap, and realizes high-speed signal processing and feedback equalization; and the signal output module converts the balanced signal into a target coding format and outputs the signal. According to the invention, the overall performance of the circuit is improved, the problems of time sequence tension, bandwidth limitation and the like of the traditional DFE architecture at a high speed are solved, and the circuit is suitable for 128Gbps high-speed PAM4 and NRZ signal transmission and shows better comprehensive performance.

The invention provides a motorcycle unlocking and locking method based on low-frequency radio frequency, Bluetooth and communication protocols, and the method comprises the steps: carrying out the phase compensation of a received signal through an iterative optimization equalizer coefficient until the phase distortion is effectively suppressed; a Kalman filtering algorithm is adopted to filter signals of a receiving end, and a filtered high-quality signal is obtained by establishing a state space model of the signals and updating state estimation by using observation values, so that interference of a multipath effect on a pairing process is reduced; in combination with a retransmission mode of a pairing protocol, dynamically adjusting retransmission parameters by tracking the response time and the success rate of a connection request; a Bluetooth pairing process is simulated, and connection success rates under different environment parameter settings are analyzed through a large number of simulation experiments, so that parameter selection of a pairing protocol is optimized.

A method for equalizing a data signal includes providing a data signal to a pair of input transistors that provides an output signal, contributing to the output signal, a first current or voltage that has a magnitude determined by a first weighted feedback signal using a first decision-feedback circuit that includes a first pullup circuit coupled to a drain of a first input transistor, and a first pulldown circuit coupled to the drain of the first input transistor, and contributing to the output signal, a second current or voltage that has a magnitude determined by a second weighted feedback signal using a second decision-feedback circuit that includes a second pullup circuit coupled between a drain of a second input transistor and the first voltage rail, and a second pulldown circuit coupled between the drain of the second input transistor and a second voltage rail.

The invention provides an equalization parameter adjusting method and circuit, a chip, a transceiver and a storage system. The method comprises the following steps: acquiring a transmission signal transmitted by a channel; extracting a plurality of equalization features from the transmission signal; determining a required feature set of each equalizer according to the plurality of equalization features, the plurality of channel features of the channel and a current required feature requirement of an equalization network model of at least one equalizer; and predicting a plurality of equalization parameters of each equalizer according to the equalization network model of each equalizer and the corresponding required feature set, and transmitting the plurality of equalization parameters to the corresponding equalizer, so that each equalizer performs signal compensation on the received signal according to the corresponding plurality of equalization parameters.

The invention discloses a self-adaptive suppression method and system for multi-band signal interference of a mobile terminal, and the method comprises the steps: collecting a multi-band radio-frequency signal power spectrum, extracting an interference feature vector, inputting the interference feature vector into a neural network prediction model, outputting future interference intensity probability distribution, generating a prediction frequency spectrum according to the probability distribution, and combining the current channel state information, pre-compensation processing is carried out through a double-level equalizer; the balancing strategy is dynamically adjusted according to the resource state of the mobile terminal, specifically, when the CPU load exceeds a first preset value or the electric quantity is lower than a second preset value, a second-level equalizer in the double-level equalizer is forbidden, and the steps S20-S40 are executed again till the CPU load and the electric quantity meet preset conditions; and a sliding window verification mechanism is adopted, DTW distances of the predicted frequency spectrum and the actually measured frequency spectrum are compared, and the frequency band weight coefficient of the feature extraction matrix is dynamically updated. According to the method, the signal interference suppression capability is improved through the synergistic effect of time-frequency feature enhancement, hybrid model prediction, dynamic resource scheduling and closed-loop optimization.

The invention relates to the technical field of distributed response, in particular to a distributed message dynamic response method based on websocket. The method comprises the following steps: constructing a distributed message service cluster to configure a websocket communication module, message middleware and a client for each service node, and providing a unified service access point to the outside through an Nginx load balancer, so as to automatically register and subscribe a global control theme to the message middleware and form a hierarchical theme subscription structure; when the client initiates a connection request, the connection is distributed and a secure channel is established; the client sends a service request message, packages the service request message into a standardized message format, and associates session information of the client at the same time; and receiving the session message, performing intelligent filtering, generating a response result, and pushing the response result to the client in real time. According to the invention, efficient processing and real-time response of messages in a distributed environment can be realized.

The invention relates to the technical field of artificial intelligence and digital audio signal processing, and particularly discloses a Karaoke all-in-one machine intelligent tuning method based on AI sound effect optimization, and the method comprises the steps: obtaining an original mixed audio signal sung by a user, and carrying out the preprocessing; processing the preprocessed audio by using a multi-source audio separation model based on a deep neural network, and extracting a human voice track and accompaniment components; extracting time-frequency domain features from the human voice track, and performing quantitative evaluation on the voice tension degree of the user in combination with the trained voice state recognition model; dynamically adjusting an equalizer and a dynamic range compression parameter according to an evaluation result to realize adaptive sound effect optimization; synthesizing the optimized voice and accompaniment and outputting the synthesized voice and accompaniment to monitoring equipment; and finally, establishing a personalized user behavior feature vector by collecting user singing performance and historical tuning data, and performing online fine tuning on a system strategy based on a deep Q network reinforcement learning mechanism to continuously optimize a tuning effect.

The invention discloses an optical fiber terahertz communication system optimization method based on artificial intelligence, and belongs to the technical field of communication. According to the method, four-dimensional constellation shaping is constructed by utilizing additional dimensions provided by two independent sidebands, and an end-to-end optimization framework is divided into a training stage and a deployment stage; in the training stage, firstly, an equalizer based on a pruning neural network and an equalized channel model based on a mixed density network are trained in sequence through receiving and transmitting of a random training sequence; then connecting a constellation shaper at a transmitting end with a demapper at a receiving end through an equalized channel model with fixed parameters, thereby considering full-link residual distortion and noise after equalization, and carrying out back propagation gradient to learn a globally optimal four-dimensional joint geometric probability constellation diagram to further approach the Shannon limit; and in the deployment stage, transmission of the bit stream is realized through coordination of the four-dimensional geometric shaping constellation table and the probability distribution obtained in the training stage and an equalizer at the receiving end and a demapper.

The invention discloses a debugging method and system of an audio system, and relates to the technical field of audio debugging, the method comprises the steps of S1, environmental acoustic analysis, S2, basic parameter presetting, S3, real-time monitoring and dynamic adjustment, and S4, adaptive optimizing.The layout of an equalizer or a loudspeaker is adjusted through environmental acoustic analysis; presetting basic parameters of the sound amplifying device and the microphone; real-time multi-band sampling, delay calibration and gain regulation are realized; adaptive optimization is carried out, algorithms such as noise reduction are started, stored parameters are scene presetting, and one-key calling and self-checking updating are supported; the environment is analyzed, the audio system is accurately debugged, the system is dynamically optimized, the tone quality and the debugging efficiency are improved, and diversified scene requirements are met.

The invention belongs to the technical field of optical communication, and particularly relates to a low-complexity digital pre-equalizer based on frequency domain comb pilot channel estimation. The device comprises a data sending module, a channel response test module and a digital signal pre-equalization module, the data sending module comprises an initial comb signal generation part and a frequency component phase rotation part; the channel response test module comprises a signal frequency difference estimation and recovery part and a channel amplitude-frequency and phase-frequency response test part; the digital signal pre-equalization module comprises a filtering coefficient generation part and a sending signal convolution pre-equalization part; according to the invention, a frequency domain comb pilot signal is sent to analyze channel amplitude-frequency and phase-frequency response, so that a pre-equalizer for pre-compensating channel response at a sending end is generated; the method has the characteristics of high granularity, high precision, robust transmission signal system and the like, and can be applied to various scenes such as polarization multiplexing long-distance single-carrier coherent optical transmission, mode multiplexing short-distance intensity modulation direct detection systems and the like.

A reconfigurable driver in an I / O circuit has a first transistor provided in a first pullup structure, a second transistor provided in a second pullup structure, and a control circuit that generates a control signal provided to a gate of the second transistor. A gate of the first transistor receives a data signal. The control signal is an inverted, delayed version of the data signal in a first mode. The control signal turns off the second transistor in a second mode. The control circuit generates the control signal using a version of the data signal when operated in a third mode. The second pullup structure may be used to provide one-shot equalization to an output of the reconfigurable driver when the second pullup structure is operated in the first mode. The second transistor may be a thin-oxide PMOS transistor. The first transistor may be a thin-oxide NMOS transistor.

The invention discloses a signal recovery method and device based on a continuous time linear equalizer. The method includes: determining attenuation data based on an attenuated target signal received from a channel; configuring a compensation gain of a continuous time linear equalizer according to the attenuation data, and starting the continuous time linear equalizer to perform first signal compensation on the received target signal based on the compensation gain to generate a first compensation target signal; and sending the first compensation target signal to a feedback equalizer configured with a fixed working stage number so as to perform signal recovery on the target signal. According to the invention, the adaptive complexity of the equalizer system can be reduced, and the data recovery precision is ensured.

This disclosure relates to a receiver device for pulse amplitude modulation (PAM) signals. The receiver device calculates a transmitter dispersion eye closure quaternary (TDECQ). The receiver device first obtains a signal, wherein the signal is based on a PAM signal sent by a transmitter device over a channel to the receiver device, and filters the obtained signal. Further, the transmitter device equalizes the filtered signal using a FFE with multiple taps, and filters the equalized signal output by the FFE using a 2-tap post filter, wherein high frequency noise caused by the FFE is compressed. The receiver device applies a Max-Log-Map (MLM) algorithm on the filtered signal output by the 2-tap post filter, reconstructs a signal constellation of the PAM signal based on the result of the MLM algorithm, and calculates a TDECQ based on the reconstructed signal constellation.

The utility model provides an equalizer adjustable circuit, an amplifier adjustable circuit and electronic equipment, and belongs to the technical field of equalizers. And the cross negative impedance module is used for compensating the input signal through negative impedance. And the adjustable current module is connected with the cross negative impedance module. And the adjustable current module is used for providing adjustable bias current for the cross negative impedance module so as to adjust the negative impedance generated by the cross negative impedance module through the adjustable bias current. By adjusting the current of the adjustable current module, the bias current of the cross negative impedance module can be adjusted, and then the negative impedance generated by the cross negative impedance module can be adjusted, so that the loss of the circuit and the frequency response characteristic can be optimized in bandwidth, gain, peak point and peak amplitude; the technical problem that a traditional equalizer circuit cannot adjust the circuit gain is solved, so that the circuit can achieve the equalization effect, and input signals are compensated and equalized.

The invention discloses a high-speed serial signal linear equalization circuit which comprises an input terminal, a continuous time linear equalizer (CTLE), a super source follower, a variable gain amplifier (VGA) and an adaptive feedback. The input end is connected with a 100-ohm internal resistance differential signal source of the transmitting end through a channel; the equalization circuit CTLE is connected to the output end of the input end connection module, two groups of resistance switches (RsMF and RsHF) of the CTLE module are respectively controlled by 4-bit binary codes to enable source degeneration resistors Rs of two stages of CTLEs to be variable, two groups of capacitance switches (CsMF and CsHF) are respectively controlled by 2-bit binary codes to enable source degeneration capacitors Cs of the two stages of CTLEs to be variable, and the two groups of capacitance switches (CsMF and CsHF) are respectively controlled by 2-bit binary codes to enable source degeneration capacitors Cs of the two stages of CTLEs to be variable. The change of a zero pole of the circuit is realized through the change of the source degeneration resistor Rs and the source degeneration capacitor Cs, and the adjustability of the difference between the high-frequency gain and the low-frequency gain of the circuit is realized, so that the multi-gear adjustability of the equalization capability is realized.

An equalizer includes a delay circuit configured to generate at least one delay signal based on at least one input signal, an encoding circuit configured to generate a plurality of driving signals and a connection switching signal, based on the input signal and the delay signal, a pre-driver configured to generate a plurality of driving switching signals based on the plurality of driving signals, a first differential circuit configured to generate a first differential output signal based on the plurality of driving switching signals, a second differential circuit configured to generate a second differential output signal based on the plurality of driving switching signals, and a connection circuit configured to adjust a connection between the first differential circuit and the second differential circuit based on the connection switching signal.

The invention discloses an LPO wired receiver adopting adaptive CTLE based on a genetic algorithm, and the receiver comprises an analog front end, a data sampler, an edge sampler, an error sampler, a 1: 32 demultiplexer, a verification module, an eye pattern monitor, a genetic algorithm module, clock recovery logic, and a clock path. The eye pattern monitor is used for calculating the eye pattern closure degree according to the data of the data sampler and the error of the error sampler and outputting the eye pattern closure degree to the genetic algorithm module; and the genetic algorithm module is used for realizing parameter adaptive control of a continuous time linear equalizer CTLE and a variable gain amplifier VGA in the analog front end. The invention aims to apply the genetic algorithm to the adaptive equalization of the adaptive continuous time linear equalizer, so that the adaptive continuous time linear equalizer has stronger global search capability and lower power consumption and is not easy to fall into local optimum, and the complexity and power consumption of the adaptive continuous time linear equalizer are reduced. And the real-time and energy-saving requirements are met.

The invention discloses a temperature compensation equalizer with adjustable equalization slope linearity, and relates to the technical field of microwave integrated circuits. The equalizer comprises a temperature compensation driving module and a temperature compensation equalization module. The temperature compensation driving module generates a control voltage changing along with the temperature by using the negative temperature characteristic of the diode. The temperature compensation equalization module comprises an equalization circuit formed by resonators and a pair of stacked switch tubes, and realizes a temperature compensation function by controlling voltage to adjust insertion loss; meanwhile, by changing the capacitance value of the equalization slope linearity adjusting capacitor C3 which is connected with the series resonator in parallel, the linearity of the equalization slope can be flexibly adjusted on the premise that the equalization quantity is kept unchanged. According to the invention, the temperature compensation and equalization functions are integrated, the structure is compact, the performance is stable, the slope linearity can be flexibly adjusted, and the device is suitable for gain frequency and temperature compensation in a broadband radio frequency link.

Hub node of a passive optical network, wherein the hub node includes a DSP (Digital Signal Processing) chain configured to: Receiving a signal burst from a leaf node in the passive optical network, wherein the signal burst comprises a frame including a payload and a frame header, the frame header comprising a clock and gain control section, a frame detection section and an equalizer section; Retrieving a clock phase of the leaf node from the clock-and-gain control section of the frame header; Estimation of the signal strength of a signal burst from the leaf node in the passive optical network; Compensation for differences in the signal power of the signal burst from the leaf node; Detecting a frame alignment sequence that indicates the arrival of the signal burst; Determination of MIMO (Multiple Input, Multiple Output) polarization filter coefficients from the frame alignment sequence; Aligning the phase between the X-polarization and Y-polarization of the signal burst using the MIMO polarization filter coefficients; and Determine the frequency offset estimate (FOE) of a local oscillator signal.

The invention discloses a continuous time linear equalizer which comprises a transconductance circuit, a transimpedance amplifier circuit and a common-mode voltage feedback circuit. The transconductance circuit comprises a pair of PMOS (P-channel Metal Oxide Semiconductor) tubes, a pair of NMOS (N-channel Metal Oxide Semiconductor) tubes, six current sources and two RC (Resistance-Capacitance) networks; two branches are arranged between the power supply and the ground. A grid electrode of the first PMOS tube is connected with a grid electrode of the first NMOS tube, a grid electrode of the second PMOS tube is connected with a grid electrode of the second NMOS tube, and the first PMOS tube and the second PMOS tube respectively receive a pair of differential input voltages. The drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and a pair of differential intermediate signals is output respectively. The circuit is simple in structure and only has a primary circuit; a complementary structure of PMOS input geminate transistors and NMOS input geminate transistors is adopted, bias current is utilized to the maximum extent, power consumption is low, and compared with a traditional circuit, the current utilization rate is improved; balancing of a wide frequency band can be realized under the condition of low power consumption, and the gain is high.

An integrated circuit device may include a transmission driver and an equalizer. The transmission driver may be configured to, in response to a transmission control data, transmit an output signal to an outside through a signal line in a transmission operation that outputs the output signal to the outside, and provide termination resistance in a reception operation that receives an input signal from the outside through the signal line. The equalizer may be configured to, in response to an equalizer control data, amplify high-frequency components of the output signal in the transmission operation, and to provide termination resistance in the reception operation.

A system including a memory sub-system controller to transmit a data signal via a communication channel. The system includes a receiver to receive the data signal from the memory sub-system controller via an interface, the receiver comprising a decision feedback equalizer (DFE) sub-system. The DFE sub-system includes a first data detector circuit including a first tap circuit, where the first data detector circuit generates, using a first reference voltage, a first subset of detected values corresponding to the data signal. The DFE sub-system includes a second data detector circuit including a second tap circuit, where the second data detector circuit generates a second subset of detected bit values corresponding to the data signal using a second reference voltage.

The invention provides a continuous time linear equalizer based on a low-pass and band-pass mixed structure. The continuous time linear equalizer comprises a frequency selection coupler, a low-pass transconductance unit, a band-pass transconductance unit and a load unit. The frequency selection coupler is used for separating the differential analog signal into a first voltage component in a first band-pass frequency range and a second voltage component in a low-pass frequency range, the first band-pass frequency range comprises a target frequency expected to be compensated, and the frequency in the first band-pass frequency range is greater than the frequency in the low-pass frequency range; the band-pass transconductance unit is used for converting the first voltage component into current and synchronously realizing gain amplification to obtain a first current signal; the low-pass transconductance unit is used for converting the second voltage component into current and synchronously realizing gain amplification to obtain a second current signal; the load unit is used for summing the first current signal and the second current signal and converting the sum to a differential output voltage signal. According to the invention, the frequency corresponding to the gain peak point and the gain amplitude can be improved.

A receiver device receives a signal transmitted to the receiver device over an optical communication channel and equalizes the signal using a multi-decision feedback equalizer of the receiver device. Equalizing the signal includes generating, using at least one decision feedback equalizer configured with a plurality of slicing thresholds, decisions on symbols transmitted to the receiver device, detecting that a decision made by the decision feedback equalizer is unreliable. Equalizing the signal also includes, in response to detecting that the decision is unreliable, tracking, for a tracking period, multiple decision paths that generate respective possible sequences of symbols transmitted to the receiver device, determining error energies in decisions made, during the tracking period, in respective decision paths, and selecting, based on a comparison between the respective error energies, a sequence of symbols generated in one of the multiple decision paths as an output of the multi-decision feedback equalizer.

Serializer / deserializer (SerDes) modules, equalizers, and equalization techniques having robust parameter initialization may substantially reduce convergence time. One illustrative equalizer includes: a discrete-time, finite impulse response (“FIR”) filter to convert a receive signal to a filtered signal; a decision element to determine channel symbols represented by the filtered signal; and a controller. The controller is configured to, for each of multiple values in a search range, estimate a performance of the equalizer based on the channel symbols and at least one of the filtered signal or an input signal to the decision element; configured to find a centroid value based on the performance for each of the multiple parameter values in the search range; and configured to derive an initial value for the parameter from the centroid value.

The invention provides an optical module and a link optimization method and system. The method comprises the following steps that: the microcontroller issues a gain value, so that the continuous time linear equalizer performs equalization processing on an input voltage signal; the time processing module is used for sampling a voltage signal output by the continuous time linear equalizer to obtain sampling data; and the microcontroller determines the gain configuration of the continuous time linear equalizer based on the sampling data under different gain values. Compared with the prior art, the power consumption and the time delay of the module are equal to those of a traditional LPO, and meanwhile, the self-adaptive capability which is only achieved by a DSP scheme in the past is obtained. The application scene and deployment flexibility of the LPO technology are expanded; and meanwhile, the link performance can be always maintained near the optimal point, so that the risk that the performance is continuously deteriorated until error codes occur is fundamentally avoided, and intelligent maintenance of the link state is realized.

Systems and methods are provided for a memory device that includes a decision feedback equalizer (DFE) reset generator configured to transmit a DFE reset signal to reset taps of a DFE. The memory device also includes an input buffer. The input buffer includes a data branch configured to output data from the input buffer for use downstream in the memory device. The input buffer also includes a DFE reset branch configured to reset the taps for the DFE based on the DFE reset signal. Moreover, resetting the taps using the DFE reset branch does not reset output data of the data branch.