The invention discloses a high-speed low-power-consumption two-step echo cancellation circuit based on a shared
delay chain, and belongs to the technical field of high-speed serial interfaces. The circuit comprises a central shared coarse tuning
delay chain, a plurality of tap modules sharing the
delay chain,
a weighting unit and a summing unit, the tap module comprises a fine adjustment delay stage, and multiplexes a
transmitter side multiphase
clock signal to perform phase fine adjustment; the weighting unit weighs the delay
signal replica, and the summing unit subtracts the delay
signal replica from the received signal after superposition so as to eliminate the echo. The
receiver system adopts a separated subtraction architecture, near-end echoes are eliminated in front of the input end of a continuous time linear
equalizer, far-end echoes are eliminated behind the output end of the continuous time linear
equalizer, and a
digital control logic module is additionally arranged to realize closed-loop
adaptive control. Through resource sharing and architecture optimization, the
power consumption and the
chip area are greatly reduced, wide-range and high-precision echo cancellation is realized, and the method is suitable for a data communication
system with 112Gb / s and higher rate.