The utility model provides a frequency hopping zero
intermediate frequency receiver circuit, which is characterized in that a
radio frequency amplification circuit is connected with the input end of a power distribution circuit through a controllable attenuation circuit, the output end of the power distribution circuit is respectively connected with the input ends of two orthogonal
demodulation circuits, the output end of a first PLL circuit is connected with the local oscillation end of a first orthogonal
demodulation circuit, and the output end of a second PLL circuit is connected with the local oscillation end of a second orthogonal
demodulation circuit. The output end of the second PLL circuit is connected with the local oscillation end of the second orthogonal demodulation circuit; two outputs of the first orthogonal demodulation circuit are respectively connected with the input end of the first
baseband pre-amplification circuit, and two outputs of the second orthogonal demodulation circuit are respectively connected with the input end of the second
baseband pre-amplification circuit; the two output ends of each
baseband pre-amplification circuit are respectively connected with the input end of the
electronic switch circuit, and the output end of the
electronic switch circuit is connected with the final-stage amplification circuit through the baseband filter circuit. The PLL load is not changed at the switching moment of the
electronic switch, the influence of PLL load traction can be obviously relieved, and the frequency
switching time is reduced by more than 80% compared with that of a traditional ping-pong phase-locked loop.