13 results about "Dither" patented technology

A segmented digital-to-analog converter (DAC). The segmented DAC includes at least two DAC segments. The DAC includes at least one overrange DAC configured to generate a dither subtraction signal based on an overrange DAC control data, and a dither control circuit configured to add a dither to the input data for the segmented DAC and generate the overrange DAC control data to compensate the dither. The dither subtraction signal is combined with the output signals of the DAC segments in an analog domain. The DAC includes a segment mismatch correction circuit configured to modify the input data for the segmented DAC or input data for at least one segment to correct a mismatch error of one or more of the segments and / or the at least one overrange DAC.

The invention relates to quantization error and spurious suppression in digital phase-locked loops. A digital phase locked loop (DPLL) may include a dither source to provide a dither signal at an order to reach an integer bit over a set of fractional bits of a modulated signal. The DPLL may include a digitally controlled oscillator (DCO) to generate a DPLL output signal. The DPLL may include: a main delta-sigma modulator (DSM) for driving a main capacitor bank of the DCO based on a dither signal and a modulation signal; a first auxiliary DSM, associated with eliminating the influence of the dither signal on the DPLL output signal, for driving a first auxiliary capacitor bank of the DCO based on the dither signal; and a second auxiliary DSM for driving a second auxiliary capacitor bank of the DCO based on the modulation signal and the dither signal, associated with eliminating the effects of the quantization error of the main DSM.

To record images while suppressing the degradation of image quality due to beading, etc. [Solution] The first number, which is the number of pixels that overlap between a dot arrangement having a value lower than the median of all tones in the first dither pattern and a dot arrangement having a value lower than the median of all tones in the second dither pattern, is controlled to be greater than the second number, which is the number of pixels that overlap between a dot arrangement having a value higher than the median of all tones in the first dither pattern and a dot arrangement having a value lower than the median of all tones in the second dither pattern.

The application discloses a Dither signal generation method, a circuit and a Sigma Delta modulator. The Dither signal generation circuit is applied to the Sigma Delta modulator, and the Dither generation circuit comprises a random number generation unit, a first delay unit, a first adder unit, a first gain unit, a second delay unit and a second adder unit. Thus, only 1 bit of random number is needed to generate 7 kinds of Dither levels, the design requirement of the random number is reduced, the hardware cost is saved, and the transfer function of the control code is ingeniously designed, so that the Dither signal has a first-order shaping effect, and the precision loss of the modulator caused by the Dither D / A conversion error is greatly reduced.

Electronic devices, circuitry, and methods are provided to efficiently generate a dither signal. An electronic device may include an output device, such as a speaker, to output a media signal, such as an audio signal, based on dithered media data, such as dithered audio data. The electronic device may include dithering circuitry to generate a dither signal, based on a first pseudorandom signal from a first linear feedback shift register and a second pseudorandom signal from a second linear feedback shift register, to add to the media signal to generate the dithered media signal.

The invention discloses a jitter injection circuit for comparator foreground calibration. The jitter injection circuit comprises a gain amplifier circuit, a resistance feedback network circuit, a current mirror circuit, a current selection switch circuit, a shunt resistor and a resistor string circuit, wherein the gain amplifier circuit is respectively connected with the resistance feedback network circuit and the current mirror circuit; the resistance feedback network circuit, the current mirror circuit and the current selection switch circuit are respectively connected with the shunt resistor; and the resistor string circuit is respectively connected with the shunt resistor and the current selection switch circuit. According to the invention, accurate control of dither (jitter) injection amplitude is realized.

The invention discloses a pipeline successive approximation analog-to-digital converter calibration method, device and equipment, relates to the technical field of analog-to-digital converters, and aims to solve the problem that calibration is inaccurate due to the fact that large residual error swing is introduced when pseudo-random sequence injection is carried out in an existing Piped SAR ADC calibration method. The method comprises the steps of obtaining a to-be-compared signal; successive approximation comparison is carried out based on the to-be-compared signal and the two comparators, a jitter injection flag bit corresponding to each cycle is determined, pseudo-random sequence injection is carried out according to the jitter injection flag bit, and residual error voltage is obtained; determining a finely quantized digital code based on the residual voltage; carrying out iterative calculation on the bit weight by adopting a minimum mean square algorithm until a convergence condition is met, and obtaining a target bit weight; and performing calibration based on the target bit weight. The streamline successive approximation analog-to-digital converter calibration method provided by the invention is used for reducing residual error swing caused by pseudo-random sequence injection and improving calibration accuracy.

A digital phase-locked loop (DPLL) can include a dither source to provide a dither signal of up to one integer bit on a set of fractional bits of a modulation signal. The DPLL can include a digitally controlled oscillator (DCO) to generate a DPLL output signal. The DPLL can include a primary delta-sigma modulator (DSM) to drive a primary capacitor bank of the DCO based on the dither signal and the modulation signal; a first auxiliary DSM to drive a first auxiliary capacitor bank of the DCO based on the dither signal, thereby canceling any effect of the dither signal on the DPLL output signal; and a second auxiliary DSM to drive a second auxiliary capacitor bank of the DCO based on the modulation signal and the dither signal, thereby canceling any effect of a quantization error in the primary DSM.

An analog-to-digital converter (ADC) includes bit trial circuitry configured to perform ADC bit trials that compare an input signal to states of weighted circuit elements, a dither digital-to-analog converter (DAC) to receive a dither sequence and apply a dither signal to the bit trial circuitry, and calibration circuitry. The calibration circuitry is configured to input a dither sequence into the ADC bit trials as dithered bit trials; determine an effect of the dither sequence on results of the dithered bit trials; and update correction factors used to adjust results of the ADC bit trials using the determined effect of the dither sequence.

A dither signal filtering and sampling method based on a TFLN laser. The method comprises: step 1, loading a fundamental wave / second harmonic of a low-frequency dither signal into a photo-generated current of an optical module; step 2, amplifying, by means of an operational amplifier circuit, a photo-generated current signal loaded with the fundamental wave / second harmonic of the dither signal, and then splitting the amplified photo-generated current signal into two outputs; step 3, passing a first output of the two outputs through a low-pass RC filter circuit and then performing optical power sampling to monitor an output optical power, and splitting a second output of the two outputs into a fundamental wave branch and a second harmonic branch; and step 4, passing the fundamental wave branch and the second harmonic branch through corresponding frequency-selective filtering and amplification circuits and subsequent amplification and biasing circuits, respectively, so as to obtain a fundamental wave signal and a second harmonic signal, and outputting the fundamental wave signal and the second harmonic signal to an ADC sampling module for sampling. The present invention achieves effective sampling of a fundamental wave and a second harmonic of dither.

1. The name of the design product: laser gyroscope parameter debugging graphical user interface for electronic device. 2. The use of the design product: for running laser gyroscope parameter debugging program and displaying parameter debugging results on electronic device. 3. The design points of the design product: graphical user interface on electronic device. 4. The picture or photo that best shows the design points: front view. 5. The electronic device is a common design, and the rear view, left view, right view, top view and bottom view are omitted. 6. The use of the graphical user interface: when the software is opened, enter the front view, click the power-on, start dithering, start high voltage, and start frequency stabilization buttons on the test bench, and the gyroscope starts normally. Click the "zero offset / dither frequency" button, the interface changes to interface change state figure 1, and the zero offset and dither frequency data change curves can be viewed; click the "light intensity / frequency stabilization" button, the interface changes to interface change state figure 2, and the DC light intensity and frequency stabilization data change curves can be viewed; click the "sum frequency / difference frequency" button, the interface changes to interface change state figure 3, and the sum frequency and difference frequency data change curves can be viewed; click the "dithering" button, the interface changes to interface change state figure 4, and the dithering drive and dithering feedback data change curves can be viewed; click the "temperature" button, the interface changes to interface change state figure 5, and the temperature data change curves of the four zones can be viewed; click the "BS" button, the interface changes to interface change state figure 6, and the BS data change curves can be viewed; click the "DATA" button, the interface changes to interface change state figure 7, and the real-time data of zero offset, dither frequency, DC light intensity, frequency stabilization, sum frequency, difference frequency, and temperature of the four zones can be viewed.

The application discloses a polar self-control wideband large-amplitude dither structure applied to differential input, which comprises a counter, two zero-crossing comparators, an improved PN code generator, a DAC, a register, two adders, a differential ADC, a look-up table module, a delay module and a subtractor; the zero-crossing comparator added at the input end can control the positive and negative polarity of random noise with low complexity, and ensures that the final signal amplitude does not exceed the quantization range; in addition to the method of combining the multiplication congruence method with the Fibonacci sequence, the initial sequence generated by the Fibonacci sequence is changed by using an improved random number generation formula, so that the randomness is enhanced; a group of different uniformly distributed random sequences is generated by using a simple logic structure for the generated PN code for differential input; the PN code corresponding to the differential input structure ADC is added, so that the application range of the structure is widened; and the operation demand is not obviously increased, the structure is simple, and the overall complexity is low.