34 results about "Total delay" patented technology

The invention relates to the technical field of chip design, and provides a critical path screening method based on a chip time sequence report, which comprises the following steps: collecting chip time sequence report data, screening out first N critical paths from the data based on time sequence index data, and establishing a path ID-delay type-scene three-dimensional data model; and calculating the delay ratio of the unit delay to the interconnection line delay in each critical path. Performing single-type delay, type relevance and RC condition influence comparison on different scenes to obtain delay characteristic data. The invention discloses a system for executing the method, which can avoid full data redundancy and improve the analysis efficiency by screening the first N critical paths. And the delay change rule in different scenes is quantified. The delay characteristic data reflects the actual influence of the key path delay on the time sequence, so that a designer can quickly position the delay bottleneck of the key path, and a basis and a reference are provided for the targeted optimization of the total delay of the chip in the later period.

The invention provides a scene port entering and leaving aircraft joint optimization scheduling method. The method comprises the following steps: aiming at aircrafts which take off and land on a plurality of parallel runways in an airport, establishing a mixed integer programming model for a scene port entering and leaving aircraft IASP; setting a target function and a constraint condition of an IASTP problem by taking minimization of the total delay duration of the port entering and leaving aircrafts as a target; and based on the constraint conditions, solving a target function of the IASTP problem by adopting a heuristic algorithm based on VNS, and obtaining a comprehensive scheduling scheme of runway and sliding path distribution, take-off and landing sequence and time of the port entering and leaving aircraft. According to the method, actual operation constraints of various scenes are considered, runway distribution and sorting, taxiing path selection and taxiway scheduling of the port entering and leaving aircrafts, and a deducing sorting scheduling scheme of the port leaving aircrafts are planned and optimized as a whole, the take-off and landing delay time of the port entering and leaving aircrafts is shortened as much as possible, the hub airport operation efficiency is improved, and the airport landing time is shortened. And decision support is provided for efficient scheduling of aircrafts.

The invention provides an energy storage equipment phase synchronization control method and an energy storage system, relates to the technical field of energy storage equipment, and aims to solve the problem of phase tracking lag of slave machines caused by communication link delay when multiple machines are connected in parallel. The energy storage device phase synchronization control method comprises the steps that a first synchronization frame is received from a first energy storage device, and the first synchronization frame comprises a first voltage phase; a second synchronization frame is received from the first energy storage device, the second synchronization frame comprises a first time difference, and the first time difference is the difference value between the sending completion time and the sending start time of the first synchronization frame; calculating a second time difference based on a first reception time of the first synchronization frame and a second reception time of the second synchronization frame; and performing phase synchronization based on the first voltage phase, the first time difference and the second time difference. According to the phase synchronization control method, the communication processing total delay of the whole link is actively calculated, then the real-time phase of the host at the current moment is dynamically predicted, and finally accurate synchronization without lag errors is achieved.

A method for edge cache replacement based on deep reinforcement learning is provided, including: constructing a system network model; obtaining a caching state of an MEC server in the system network model; calculating a total delay for all users to obtain cached contents based on a total delay for a single user to obtain a cached content; constructing an optimization objective function based on the total delay for all users to obtain the cached contents; formulating a Markov decision process according to the optimization objective function; and replacing the cached content of the MEC server using a dynamic content replacement algorithm based on deep reinforcement learning according to the Markov decision process. According to a condition of a cache space of the MEC server, the system network model can obtain a minimum average delay for users to obtain contents and find a most suitable cache replacement policy.

The present application belongs to the technical field of mobile edge computing microservice, and particularly relates to an edge computing microservice deployment and task scheduling method based on microcell architecture in a 5G and Internet of Vehicles scenario.The method comprises the following steps: firstly, describing an edge computing network structure based on microcells in a 5G scenario; on this basis, systematically modeling the microservice deployment and task scheduling problem, with the optimization target being to minimize the delay of all users, which is mainly manifested as processing data upload delay; then, decomposing and completely solving the sub-problems to transform the original problem into a linear integer programming problem; and using an L2Box-ADMM algorithm to solve the linear integer programming problem.Test results show that, compared with other microservice deployment and task scheduling algorithms, the algorithm of the present application can find a microservice deployment and task scheduling strategy that satisfies the resource constraint condition and has smaller total delay, and can reduce the gap with the optimal solution by 35%.

The application discloses a task scheduling method and device based on a distributed large language model, terminal equipment and a storage medium. The method comprises the following steps: obtaining communication data of each device node in a multi-layer network of the distributed large language model, a to-be-scheduled task, a task feature of the to-be-scheduled task, and real-time monitoring data of each device node; then, according to the communication data, the to-be-scheduled task, the task feature of the to-be-scheduled task, and the real-time monitoring data of each device node, performing model segmentation and task scheduling on the multi-layer network with the minimum total delay of the multi-layer network as the target, obtaining a target device node corresponding to each to-be-scheduled task, and distributing each to-be-scheduled task to the corresponding target device node for scheduling. Through implementation of the application, resource management of the multi-layer network in the large language model can be realized, the performance of the network is improved, and the delay is reduced.

The invention discloses an order type task scheduling optimization method and system, and relates to the technical field of task scheduling and control optimization, and the method comprises the steps: constructing an order type task scheduling control model; by constructing a dual-objective function of total delay time minimization and overall execution efficiency maximization, global optimization of task resource allocation is achieved, it is clear that task execution time resources do not exceed the maximum processing duration, and the situation that due to excessive optimization, resources are occupied by a single task for a long time, and the task execution efficiency is improved is prevented. Two objective functions of total delay time and average processing efficiency are constructed, the total delay time objective function can reflect the influence of the task queuing length on the execution efficiency, a penalty term is introduced into a scheme violating constraints, the evaluation weight of the scheme is reduced, it is ensured that the generated scheduling scheme meets both the optimization objective and the actual constraint condition, and the scheduling efficiency is improved. The frontier solution set is generated through iterative solution, conversion of task planning from static rules to dynamic optimization is achieved, and an efficient and reliable solution is provided for an intelligent task management system.

The embodiment of the invention relates to an information processing method and device, equipment and a medium. The method comprises the steps of obtaining first task information of a to-be-executed data production task and a planned execution moment of the data production task; generating first estimation information corresponding to the data production task based on the first task information; the first pre-estimation information at least comprises a first pre-estimation duration required by the target cluster to execute the data production task; obtaining target reference information, and estimating a total delay duration corresponding to the data production task based on the target reference information; the target reference information comprises one or more of resource information of the target cluster, second task information of an upstream task on which the data production task depends, and fault information of the target cluster; and determining an estimated completion moment of the data production task based on the planned execution moment, the first estimated duration and the total delay duration. According to the embodiment of the invention, the accuracy of the estimated completion time of the finally obtained data production task can be fully guaranteed.

The invention relates to the technical field of computers and data processing, discloses a streaming transmission and low-delay decoding method based on a cloud game, and aims to solve the problems of high transmission delay, low coding and decoding efficiency and split interaction response in the prior art. The method comprises the following steps: extracting dynamic characteristics of a game picture, dynamically adjusting a coding rate and a resolution ratio through a reinforcement learning model based on network state parameters and the dynamic characteristics, generating a current frame prediction result by using an AI prediction model, and preferentially transmitting a key frame patch, decoding is accelerated through a special hardware decoding chip, asynchronous rapid decoding is adopted for key frame patches, and frames and user input events are decoded synchronously to control the end-to-end total delay to be smaller than or equal to 50 ms. According to the technical scheme, the loss rate and the average transmission delay of the key picture area can be remarkably reduced, the decoding delay is reduced, it is ensured that the total delay is stabilized within 50 ms, and the interaction synchronism and the operation response accuracy of the high-speed dynamic game are improved.

The invention provides a flight delay recovery method and device, computer equipment and a storage medium, and belongs to the field of aviation operation and maintaining.The method comprises the steps that the minimum total delay economic loss, the total delay duration and the delay duration standard deviation serve as optimization objectives; establishing an optimization model by taking aircraft resource allocation, unit task connection, passenger travel guarantee, ground guarantee resource collaboration and airport time slot capacity limitation as constraint conditions; a Harris eagle optimization algorithm is used as a basic algorithm, and a dynamic balance pool mechanism and a transverse crossing mechanism are introduced for improvement; and carrying out optimization solution on the optimization model by utilizing an improved Harris eagle optimization algorithm to generate a flight recovery scheme. In this way, a mathematical model which takes a plurality of key indexes as optimization targets and comprehensively considers multi-dimensional operation rule constraints is established, and complex scenes and requirements of flight recovery can be described more comprehensively and accurately.

This invention discloses a chip prototype verification method, apparatus, product, equipment, and medium, relating to the field of circuit technology. This invention is applied to a verification system containing main and sub-verification boards. The sub-verification board is equipped with a first delay counter, and the main verification board is equipped with a second delay counter and an interrupt generation module. The method includes: obtaining the first delay value of the valid data signal and the original interrupt signal from the sub-verification board using the first delay counter; sending the service data, the two signals, and the first delay value to the main verification board; writing the service data into an external memory; obtaining the second delay value of the two signals received by the main verification board using the second delay counter; if the total delay value exceeds a preset clock cycle threshold, after all service data is written to the external memory, the interrupt generation module generates a target interrupt signal based on the first delay value and sends it to the main control unit; the main control unit reads the data from the external memory to complete the prototype verification. This method can accurately calculate inter-board delays, avoid timing offsets, and achieve accurate prototype correction.

The invention discloses a data processing method, device and equipment, and relates to the technical field of computers, which comprises the following steps of: simultaneously carrying out erasure code coding calculation and cyclic redundancy check calculation on a data block in a continuous time period when original data is loaded to a processor cache, so that multiple calculation operations on the same data are completed in a cache period, and the data processing efficiency is improved. The time for waiting for data loading of the processor and the memory bandwidth occupation are reduced, the cache utilization rate is improved, the total delay of data processing is reduced, and the input / output path is shortened. Therefore, the technical problems of repeated data loading and frequent swap-in and swap-out of the cache caused by multiple serial calculations are solved, and the technical effect of improving the data processing efficiency and the throughput capacity is achieved.

The application discloses a dense false target generation method based on segmentation reconstruction, which is applied to an FPGA provided with an IIR filter, a feedback branch of the IIR filter is provided with a register, and a forward branch of the IIR filter is connected with a RAM, and the method comprises the following steps: saving signals collected by a DRFM into the RAM; according to a minimum segmentation length, signal segments at each moment are sequentially obtained from the DRFM, and after register delay and accumulation, corresponding accumulated values at each moment are obtained; after the obtained signal segments reach a given false target number M, signal segments before M moments at each moment are sequentially obtained from a starting position of the external RAM according to the minimum segmentation length, and the corresponding accumulated values at each moment are subtracted from corresponding signal segment data obtained from the external RAM, and the corresponding accumulated values at each moment are taken as data of signal segments at each moment of the dense false target signal. The application overcomes the problem that the segmentation reconstruction method consumes too much storage resource when the total delay length is large.

The application discloses a multi-user task offloading calculation method, system and device and a storage medium, belongs to the wireless communication technical field, and comprises the following steps: calculating the channel transmission rate of user task offloading to a small base station and the channel transmission rate of user task being forwarded to a macro base station through the small base station; calculating the transmission delay of user task offloading to the small base station and the transmission delay of user task being forwarded to the macro base station through the small base station according to the two channel transmission rates; calculating the processing delay of user task calculation at the small base station and the macro base station; inputting the two transmission delays and the two processing delays into a task offloading and calculation resource joint allocation model based on delay minimization which is constructed, and obtaining the optimal allocation scheme of MEC calculation resources in the small base station and the macro base station by solving; and based on the optimal allocation scheme, user task is offloaded to the small base station and the macro base station for calculation; the application reduces the total delay of user task processing through joint optimization of task offloading and calculation resource allocation.

The application provides a multi-task edge computing method for an Internet of Things, and belongs to the technical field of edge computing, and comprises the following steps: collecting task state information of to-be-processed tasks generated by a task collector of a monitoring area of the Internet of Things and a transmission queue and a computing queue reported by an edge server; inputting the task state information into an intelligent agent to output a scheduling decision of the to-be-processed tasks; determining a task that needs to be unloaded and a target server for unloading according to the scheduling decision, and creating a virtual task in a computing queue of the target server; determining an expected arrival order of the task that needs to be unloaded in the target server according to a generation time of the task that needs to be unloaded and a waiting time of the virtual task, calculating a total delay and a total energy consumption, updating the intelligent agent based on queue perception TD3, and obtaining an optimal scheduling decision. The application solves the problem that, in the prior art, the influence of transmission delay of task unloading between servers on the order of a computing queue is ignored, resulting in inaccurate task scheduling.

The invention discloses a flexible job shop scheduling method oriented to date of delivery constraints. The method is oriented to date of delivery constraints, takes total tardiness and maximum completion time into account, establishes a model comprising process, machine and sequence constraints, and expresses scheduling as Markov decision; constructing a delivery time perception heterogeneous graph composed of process and machine nodes, and explicitly injecting semantics such as urgency degree, residual processing time, queue and predicted idle time in node and edge features by combining three relations of process sequence, process-machine feasibility and same-machine time sequence; tardiness perception graph attention network coding is adopted, a single actor-double commentator structure is matched, and a decision is made in a feasible action set through mask normalization and temperature sampling; the rewards and the event advance are aligned and calculated according to increments, and PPO + GAE is used for stable optimization in the training stage. The method is stable in performance in the aspects of reducing the total tardiness and controlling the maximum completion time, convergence is faster, good generalization is achieved, and the method is suitable for engineering deployment and online application.

The embodiment of the invention provides a TCP transmission implementation method and device, computing equipment and a storage medium. The transmission method comprises the steps that the duration of a TCP window switching timer is set as TCP end-to-end total delay; after the data sender sends the TCP packet, the data sender does not need to wait for an acknowledgement (ACK) of the data receiver to the sent TCP packet, and continues to send the TCP packet to be sent; when the duration that the data receiving party does not receive the TCP packet needing to be received reaches the duration of the TCP window switching timer, the data receiving party sends a NACK message to require retransmission of the TCP packet; and when the data sender receives the NACK message before the TCP window switching timer is overtime, the data sender sends the TCP packet required to be retransmitted by the NACK message. According to the TCP transmission technical scheme, TCP transmission is achieved on a deterministic network, the received TCP packet does not need to be confirmed through frequent ACK confirmation messages of a TCP layer, the influence of the frequent ACK confirmation messages on the network bandwidth and the CPU load is reduced, and the network transmission rate is increased.

The invention discloses a method and system for conducting self-adaptive sampling in SPI communication, and belongs to the field of digital communication.The method comprises the steps that an SPI host sends a reading command capable of reading parameters to an SPI slave, and when the last data bit of the reading command is sent, a starting identification signal is generated; a first MISO signal returned by the SPI slave is received, timing is started when the trigger edge of the start identification signal is detected based on the automatic detection module, timing is stopped when the first expected jump edge in the first MISO signal is detected, so that total delay time is obtained, and delay compensation time is calculated; and taking the original sampling edge delay compensation time of the SPI clock as an optimal sampling edge, and sampling a second MISO signal returned by the SPI slave when the optimal sampling edge is effective. According to the method, the received data sampling points can be automatically adjusted in different application scenes, the SPI communication rate and robustness are improved, the application range is wide, and portability is high.

The invention provides a low-delay high-definition panoramic multi-video stream fusion method and device and a medium, and belongs to the technical field of video transmission. The method comprises the following steps: collecting video data, extracting key frames through a semantic compression strategy, and maintaining a local data queue; constructing a transmission time delay model at an edge side, introducing a time delay deviation index to evaluate the transmission consistency of different video streams, constructing a decoding packet loss probability model, and establishing a relationship between a compression ratio and a packet loss probability; constructing an optimization problem aiming at minimizing the weighted sum of the total time delay and the time delay deviation, and combining the bandwidth resource constraint and the long-term packet loss rate constraint; the optimization problem is converted into a real-time optimization target; carrying out edge bandwidth resource allocation by adopting an SAC algorithm; and dynamically adjusting an end-side video compression ratio based on a bandwidth-oriented UCB algorithm, and dynamically selecting an adaptive scene according to an edge-side allocation bandwidth. According to the invention, the balance between low time delay and low packet loss is realized, and the stability and impression quality of panoramic multi-video stream fusion are improved.

A spatially unrolled time domain (TD) architecture that includes an input and weight register having i inputs and j weights, where i corresponds with a number of delay lines for i neurons, and j corresponds with a number of processing elements (PEs) for each delay line of the i delay lines. An enable control register sends a global input pulse to i neurons, and each delay line of the i delay lines includes the corresponding j PEs for that delay line. Each PE includes a digital-to-time converter (DTC) that accepts a digital input and weight and generates a relative delay, each time delay within a given delay line contributing to an overall delay for the given delay line. i time-to-digital converters (TDCs). A readout register receives digital outputs from each of the i TDCs, and serially outputs a signal from each of the i delay lines based on the overall time delay for each of the i delay lines.

The invention relates to a burr filtering circuit with equal rising edge and falling edge transmission delays, and belongs to the technical field of circuits. According to the burr filtering circuit, two stages of delay circuits are connected in series, and related parameters of the first-stage delay circuit and the second-stage delay circuit are the same, so that no matter whether an input signal is changed from low to high (rising edge) or from high to low (falling edge), the total delay is not changed and is equal to the sum of discharge time and charge time of RC circuits in the two stages of delay circuits. In addition, the original duty ratio of the input signal can be ensured while the burr signal is filtered out. In addition, the burr filtering circuit can also avoid output signal mistaken overturning caused by power supply voltage jump.

The application provides a data synchronization method and device for a master side and a slave side in a power supply system. The method comprises the following steps: when a master controller detects a trigger event, recording an event trigger time, generating a synchronization instruction package containing a total delay duration, and sending the synchronization instruction package to a slave controller; when the slave controller receives the synchronization instruction package, recording an instruction receiving time, analyzing and obtaining the total delay duration, calculating a synchronization time according to the difference between the instruction receiving time and the total delay duration, determining a target time interval according to the synchronization time and an effective data duration, and extracting slave side measurement data in the target time interval; wherein the synchronization time and the event trigger time are the same time. The method introduces total delay duration compensation, realizes data backtracking alignment, accurately eliminates the data communication delay of both sides, ensures the accurate alignment of the recorded data on the time axis of both sides, and is compatible with the existing system without relying on the addition of a hardware interface or physical circuit modification.

This application relates to devices and components, including apparatus, systems, and methods for performing a transition of a TCI state from a serving cell to a neighboring cell. The UE determines whether the state of the neighboring cell is known or unknown and whether the TCI state of the neighboring cell is known or unknown. The total delay time for performing the TCI state transition can be affected by the known / unknown state. Other factors can also contribute to the total delay time. The UE can also signal its capability to monitor the TCI state of the neighboring cell and its capability to transition to such a TCI state.

Embodiments of the present disclosure provide a method performed by a network node for transmission of data packets to a wireless device. The method comprises obtaining a packet delay budget, PDB, wherein the PDB represents a maximum allowable delay for a data packet. The method comprises determining a total delay time interval indicating a delay incurred for an estimated number of consecutive data packets transmitted from the network node to the wireless device. The method comprises transmitting the data packets to the wireless device based on if the determined total delay time interval exceeds the obtained PDB or not. Corresponding network node, and computer program products are also disclosed.

The invention discloses a matrix production workshop-oriented heterogeneous multi-load AGV scheduling method and system, and belongs to the technical field of automatic logistics scheduling. The core of the method is to construct a multi-objective optimization model which aims at minimizing task total delay time and the total number of path conflicts, and a multi-group evolution combined adaptive neighborhood search (MPE-ANS) algorithm is adopted for solving (the flow is shown in figure 1). According to the algorithm, a total population is divided into sub-populations, excellent individuals and common individuals are distinguished, and a targeted evolutionary strategy is designed: the excellent individuals realize local accurate optimization through three neighborhood structures, the common individuals expand a search space by virtue of crossover and mutation operators, and meanwhile, non-dominated solutions are dynamically stored through external archives. The method adapts to heterogeneous multi-load AGV operation characteristics, effectively balances global exploration and local optimization capabilities, remarkably reduces task delay and path conflicts, and is suitable for multi-AGV collaborative transportation in scenes such as intelligent factories and automatic warehouses.

This invention relates to the field of network security protocol technology, specifically to a method and system for encrypted transmission of network communication information, comprising the following steps: collecting transmission delay and queuing delay and summing them to generate a total delay; normalizing the error to form a delay redundancy mask; adjusting the encryption level and key length based on the judgment interval; constructing a topology mapping based on node processing capabilities and communication distance; allocating tasks and generating a node task table using the HEFT algorithm; generating a control factor using weighted averaging; optimizing the encryption level and task allocation; and improving transmission security and efficiency. In this invention, by collecting delay, extracting errors and normalizing them to generate a mask, dynamically adjusting the encryption level and key length to cope with fluctuations, optimizing task allocation based on node capabilities and communication distance, improving efficiency using the HEFT algorithm, and generating a control factor using weighted averaging to avoid over- or under-encryption, the invention enhances transmission security and efficiency.

The invention provides a phase delay circuit and a clock generator, the circuit comprises at least two delay modules, the delay modules are in cascade connection, the input end of the first delay module in cascade connection is connected with a to-be-delayed signal, the first output end is connected with the input end of the next-stage delay module, and the second output end is connected with the output end of the next-stage delay module; the second output ends of the delay modules are connected in parallel and then are respectively connected with the output end of the phase delay circuit and the first end of a preset common load resistor; the delay setting module is used for decoding the delay setting signal to obtain two paths of multi-bit-width control signals, and the first control end and the second control end of the last cascaded delay module are both grounded; the first control ends of the rest delay modules are respectively connected with the control bits in the first path of control signals, and the second control ends of the rest delay modules are respectively connected with the control bits in the second path of control signals; according to the circuit, the phase delay precision can be effectively improved, and the total delay amount, namely the sum of the delay amounts of the delay modules, can be conveniently adjusted and controlled.

The invention relates to the field of signal generation and delay, and discloses a ps-level high-precision low-jitter arbitrary waveform delay device and method.The device comprises a delay coarse adjustment module used for receiving input signals and providing first-level delay, and the delay coarse adjustment module comprises at least one digital delay chip; the delay fine adjustment module is coupled to the output end of the delay coarse adjustment module and used for providing second-level fine delay on the basis of the first-level delay, and the delay fine adjustment module comprises a plurality of switching devices and physical delay lines corresponding to the switching devices; the logic control module is respectively in communication connection with the delay coarse adjustment module and the delay fine adjustment module, and is used for receiving a delay control instruction and controlling the delay coarse adjustment module and the delay fine adjustment module to realize target total delay; according to the invention, the control mode is simple, and wide-range, high-precision and low-jitter arbitrary waveform delay can be realized.

The invention discloses a resource management and optimization method with limited total delay of data transmission based on triple sub-games. According to the invention, the resource sub-game is constructed for the upper limit value of the downlink total power of the base station; optimal power resources and data volume resources of each user in an original user set are obtained in a triple game sequential execution mode of constructing a resource sub-game for a preset global total data transmission time delay threshold value of a base station and constructing a resource sub-game for a transmission time delay idle value of a base station system so as to solve the problem how the base station passes through in a delay sensitive network. And the resource allocation means ensures that the total delay of data transmission of all users does not exceed a preset global threshold. Particularly, in each sub-game, the leader is a base station, and the follower of the game is a different user set. And a final resource allocation scheme can be obtained by sequentially solving the Stackelberg sub-game models.

The invention discloses a block unloading method and system for a super-resolution task in edge computing. The method comprises the following steps: S1, averagely dividing an image to be subjected to super-resolution processing into a plurality of blocks; s2, calculating the mPV value of each image block, and sorting all the image blocks in a descending order according to the result of the mPV values; s3, calculating to obtain a time relationship between each image block and the edge equipment; s4, on the basis of the sorting result obtained in the S2 and the time relation obtained in the S3, calculating the total delay of executing the super-resolution task by the edge device after each image block is unloaded to each edge device in sequence, selecting the edge device with the minimum total delay, and unloading the image block to the edge device; and S5, calculating the total delay of the image super-resolution task, wherein the total delay of the image super-resolution task is the longest delay for completing all the super-resolution tasks in all the edge devices obtained after the step S4. According to the method, the execution efficiency of the super-resolution task in the edge computing environment is effectively optimized.