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6results about How to "Improve Clock Synchronization Accuracy" patented technology

Linear topology slave node synchronization method and system based on IEEE 1588 precision clock protocol

ActiveCN116232513BImprove Clock Synchronization Accuracyreduce synchronization errorTime-division multiplexTransmissionComputer networkSlave clock
The application discloses a linear topology slave node synchronization method and system based on IEEE 1588 precision clock protocol, and the method comprises the following steps: step one, slave node 1 to slave node n-1 accepts PTP messages from a master node and forwards the PTP messages to the next level; step two, slave node 1 to slave node n-1 accepts PTP messages from slave node n and forwards the PTP messages to the previous level; step three, slave node 1 to slave node n takes an average value of round trip time to obtain an average link delay; step four, the master-slave clock offset is calculated according to the average transmission delay; and step five, dynamic frequency compensation calculation is performed. The application can increase the synchronization accuracy of the system and effectively reduce the clock deviation between nodes in the distributed system of the linear topology structure.
Owner:ZHEJIANG SCI-TECH UNIV

A clock synchronization method, device, mobile terminal and storage medium

The present invention discloses a clock synchronization method, device, mobile terminal and storage medium, the method comprising: obtaining a clock synchronization beacon; calculating a first clock synchronization error according to the clock synchronization beacon; wherein the first clock synchronization error is an error generated when performing the nth clock synchronization, and n is a positive integer; according to the first clock synchronization error and the synchronization period adaptive adjustment parameter, in combination with a first formula, calculating a first clock synchronization period; wherein the first clock synchronization period is a period when performing the n+1th clock synchronization; performing the n+1th clock synchronization according to the first clock synchronization period. The embodiment of the present invention can realize the adaptive adjustment of the clock synchronization period according to the clock synchronization error, thereby improving the accuracy of clock synchronization.
Owner:GUANGDONG POWER GRID CO LTD +1

A clock synchronization method between multiple EtherCAT network segments

ActiveCN118659853BImprove Clock Synchronization AccuracyTime-division multiplex
The present invention discloses a method for clock synchronization between multiple EtherCAT network segments, including: Step 1, synchronize the clocks of multiple slave stations within each of the multiple EtherCAT network segments; Step 2, the MCU generates a pulse signal LATCH; Step 3, when ESC1 and ESC5 detect the rising edge of the LATCH signal, latch the local system time, which are T1 and T5 respectively; Step 4, the MCU reads the time T1 of the rising edge of the LATCH latched by ESC1 and writes T1 into ESC5; Step 5, ESC5 compares T5 and T1, if T5 > T1, slow down the local time; if T5 < T1, speed up the local time; Step 6, the MCU periodically generates the LATCH signal, reads T1 and writes T1 into ESC5; Step 7, ESC5 periodically adjusts the local system time to achieve clock synchronization with ESC1, realizing clock synchronization of multiple network segments. Timestamp latching and time adjustment are both implemented by ESC, and the MCU software only responsible for data transmission and does not participate in clock adjustment, so clock errors will not be introduced.
Owner:WUXI CORE FIELD MICROELECTRONICS CO LTD

Clock synchronization method, device, equipment and readable storage medium

ActiveCN115296766BImprove Clock Synchronization AccuracyTime-division multiplexComputer hardwareOperational system
The present invention provides a clock synchronization method, device, equipment and readable storage medium. The method includes: starting an operating system, reading a 1588 network card driver and a compensation value file corresponding to the operating system, wherein the compensation value file records clock synchronization compensation values ​​corresponding to different system loads; replacing the network card driver of the operating system with the 1588 network card driver; obtaining the actual system load, and determining the actual clock synchronization compensation value corresponding to the actual system load according to the compensation value file, and performing clock synchronization with the actual clock synchronization compensation value. Through the present invention, the corresponding clock synchronization compensation value can be selected according to the actual system load for clock synchronization, thereby improving the accuracy of clock synchronization.
Owner:FIBERHOME SUPERMICRO INFORMATION TECH CO LTD +1

Implementation method of clock synchronization of master-slave system based on EtherCAT

ActiveCN117411579BImprove Clock Synchronization AccuracyClock driftClock offset
The application discloses an implementation method of clock synchronization of master-slave system based on EtherCAT. The basic idea of the method is to compensate the clock deviation between the master station and each slave station from three aspects of initial clock offset, transmission delay and clock drift. Compared with the traditional clock synchronization algorithm, the clock synchronization algorithm has the advantages that the transmission delay between the master station and the reference slave station is measured, and the initial clock offset of each slave station is compensated by using the transmission delay. The application has the beneficial effect that the clock synchronization precision between the master station and the slave station is improved while ensuring the nanosecond-level clock synchronization precision between the slave stations.
Owner:TIANJIN POLYTECHNIC UNIV +1