54 results about "DC block" patented technology

Circuits and methods for providing ESD protection, particularly for LNAs lacking a DC blocking input capacitor (“capless LNAs”). Novel circuitry provides both improved ESD protection and an improved Noise Figure compared to conventional designs. One embodiment includes an integrated circuit including a voltage source pin and a plurality of low-noise amplifiers lacking a respective DC blocking input capacitor, each of the plurality of low-noise amplifiers including: a voltage source terminal coupled to the voltage source pin, an input terminal configured to receive a signal to be amplified, an output terminal configured to output an amplified version of the received signal to be amplified, an ESD protection circuit coupled to the input terminal and to both the voltage source terminal and a reference potential, and a distributed ESD clamp coupled between the reference potential and a node located between the ESD protection circuit and the voltage source terminal.

The utility model discloses a low-internal resistance direct current detection circuit and electronic equipment. The circuit comprises a sampling resistor unit, an analog single-pole double-throw switch, a first blocking capacitor, a first voltage amplification unit, a second blocking capacitor, a frequency mixing unit, a second voltage amplification unit, a third blocking capacitor and a control unit. The sampling resistor unit is arranged in a direct current loop to be measured; the analog single-pole double-throw switch is used for converting direct-current voltage at two ends of the sampling resistor into a high-frequency alternating signal; the first voltage amplification unit amplifies the signal and then outputs the signal to the frequency mixing unit through the second blocking capacitor; the mixing unit outputs a low-frequency mixing signal under the action of the mixing control signal; the second voltage amplification unit differentially amplifies the frequency mixing signal and then outputs a third output voltage signal through a third blocking capacitor, and the third output voltage signal is used for determining the magnitude of loop current and controlling gear switching. The circuit is simple in structure, low in cost and suitable for large-range direct current on-line continuous detection.

The present invention discloses a single-core cable communication circuit between well logging instruments, a well logging instrument, and a well logging system. The single-core cable communication circuit between well logging instruments includes: a single-core cable interface, a sampling inductor, a DC blocking capacitor, a transmitting drive circuit, a receiving signal conditioning circuit, and a power supply module. The receiving signal conditioning circuit includes: a receiving end digital interface, and the transmitting drive circuit includes: a first transmitting end digital interface and a second transmitting end digital interface. The single-core cable interface is respectively connected to the first end of the DC blocking capacitor and the first end of the sampling inductor. The second end of the DC blocking capacitor is respectively connected to the receiving signal conditioning circuit and the transmitting drive circuit. The second end of the sampling inductor is connected to the power supply module. This circuit can supply DC power to the well logging instrument through the single-core cable while realizing half-duplex communication between the well logging instruments. It has the characteristics of simple circuit structure and easy implementation.

The utility model discloses a full-bridge converter module without a blocking capacitor. The full-bridge converter module comprises an input filtering unit, a first inversion bridge arm, a second inversion bridge arm, a planar transformer T, a first rectification bridge arm, a second rectification bridge arm, a planar inductor Lf, an output capacitor Co and a square wave detection unit M, the output capacitor Co is connected between the output positive end and the output negative end; a load Rload is connected between the output positive end and the output negative end; according to the full-bridge converter module, a planar magnetic technology is adopted, blocking capacitor configuration is avoided, positive and negative volt-second products are calculated through square wave voltage sampled by a resistance voltage division circuit and driving edge time captured by a comparator circuit, duty ratio control quantity is output, primary side full-bridge driving signal pulse width is dynamically adjusted, and magnetic flux balance control is achieved; the problem that the blocking capacitor occupies a large area is solved, and the high-power density design of the brick power supply module can be realized.

The utility model discloses a characteristic current transmitting circuit for a transformer area topology identification device, which relates to the technical field of intelligent low-voltage power distribution and comprises a rectifying circuit used for converting alternating-current mains supply into high-voltage direct current and serially connecting a fuse to realize over-current protection; the direct-current voltage stabilizing circuit is connected with the output end of the rectifying circuit, consists of a voltage stabilizing tube, an MOS (Metal Oxide Semiconductor) tube and a resistor-capacitor element, and is used for outputting stable low-voltage direct-current voltage, and the static power consumption is microampere level; the characteristic current signal transmitting circuit comprises a blocking capacitor, a push-pull output triode and an optocoupler, and is used for receiving an external PWM signal and coupling the external PWM signal to the optocoupler through the blocking capacitor so as to generate a driving signal; and the constant current transmitting circuit is connected with the output end of the characteristic current signal transmitting circuit and comprises an MOS (Metal Oxide Semiconductor) tube and a negative feedback resistor, and the gate-source voltage is adjusted through the negative feedback resistor to realize constant current output. The circuit is low in static power consumption, stable in constant current output, strong in anti-interference performance, and simple in structure.

The application discloses a multi-mode power amplifier circuit for electronic warfare and a dual-band communication system and belongs to the technical field of microwave integrated circuits. pn The application introduces a plurality of reconfigurable branches with the same structure in the circuit structure, each of which comprises a capacitor C sn , an inductor L pn , a DC blocking capacitor C sn and a switching transistor Q sn , the capacitor C pn and the inductor L pn are connected in parallel to form a band-pass network, one end of the band-pass network is connected with the drain of the switching transistor Q sn through the DC blocking capacitor C sn , the source of the switching transistor Q sn is grounded, the gates of the switching transistor Q sn in the first, second and third reconfigurable branches are connected and are all connected to a DC control power supply V gc . The switching of the ultra-wideband and the communication band can be realized by changing the control voltage of the switching transistor in the reconfigurable branch and the drain power supply circuit of the pre-stage electric amplification path, and the multi-mode operation of the high-performance power amplifier in the ultra-wideband and the dual communication band is realized.

Various embodiments herein relate to apparatuses and methods for wafer state detection. In some embodiments, an apparatus for wafer state detection is provided, the apparatus comprising: an RF blocking filter; a DC blocking filter; and a controller coupled to a plurality of electrodes associated with an electrostatic chuck (ESC) via the RF blocking filter and the DC blocking filter, wherein the controller is configured to: cause an input signal to be injected in an input side of a circuit associated with the plurality of electrodes, the RF blocking filter, and the DC blocking filter, wherein the input side corresponds to a first electrode; measure characteristics of an output signal at an output side of the circuit, wherein the output side corresponds to a second electrode; and calculate wafer state characteristics of a wafer positioned on a surface of a platen based on the characteristics of the output signal.

This invention discloses a system and method for achieving atomic layer etching (ALE) and radical-enhanced deposition (REED) in a single chamber. The system features a switchable DC blocking capacitor for grounding an electrostatic chuck (ESC) to eliminate the plasma sheath, and employs high-power short-pulse RF to suppress ion bombardment during ALE surface modification and REED deposition steps, thereby achieving efficient processing and making it suitable for applications such as the fabrication of high aspect ratio structures.

The invention provides a bypass system of a capacitor bank in an eddy current self-driving type direct current magnetic bias suppression device, and relates to the technical field of direct current magnetic bias governance. The system comprises an eddy current self-driving switch and a blocking capacitor, one end of a self-driving coil of the eddy current self-driving switch is connected with a neutral point of a transformer; the other end of the self-driven coil of the eddy current self-driven switch is connected with one end of the blocking capacitor, and the other end of the blocking capacitor is grounded; and moving and static contacts of the eddy current self-driven switch are connected in parallel to two ends of the blocking capacitor. The influence of earth surface potential on the neutral point of the transformer can be effectively reduced through the blocking capacitor, in addition, in the process of a single-phase short-circuit fault, the self-driving coil pushes the eddy current self-driving switch to be switched on, the neutral point of the transformer is metallically grounded after passing through the self-driving coil of the eddy current self-driving switch after switching on, the blocking capacitor is short-circuited, and the fault of the single-phase short-circuit fault is eliminated. And the current flowing through the blocking capacitor is reduced, so that the possibility that the blocking capacitor is damaged due to a single-phase short-circuit fault is reduced.

The invention discloses a reflective broadband energy amplification surface with polarization selectivity. The reflective broadband energy amplification surface comprises a plurality of energy amplification surface units which are periodically distributed, and each energy amplification surface unit comprises a first metal surface, a second metal surface, a third metal surface, a fourth metal surface and a fifth metal surface which are separated by dielectric substrates. The third metal surface adopts two rectangular metal patches which are distributed in an L shape; the fifth metal surface comprises a C-shaped microstrip transmission line, a feed microstrip line and a rectangular metal patch; an amplifier and two blocking capacitors are connected in series on the middle section of the C-shaped microstrip transmission line, and two arms are respectively connected with the two rectangular metal patches through via holes. The feed microstrip line is connected in series with an inductor and a resistor, and the amplifier, the resistor, the blocking capacitor and the inductor form a radio frequency amplification and bias filter circuit. According to the invention, by introducing an active amplification circuit and a polarization coupling mechanism, energy amplification and polarization regulation and control of in-band incident waves are realized.

Circuits and methods for providing ESD protection, particularly for LNAs lacking a DC blocking input capacitor ("capless LNAs"). Novel circuitry provides both improved ESD protection and an improved Noise Figure compared to conventional designs. One embodiment includes an integrated circuit including a voltage source pin and a plurality of low-noise amplifiers lacking a respective DC blocking input capacitor, each of the plurality of low-noise amplifiers including: a voltage source terminal coupled to the voltage source pin, an input terminal configured to receive a signal to be amplified, an output terminal configured to output an amplified version of the received signal to be amplified, an ESD protection circuit coupled to the input terminal and to both the voltage source terminal and a reference potential, and a distributed ESD clamp coupled between the reference potential and a node located between the ESD protection circuit and the voltage source terminal.

The application provides a charger power module, comprising a substrate assembly, a frame assembly, a support capacitor assembly and a DC blocking capacitor assembly, the support capacitor assembly is located at the bottom of the frame assembly, the frame assembly and the support capacitor assembly enclose a frame structure, the frame structure is fixed on one side of the substrate assembly, the frame structure and the substrate assembly enclose a receiving cavity, the DC blocking capacitor assembly is located at the upper part of the receiving cavity and is electrically connected with the frame assembly and the substrate assembly respectively, the substrate assembly comprises a radiator substrate, a magnetic element and a power device electrically connected with the magnetic element, the frame structure is connected with the radiator substrate to enclose the receiving cavity, and the magnetic element and the power device are respectively integrated on the side of the radiator substrate facing the receiving cavity. The charger power module provided by the application has the advantages of compact structure, reasonable layout and high integration degree, and can better realize the miniaturization, light weight and simple design of the charger.

A configuration is provided in which two high-frequency power transmission antennas 111, 121 formed on two microstrip lines 101, 102, respectively, are disposed to face each other with an insulating sheet 103 interposed between the two high-frequency power, and the high-frequency power transmission antennas 111, 121 are formed on the two microstrip lines 101, 102, respectively, to realize transmission of high-frequency power, to make it possible to reduce the size of a DC block as compared with a conventional DC block using a coaxial line shape or a waveguide shape, and make it possible to highly efficiently transmit only high-frequency power while cutting off high-voltage direct-current power by the insulating sheet 103.

A device may include a transistor die including a transistor and a transistor input terminal and a transistor output terminal, and an output circuit coupled between the amplifier output and the transistor output terminal, wherein the output circuit includes: a DC blocking capacitor, a first inductance electrically connected between the transistor output terminal and a first terminal of the DC blocking capacitor, and a series-connected second inductance and a first capacitor connected, in parallel with the first inductance, between the transistor output terminal the first terminal of the DC blocking capacitor, wherein a second terminal of the DC blocking capacitor is connected to a ground node and wherein the first inductance and the series-connected second inductance and the first capacitor form at least a portion of a pseudo tank circuit in which the first inductance is configured to resonate with the first capacitor.

A display device is disclosed. The display device includes a power supply and a display. The power supply includes: a first line filter connected to an external alternating current (AC) power source and including a first common mode choke and a first capacitor connected in parallel to the first common mode choke; a second line filter connected to the first line filter and including a second common mode choke and a second capacitor connected in parallel to the second common mode choke; a third capacitor having one end connected to a neutral of the first capacitor and the other end connected to a frame ground; an AC / DC block connected to the second line filter; a fourth capacitor having one end connected to a neutral of the second capacitor and the other end connected to the frame ground; and a DC / DC block connected to the AC / DC block and configured to provide driving power to the display connected to the power supply.

This invention relates to the field of radio frequency integrated circuit technology, specifically disclosing a high-gain, adjustable-gain low-noise amplifier, including a DC blocking capacitor circuit, a first-stage amplifier circuit, and a second-stage amplifier circuit. The second-stage amplifier circuit includes an amplifying transistor and a gain control unit. The DC blocking capacitor circuit is connected to the input terminal of the second-stage amplifier circuit through the first-stage amplifier circuit, and the gain control unit is connected between the input and output terminals of the amplifying transistor. The DC blocking capacitor circuit is used to input a radio frequency signal. The first-stage amplifier circuit amplifies the radio frequency signal to output a pre-amplified radio frequency signal. The second-stage amplifier circuit amplifies the pre-amplified radio frequency signal to output a further amplified radio frequency signal. The gain control unit is used to adjust the closed-loop gain of the second-stage amplifier circuit. This invention can provide adjustable high gain and can achieve balun-free single-ended input to dual-ended output conversion, saving circuit area and power consumption.

A distributed amplifier system comprising an impedance matching network configured to match an input impedance to an output impedance of the signal source, and a DC block configured to block DC components in the input signal. A variable gain amplifier adjusts the gain applied to the input signal based on a gain control signal to generate a gain adjusted signal. An emitter follower circuit receives and processes the gain adjusted signal to introduce gain peaking to create a modified signal. A distributed amplifier receives and amplifies the modified signal from the emitter follower circuit, to create an amplified signal. The distributed amplifier includes a termination network and one or more impedance matching elements configured for gain shaping the amplified signal. The gain peaking introduced by the emitter follower circuit is controlled by a variable current source. The distributed amplifier may be an open collector distributed amplifier.

An audio amplifier chip includes an audio amplifier, a current providing circuit, a detection circuit, and a control circuit. The audio amplifier is arranged to drive a speaker, wherein the audio amplifier has multiple differential input terminals, and a direct current (DC) blocking capacitor is coupled to one of the multiple differential input terminals. The current providing circuit is arranged to provide at least one current for charging the DC blocking capacitor. The detection circuit is coupled to a node located between the one of the multiple differential input terminals and the DC blocking capacitor, and is arranged to detect whether an external resistor of the audio amplifier chip exists according to an input voltage from the node, in order to generate a detection result. The control circuit is arranged to determine a start-up time of the audio amplifier according to the detection result.

This application discloses a high-frequency reliability testing circuit and a semiconductor reliability testing device. The high-frequency reliability testing circuit includes: a signal input terminal for receiving a high-frequency sinusoidal signal; a DC blocking capacitor, one end of which is coupled to the signal input terminal; a self-biased inverter unit, its input terminal coupled to the other end of the DC blocking capacitor, for converting the high-frequency sinusoidal signal into a quasi-square wave signal; a buffer unit, its input terminal coupled to the output terminal of the self-biased inverter unit, for shaping and amplifying the quasi-square wave signal to generate a shaped square wave signal; and a signal output terminal coupled to the output terminal of the buffer unit for outputting the shaped square wave signal. The signal output terminal is coupled to the device under test (DUT) to apply the shaped square wave signal as AC electrical stress to the DUT. This application solves the problem of high-frequency test signals being limited by external bandwidth in the prior art, enabling accurate assessment of the reliability and lifetime of devices in high-frequency application scenarios.

The invention discloses a high-performance dual-mode frequency multiplier circuit. The frequency multiplier can be applied to a millimeter wave band, and outputs frequency doubling and frequency tripling signals at the same time. The circuit comprises an input balun, an improved push-push frequency doubler, a frequency tripler based on a single balanced mixer, and an output balun. The input Balun converts an input single-ended fundamental wave signal into a differential signal; the improved push-push frequency doubler comprises a main body push-push frequency doubler formed by field-effect tubes M1 / M2 and a gain-enhanced cross coupling pair formed by field-effect tubes M3 / M4, and is used for completing secondary frequency doubling of a fundamental wave signal, wherein the main body push-push frequency doubler is formed by the field-effect tubes M1 / M2, and the gain-enhanced cross coupling pair is formed by the field-effect tubes M3 / M4. The frequency tripler based on the single balanced mixer completes self-mixing frequency tripling of a fundamental wave signal through output matching inductors L1 and L2 and blocking capacitors C5 and C6; and the output Balun finishes subtraction operation of the two paths of signals and then retains a triple frequency signal. The scheme of the invention has the characteristics of dual-mode frequency multiplication ratio, high gain and simple structure.

The invention discloses a novel DC block, which belongs to the technical field of microwave capacitor assembly, is of a coaxial structure, and comprises a DC block inner conductor, a DC block outer conductor and an insulating support, the DC block inner conductor comprises a first inner conductor, a second inner conductor and a third inner conductor, the DC block outer conductor comprises a first outer conductor, a second outer conductor, a third outer conductor and a fourth outer conductor, the two first inner conductors are respectively arranged in the second inner conductor and the third inner conductor, and the second inner conductor, the third inner conductor and the insulating support are arranged in the first outer conductor through interference fit; the microwave capacitor is assembled between the two first inner conductors, the side wall of the first outer conductor is provided with an opening, the position of the microwave capacitor corresponds to the position of the opening, and the second outer conductor is arranged in the opening of the first outer conductor. According to the novel DC block, multiple conversion links of'coaxial-microstrip-capacitance-microstrip-coaxial 'are canceled, so that signal reflection and energy loss caused by mode conversion and discontinuous impedance are reduced.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion / mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

The invention discloses a fan pitch adjustment compensation damping control system and method for ultralow frequency oscillation suppression, and the system comprises a wind turbine generator primary frequency modulation control module and an additional damping controller, and the additional damping controller is connected with the wind turbine generator primary frequency modulation control module in parallel and then is connected into a pitch angle compensation control system; the additional damping controller comprises a power grid frequency monitoring and low-pass filtering module, an additional damping controller gain adjusting module, an isolation direct current module and a frequency control signal phase compensation module which are sequentially connected in series. The additional damping controller is connected to the primary frequency modulation position of the draught fan in parallel to suppress the ultralow frequency oscillation behavior of the water-wind combined system, the power output active power is changed through dynamic paddle adjustment, and therefore power oscillation of the ultralow frequency band is suppressed.

When the signal level of a signal outputted from a predetermined amplifier among the at least one amplifier is greater than or equal to a reference voltage, the comparator unit outputs, from its output terminal, an output signal which is in line with the difference between the signal level and the reference voltage. The DC blocking unit is electrically connected, at its first terminal, to the output terminal of the comparator unit, and outputs, from its second terminal, a signal obtained by blocking the DC component of the output signal. The detection unit is electrically connected, at its input terminal, to the second terminal of the DC blocking unit, and outputs, from its output terminal, a control signal, which is in line with the signal level of the signal outputted from the predetermined amplifier, to a predetermined circuit capable of reducing the gain of the power amplifier circuit.

This invention discloses an on-chip compact dual-core dual-path quality factor enhancement source degradation fully differential low-noise amplifier, comprising four MOS transistors, gate-source capacitors, DC blocking capacitors, bias resistors, and inductors. Four source half-turn inductors form a first transformer, and two gate-end inductors coupled together form a second transformer, which is nested within the first transformer. The first and second transformers constitute a multiplexed four-turn coupled transformer, simultaneously achieving source degradation imaginary and real part matching within the same transformer area. In differential operation, the currents in both signal paths enhance the magnetic flux, improving the effective inductance and quality factor of the inductors. This achieves on-chip integration of gate-end inductors in the Sub-6GHz band, optimizing noise, gain, and area efficiency.

The invention provides a broadband high-voltage DC block design method suitable for power electronic equipment and a DC block. The design method is characterized by comprising the following steps: step 1, designing a coaxial transmission line structure suitable for a high-voltage environment according to the relation between the characteristic impedance of a coaxial cable and the radiuses of inner and outer conductors and considering the breakdown voltage of a medium between the conductors; 2, according to the measurement frequency range of the power electronic equipment, the withstand voltage and the capacitance value of a blocking capacitor are designed, so that the S parameter of the blocking capacitor meets the performance requirement; and step 3, designing an interface adapter according to requirements. The DC block designed by the invention can greatly attenuate low-frequency high-voltage large-current components in the power electronic equipment, and meanwhile, ensures that a measurement signal is loaded on the tested equipment without distortion, so that the DC block is suitable for a power electronic equipment test environment. According to the invention, the requirements on the dielectric material and the processing precision of the DC block are low, the design method has certain universality, the device is simple in structure, and the manufacturing method is easy to implement.

This invention proposes a single-pole double-throw (SPD) high-power switch chip with a positive input voltage, comprising transistors M1-M18, DC blocking capacitors C1-C5, bonding inductors L1-L3, microstrip lines TL1-TL5, and bias resistors R1-R3. By adding two bias resistors at the input, this invention transforms the original negative input SPD double-throw switch into one that only requires a positive input voltage, simplifying the circuit implementation. Furthermore, by stacking multiple series-parallel switching transistors on the basis of traditional series-parallel switches, this invention achieves high-power input. Simultaneously, the multiple parallel transistors ensure good isolation and isolation bandwidth over a wide frequency range, and the microstrip line matching results in excellent switch insertion loss and other performance characteristics.

A power transfer device according to one embodiment of the present invention comprises: an impedance matching network for transferring RF power of an RF generator to a load; a band elimination filter which transfers the DC pulse voltage of the DC pulse generator to a load and suppresses transfer of the RF power to the DC pulse generator; the DC blocking capacitor is connected to the output end of the impedance matching network and used for inhibiting the DC pulse voltage passing through the output end of the band elimination filter from being transmitted to the impedance matching network; and an impedance converter connected to the output end of the band elimination filter and changing the impedance of the RF power incident to the band elimination filter. The output end of the impedance converter and the output end of the DC blocking capacitor are connected with each other and then are connected to the load through a transmission line.

The present invention discloses a multi-DC coordinated control method and system based on VSC-HVDC and LCC-HVDC. Under the condition that the non-blocked DC line meets the large signal stability, when the LCC-HVDC blocking is detected, the emergency power support amount P required by the receiving system is determined. short If the required emergency power support amount P short Less than the maximum power support of VSC-HVDC P VSC_th , then VSC-HVDC will give priority to active power support; if the required emergency power support amount P short Greater than the VSC-HVDC maximum power support P VSC_th , but less than the sum of the maximum power support of VSC-HVDC and LCC-HVDC P VSC_th +P LCC_th , the non-blocking DC line VSC-HVDC and LCC-HVDC need to coordinate active power support, and the VSC-HVDC also provides reactive power support. If the maximum power support of the VSC-HVDC and LCC-HVDC still cannot ensure system stability, additional generator or load shedding measures are necessary. This invention can improve the frequency stability of the receiving power grid after DC blocking occurs in the LCC-HVDC.