34results about How to "Increased output voltage swing" patented technology

Adaptive rail power amplifier technology processes an audio signal by feeding the audio signal to the power amplifier to produce an output signal, applying positive and negative power supply voltages centered with respect to the audio signal to the positive and negative power supply rails of the power amplifier, comparing the output signal with the positive and negative power supply rail voltages to produce dynamically varying positive and negative control signals, feeding the positive and negative control signals to positive and negative high current charge pumps and adding supplemental positive and negative voltages from the positive and negative charge pumps to the positive and negative power supply rails to produce a linear adaptive rail voltage which tracks the output signal.

A ring oscillator stage includes two differential transistor pairs configured to add an adjustable amount of delay to a differential input signal. Each differential pair is biased with a bias current transistor; the bias current transistor is “protected” by a voltage-clamping transistor that limits the drain voltage of the bias current transistor. The voltage-clamping transistors enable use of a power supply voltage (V_DD) that would otherwise exceed the reliability breakdown voltage limit of the bias current transistors.

For use in professional audio amplifier applications, high current charge pump circuits including charge circuits and dynamic release circuits are connected between respective storage capacitors and the audio power amplifier output. The charge circuits charge their storage capacitors when an output signal swing of the power amplifier is below a corresponding predetermined positive and negative threshold. The dynamic release circuits release power from their charged storage capacitors to dynamically vary the voltage levels of their positive and negative power supply rails in direct relation to the output signal swing of the power amplifier, preferably at unity gain. Multiple positive and negative power supply rails at different voltage levels can be used with cascaded multi-stage dynamic release circuits to maximize system efficiency. The charge and dynamic release circuits can be connected between their storage capacitors and a buffer amplifier which also receives the power amplifier audio input.

A current mirror includes a serially connected diode-connected transistor of a first conductivity type, a saturated (fully-on) transistor of a second conductivity type, and a current source for providing a reference current. A gate voltage generated by the diode-connected transistor in response to the reference current is provided to the gate of a matching transistor. This causes the matching transistor to mirror the reference current. Meanwhile, an output transistor cascoded with the matching transistor is gate-coupled to the junction between the saturated transistor and the current source. This allows the output transistor to provide an output voltage swing from one supply voltage to two saturation voltage drops from the second supply voltage. Meanwhile, the cascode configuration gives the current mirror a high output impedance.

The invention discloses a multi-octave ultra-broadband amplifier circuit, which comprises a cascode structure stacked by three transistors, an active-passive hybrid bias circuit and a power supply VDD, wherein the three transistors in the cascode structure are a transistor M1, a transistor M2 and a transistor M3 respectively, wherein the grids of the transistor M1, the transistor M2 and the transistor M3 and the active-passive hybrid bias circuit are all connected to the power supply VDD; the source of the transistor M1 is connected to the ground; the grid of the transistor M2 is connected tothe ground through a capacitor C2; and the grid of the transistor M3 is connected to the ground through a capacitor C3. The source of the transistor M2 is connected to the drain of the transistor M1,the drain of the transistor M2 is connected to the source of the transistor M3, and the drain of the transistor M3 is connected to the active-passive hybrid bias circuit. According to the multi-octaveultra-broadband amplifier circuit, the working frequency covers megahertz (MHz) to gigahertz (GHz), the bandwidth is equivalent to a distributed amplifier, and the unit circuit gain performance, thepower consumption and the chip area are better than a distributed structure.

The invention discloses a wide-band active feedback transimpedance amplifier for low voltage operation. The amplifier is composed of a common-grid main amplifier composed of a resistor R1, a resistorRs and a MOS transistor M1, and a common-source active feedback circuit composed of a MOS transistor M2. A bias voltage is added to the gate of the MOS transistor M1 of the transimpedance amplifier, thereby replacing the gate bias of the common gate input transistor of the regulating cascode structure and reducing the voltage redundancy consumption; The transimpedance amplifier uses a common-gateinput terminal with common-source active feedback to achieve an input impedance similar to that of a regulated cascode structure, thereby isolating the effect of input parasitic capacitance on the bandwidth. A capacitive degradation circuitry is added to the transimpedance amplifier to produce zero points that cancel poles, extending bandwidth while increasing the gain of the voltage. The invention can realize the monolithic integration of the analog front end and the digital signal processing back end of the optical receiver with high performance on the same chip, reduce the cost and enhancethe function.

The invention discloses an ultra-low voltage cold start oscillator delay unit based on a deep trap MOS tube. The delay unit comprises PMOS (P-channel Metal Oxide Semiconductor) tubes M1, M3 and M5 andNMOS (N-channel Metal Oxide Semiconductor) tubes M2, M4 and M6, which are manufactured by adopting a deep trap process, wherein substrates of the M1 and M2, substrates of the M3 and M4 and substratesof the M5 and M6 are respectively connected, and a signal input end Vin of the delay unit is connected to the substrates of the PMOS tubes and the NMOS tubes; the gate electrodes of M1 and M2, the gate electrodes of M3 and M4 and the gate electrodes of M5 and M6 are respectively connected and then connected to a signal input end Vin of the delay unit, a drain electrode of M1 is connected with a drain electrode of M2 and serves as a common drain electrode X port, a source electrode of M1 is connected with a power supply, and a source electrode of M2 is grounded. Under the condition of ensuringlow input power supply voltage, the output voltage swing of the delay unit is improved, the direct-current gain of the delay unit is increased, and oscillation can be generated under lower power supply voltage.

The invention relates to an SET/CMOS latch based on negative differential resistance characteristics. The SET/CMOS latch based on the negative differential resistance characteristics comprises a double-grid single electron transistor, a PMOS tube and an NMOS tube. The SET/CMOS latch based on the negative differential resistance characteristics is characterized in that the source electrode of the PMOS tube is connected with a power source voltage Vdd, the grid electrode of the PMOS tube is used as the input end of the latch, the drain electrode of the PMOS tube is used as the output end of the latch and connected with the drain electrode of the NMOS tube and one grid electrode of the double-grid single electron transistor, the other grid electrode of the double-grid single electron transistor is connected with a control voltage Vctrl, and the source electrode of the double-grid single electron transistor is connected with the ground. Compared with a traditional CMOS latch, the latch has the advantages of being low in power consumption, simple in circuit structure, high in integration degree and the like. Compared with a single electronic latch, the latch is quite high in working voltage and large in output voltage swing, and reduces transmission delay of a circuit.

The invention discloses a unipolar differential logic static random access memory unit and a random access memory, the random access memory unit comprises a unipolar differential logic phase inverter, the unipolar differential logic phase inverter comprises a main circuit and an auxiliary pull-up path, and cross-coupled pull-down tubes are adopted in the main circuit to form a positive feedback structure so as to reduce static power consumption; a gate control module which comprises a write switch and a read switch, and when the write switch is switched on, the unipolar differential logic static random access memory unit writes and stores data; and when the read switch is switched on, data stored in the unipolar differential logic static random access memory unit is read. The pull-down tube of the unipolar differential logic static random access memory unit adopts a cross coupling connection mode to form a positive feedback structure, so that a closed TFT (Thin Film Transistor) always exists from a power supply to the ground in a stable state, a static direct-current path is eliminated, static power consumption is reduced, and output voltage swing is improved. The invention can be widely applied to static random access memories.