479results about "Single-ended push-pull amplifiers" patented technology

An object of the present invention is to allow the miniaturization of a mobile communication equipment and the reduction of consumption power, and to improve the electrical characteristics of a final stage amplifier. An inputted RF signal is amplified to a specified transmission output by a final stage amplifier, the output power and a reflected wave generated by mismatching between an output impedance of the final stage amplifier and a load impedance connected to an output side of the final stage amplifier are detected by a directional coupler. Two switches are selectively switched in a time division manner, a DC voltage corresponding to the reflected wave is selected, a comparator compares a threshold voltage with the DC voltage, a switch is switched by an output of the comparator outputted in accordance with the comparison, and gate voltages are selectively applied to the final stage amplifier.

The invention relates to a power amplifier module comprising a first amplifier 2 having a first front-end 4 and a first backend amplifier stage 5 and a second amplifier 3 having a second front-end 6 and a second backend amplifier stage 7, the first amplifier and the second amplifier being arranged in a Bridge Tied Load (BTL) configuration with feedback over the load,characterized in thatthe first and the second backend amplifier stages having point symmetrical transfer functions with respect to the origin,the input current i1 of the first backend amplifier stage being substantially equal to the input current i2 of the second backend amplifier stage.

A three stage amplifier is disclosed provided with a novel frequency compensation technique. Only a single feedback loop with a single compensation capacitance is provided. Instead of a conventional nested compensation technique, damping factor control is provided by means of a fourth gain stage in order to stabilize the amplifier. The resulting amplifier is particularly useful to drive large capacitive loads for low-voltage low-power applications.

A monolithic integrated circuit amplifier has a gain stage and a buffer stage. The buffer stage includes an output stage and two separate voltage supplies, the second of which has a greater magnitude than the first. Switching circuitry is included that is connected to the output stage via a regulator bus. When an output demand voltage is less than a switch-over threshold, current to the output stage is provided substantially from the first voltage supply; when the output demand voltage is greater than the switch-over threshold, current to the output stage is provided substantially from the second voltage supply. Collector voltage at the output stage is dynamically controlled to be greater than the emitter voltage by a difference voltage that increases proportionally as output voltage increases above the switch-over threshold. This difference voltage is commonly referred to as "headroom." The dynamic headroom control circuitry preferably includes means for predictably setting and controlling the headroom voltage at switch-over and smoothly increasing the headroom voltage up to maximum output voltage.

An automatic gain control circuit including a variable gain amplifier (11) adapted to receive a received signal (R) and to output an amplified signal (A) to an analog to digital converter (20), and a gain controller (12) which is connected to said variable gain amplifier (11) for receiving said amplified signal (A) and for controlling a gain of said variable gain amplifier (11). The gain controller (12) is adapted to determine an occurrence of a threshold event each time the amplified signal (A) has reached a predetermined threshold, decrease the gain of the variable gain amplifier (11) at each occurrence of a threshold event, measure a delay since the last threshold event, increase the gain of the variable gain amplifier (11) if the delay is greater than a delay specified value and if the gain of the variable gain amplifier (11) is not maximum.

A technique to attenuate even-order harmonics of an output stage of a multistage nested Miller compensation circuit. In one example embodiment, this is accomplished by using a low-bandwidth low-swing amplifier in the common mode feedback loop to improve the even-order harmonic performance in the signal path. The technique uses a separate multistage loop for the common mode feedback loop to attenuate the even-order harmonics. The common mode feedback loop is the fourth stage and uses the third stage of the nested Miller compensation circuit. The fourth stage of the common mode feedback loop includes a single harmonic and uses a low voltage supply to achieve lower power consumption by the common mode feedback loop.

A feedback controller in a PWM amplifier comprises a signal input for receiving a pulse width modulated (PWM) input signal (Vin) whose duty cycle represents a desired analogue output signal. A feedback loop filter 518 generates a filtered error signal (Vint) comprising a filtered representation of differences between the input signal (Vin) and a feedback signal (Vfb). A comparator (520) compares the filtered error signal with a reference to generate a provisional PWM switching control signal (C) for controlling the PWM amplifier (500). A pulse conditioner (532) receives both the provisional PWM switching control signal (C) and the PWM input signal (X=Vin) and outputs to the amplifier (500) a conditioned PWM switching control signal (Y), modified in accordance with predetermined constraints in relation to the PWM input signal. The pulse conditioner includes a single pulse function (534) whereby only a single pulse is permitted for every pulse in the input signal, thereby eliminating oscillations that can otherwise Occur under over-voltage supply conditions. Missing pulse and minimum pulse width functions (536, 538) can also be provided.

A folded-cascode operational amplifier including a differential input stage (19) and a class AB output stage (20) includes a first slew boost current mirror (13) and a second slew boost current mirror (14) having inputs connected to drains of the input transistors, respectively. Each current mirror amplifies excess tail current steered into it as a result of a large, rapid input signal transition. The amplified excess tail current is used to boost the slew rate of the class AB output stage. in accordance with a first polarity of the difference between the first (Vin+) and second (Vin−) input voltages. The drains of the input transistors are maintained at a voltage less than a transistor threshold voltage above the ground except during slewing operation of the operational amplifier to effectively isolate the current mirrors except during slewing operation.

A differential amplifier includes a differential amplifying stage and an output amplifying stage. The output amplifying stage includes a first transistor for pull-up, a second transistor for pull-down, a capacitor element, and switches. The first transistor for pull-up is connected across an output terminal and a high potential side power supply VDD and has a control terminal to which is connected a first differential output. The second transistor for pull-down is connected across the output terminal and a low potential side power supply VSS and has a control terminal to which is connected a second differential output. The switches interchangeably connect the capacitor element across the output terminal and the control terminal of the first transistor for pull-up or across the output terminal and the control terminal of the second transistor for pull-down.

A radio power output amplifier comprises a balanced radio power output that differentially drives a dipole antenna or other balanced load. One half of the differential power output drives one side of the antenna from ground to the maximum positive rail, while the other half of the differential power output drives the opposite side of the antenna from the maximum positive rail to ground. The result is a voltage swing across the antenna that is twice that which would occur if a single ended output was driving an unbalanced load. Since the power output is the square of the voltage divided by the load impedance, the result is four times the power output.

A method and apparatus is provided for detecting the output power of a power amplifier. The output power is detected by detecting the absolute values of the voltage and current at the output of the amplifier and mixing the detected voltage and current to generate a signal related to the output power.

While minimizing any increase in chip size and without incurring a loss in performance or operating characteristic under normal operating voltage conditions, a power amplifier protection circuit effectively prevents breakdown of power amplifying transistors resulting from output load fluctuations during operation with an overvoltage supply. The protection circuit includes a gate circuit electrically connected between the collector and base of at least the last-stage transistor in a power amplifier including transistors connected in stages. The gate circuit passes a feedback current to the base electrode of the protected transistor when a voltage exceeding a specific level is applied to the collector of the protected transistor.

According to an exemplary embodiment, an amplification module includes a power amplifier configured to receive an RF input signal and provide an RF output signal. The amplification module further includes an autobias control circuit configured to receive and convert the RF output signal to a control signal. The control signal can cause the power amplifier to have a quiescent current that increases substantially linearly in response to an increase in the RF output power of the RF output signal. The autobias control circuit can include a peak detector / log converter circuit coupled to a first input of a differential amplifier, where the differential amplifier outputs the control signal. The autobias control circuit can further include a DC reference circuit coupled to a second input of the differential amplifier. The amplification module further includes an analog bias circuit coupling the control voltage to a bias input of said power amplifier.

An overcurrent protection circuit for a power transistor includes a transconductance amplifier and a bias current circuit. The transconductance amplifier receives a first signal indicative of the magnitude of the load current conducted by the power transistor and a reference voltage and provides a second signal for controlling the load current. The transconductance amplifier further provides a third signal having a first logical state indicating normal operation and a second logical state indicating an overcurrent condition at the power transistor. The bias current circuit provides an output bias current to the transconductance amplifier in response to the third signal where the output bias current has a nominal current value in normal operation and an increased current value in an overcurrent condition. In this manner, a boost current is provided to the transconductance amplifier to increase the current limit response time when an overcurrent condition is detected.

The present invention provides a power supply device which can suppress a voltage drop of the input power supply immediately after recovery from shutdown status. The power supply device comprises a reference voltage generation circuit for generating reference voltage (VREF), a transistor for feeding disposed between an input terminal (VTT_IN) and an output terminal (VTT output terminal), a transistor for discharging disposed between a ground potential and a VTT output terminal, a first and second differential amplification circuits for controlling the transistors for feeding and discharging respectively by inputting the output power supply voltage (VTT) as feedback and comparing it with VREF, and a shutdown recovery circuit for generating voltage that gradually starts up by a constant current source and a capacitor, wherein the first differential amplification circuit compares VTT with the voltage (SR) of the shutdown recovery circuit instead of VREF, for a certain period from the point of recovery from shutdown status.

A wireless electric field power transmission system comprises: a transmitter comprising a transmitter antenna, the transmitter antenna comprising at least two conductors defining a volume therebetween; and at least one receiver, wherein the transmitter antenna transfers power wirelessly via electric field coupling when the at least one receiver is within the volume.

The present invention teaches a variety of high VSWR mismatch output stages and methods for protecting output stages during high VSWR operation. To accomplish these goals, the present invention teaches absorbing reverse base current arising at the base of the power transistor of the output stage. In one embodiment, a variable impedance device such as a transistor is coupled to the base of the power transistor such that when the base-emitter voltage exceeds a predefined voltage, the variable impedance device goes into a low impedance mode and absorbs a portion of the base current. In another embodiment, feedback control circuitry is incorporated into the output stage bias circuitry in order to control the total base current.

A wide bandwidth, multi-FET current sharing output stage, MOS audio power amplifier employs multiple feedback loops. An audio input is supplied to a voltage feedback amplifier stage driving a push-pull voltage gain / phase splitter stage. A bias adjustment stage driven from the push-pull voltage gain / phase splitter stage drives a current drive stage. The current drive stage drives an output stage comprising a plurality of paralleled current shared individual MOS output transistors driving an output nodeconnected to a load. Up to three feedback loops are employed. A first voltage feedback loop comprises a voltage feedback stage having an input connected to a voltage divider driven from the first terminal of the load and an output connected to a feedback input node in the voltage feedback amplifier stage. A second voltage feedback loop comprises a voltage feedback stage having an input connected to the first terminal of the load and an output connected to a feedback input node in the push-pull voltage gain / phase splitter stage. A third feedback loop comprises a current feedback stage having an input in series between the output node and the load and an output connected to a feedback input node in the voltage feedback amplifier stage. The current feedback connection works in conjunction with input stage to lower distortion and provide a relatively flat frequency response.

In a high frequency power amplifier module of a multi-stage structure in which a plurality of heterojunction bipolar transistors (npn-type HBTs) are cascade-connected, a protection circuit in which a plurality of pn junction diodes are connected in series is connected between the collector and emitter of each HBT. The p-side is connected to the collector side, and the n-side is connected to the emitter side. A protection circuit in which pn junction diodes of the number equal to or smaller than that of the pn junction diodes are connected in series is connected between the base and the emitter. The p-side is connected to the base side, and the n-side is connected to the emitter side. With the configuration, in the case where an overvoltage is applied across the collector and emitter due to a fluctuation in load on the antenna side, the collector terminal is clamped by an ON-state voltage of the protection circuits, so that the HBT can be prevented from being destroyed. Since the similar protection circuit is assembled between the base and emitter, even when the operator touches the module at the time of manufacturing the high frequency power amplifier module, the HBT can be prevented from being destroyed by the clamping effect of the protection circuit between the base and emitter and the protection circuit between the collector and emitter. Thus, an improved manufacturing yield of the high frequency power amplifier module and a wireless communication apparatus can be achieved, and destruction caused by fluctuation in load impedance of the wireless communication apparatus can be prevented.

A monolithic integrated circuit amplifier has a gain stage and a buffer stage. The buffer stage includes an output stage and two separate voltage supplies, the second of which has a greater magnitude than the first. Switching circuitry is included that is connected to the output stage via a regulator bus. When an output demand voltage is less than a switch-over threshold, current to the output stage is provided substantially entirely from the first voltage supply; when the output demand voltage is greater than the switch-over threshold, current to the output stage is provided substantially entirely from the second voltage supply. Collector voltage at the output stage can be maintained greater than the emitter voltage by a predetermined, substantially constant amount. Voltage headroom circuitry is preferably also included for setting a voltage headroom, that is, the lowest voltage constantly available at the second current terminal of the output transistor relative to the first current terminal of the output transistor.

A threshold value adjustment circuit for adjusting a predetermined threshold value is provided in a stage followed by a protection circuit which starts protection operation when a load current flowing into an MOSFET exceeds the threshold value. A voltage proportional to a drain current and generated between the opposite ends of a current detection resistor Rd inserted between the high-side MOSFET and a positive power supply +V, and an output of an output voltage detection circuit for detecting the voltage amplitude of an analog signal from a low pass filter for modulating an output of a class D amplifier stage are inputted to the threshold value adjustment circuit. The threshold value adjustment circuit adjusts the threshold value in such a manner that a limit current of the MOSFET is set as the threshold value when the output voltage is large, and protection operation is started in response to a lower current than the limit current when the output voltage is small.

Methods, circuits, and apparatuses that provide Buffer Amplifier, containing Amplifiers and Buffer Drivers, one or more of the following: ultra low power Buffer Amplifier, capable of having high gain, low noise, high speed, near rail-to-rail input-output voltage span, high sink-source current drive capability for an external load, and able to operate at low power supply voltages. Methods, circuits, and apparatuses that provide regulated cascode (RGC) current mirrors (CM) capable of operating at low power supply and having wide input-output voltage spans.

The invention provides an amplifier arrangement which is of multistage design. The output transistor in the output stage has a coupling path between its control input and its controlled path. The coupling path comprises a series circuit comprising a Miller compensation capacitance and a resistance with a controllable resistance value. It is thus possible to ensure stable operation of the amplifier regardless of bias and load conditions while simultaneously reducing the quiescent current drawn.