68results about "Single-ended push-pull amplifiers" patented technology

The present invention relates to a high-performance audio amplifier (102) intended to control at least one loudspeaker (R44), the amplifier comprising a preamplifier stage (301) receiving an input signal (S1), a power amplifier stage (302) connected to the preamplifier stage (301), and a negative feedback loop delivering an image of an output signal (3) to the preamplifier stage (301), the power amplifier stage (302) comprising two power supply circuits (155a, 155b), the two power supply circuits comprising MOSFET transistors (M1, M2). The present invention is characterized in that it comprises: a subcircuit for assisting charging, a subcircuit for assisting discharging of the MOSFET transistors (M1, M2), and a voltage shifting subcircuit.

An example apparatus includes class D amplifier circuitry (130) having a first input, a second input, a third input, and an output, the first input of the class D amplifier circuitry (130) being coupled to the output of the class D amplifier circuitry (130); and class AB amplifier circuitry (140) having a first input, a second input, a third input, and an output, the first input of the class AB amplifier circuitry (140) being coupled to the first input of the class D amplifier circuitry (130) and the output of the class D amplifier circuitry (130), the second and third inputs of the class AB amplifier circuitry (140) are coupled to the second and third inputs of the class D amplifier circuitry (130) and the output of the class AB amplifier circuitry (140).

In at least one embodiment, an amplifier (180) is provided. The amplifier (180) includes an input stage, a plurality of output stages, and a combining stage (106). The input stage includes a first input transistor and a second input transistor to receive an input signal. Each output stage includes at least one output resistor. The plurality of output stages is configured to operate in a one of a push mode to output a positive cycle of the input signal to a load and a pull mode to absorb a negative cycle of the input signal from the load. The combining stage (106) includes a plurality of combining resistors, each combining resistor forming a star connection with the output resistors for each output stage to receive a first voltage therefrom and to generate an output voltage based on the first voltage to produce a low distortion output signal at the load.

The present invention makes it possible to obtain low noise and low distortion in both of transistors to which a push-pull operation using a balun is applied.　This amplification device comprises: a first field effect transistor in which an input voltage is applied to the gate; a second field effect transistor connected in series to the first field effect transistor; a first inductor connected to the gate of the second field effect transistor; a second inductor connected in series to the source of the first field effect transistor and step-down inductively coupled to the first inductor; and a third inductor connected in series to the source of the second field effect transistor and step-down inductively coupled to the first inductor.

A system includes a plug that is shared by high-speed data and analog audio transmission. One or more switches may be included to isolate a high-speed data driver from an audio signal amplifier. Gate driving circuits may be used to turn the switches ON and OFF as well as to provide linearization during an ON state of the switches. Linearization may be achieved, at least in part, by applying an absolute value waveform as a component of the gate driving signal.

An amplifier circuit 101 includes: a first current source circuit 113 configured to output a predetermined current amount to a first interconnect L1; a voltage amplifier circuit 110 configured to amplify a voltage of an input signal; a first level shift circuit 111 connected between the first interconnect L1 and an output of the voltage amplifier circuit 110 and configured to shift a voltage of a signal output from the voltage amplifier circuit 110; a first voltage follower 117 connected to the first interconnect L1 and configured to amplify a signal in the first interconnect L1; and a first capacitor 210 connected between the first interconnect L1 and the output of the voltage amplifier circuit 110.

A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.

In some aspects, a programmable amplifier (200A) may comprise an n-channel metal-oxide-semiconductor (NMOS) amplification path and a complementary metal-oxide-semiconductor (CMOS) amplification path. In some aspects, the NMOS amplification path may include a first NMOS transistor (N1) and a second NMOS transistor (N2) that are connected in parallel between an input and an output. In some aspects, the CMOS amplification path may include a p-channel metal- oxide-semiconductor (PMOS) transistor (P1) connected in parallel with the first NMOS transistor (N1) between the input and the output. The programmable amplifier (200a) further comprises a plurality of switches that are programmable to switch the PMOS transistor (Pl) off in a first mode, such as an NMOS mode or a high linearity mode, and to switch the second NMOS transistor (N2) off in a second mode, such as a CMOS mode or a low current mode.

A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.

To provide an amplifier circuit that can be suppressed in heat generation and increases in size, and furthermore can materialize high frequency operation and high power.SOLUTION: An amplifier circuit 101 comprises a first current source circuit 113 that outputs a current having a predetermined amount of a current to a first wiring L1, a voltage amplifier circuit 110 that amplifies the voltage of an input signal, a first level shift circuit 111 that is connected between the first wiring L1 and the output of the voltage amplifier circuit 110 and shifts the voltage of the signal output from the voltage amplifier circuit 110, a first voltage follower 117 that is connected to the first wiring L1 and amplifies the signal in the first wiring L1, and a first capacitor 210 that is connected between the first wiring L1 and the output of the voltage amplifier circuit 110.SELECTED DRAWING: Figure 1

Examples include an image sensor comprising a pixel array having at least one column of addressable pixel sensors, and a column amplifier coupled to the at least one column of addressable pixel sensors, the column amplifier comprising a transistor bank including a plurality of transistors, and mode select circuitry coupled to the transistor bank and configured to establish one or more connections among the plurality of transistors to configure the column amplifier to operate in one of a differential mode of operation and a single-ended mode of operation.

A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node.

A differential signal input buffer (200) is disclosed. The differential signal input buffer (200) may receive a differential signal that includes a first signal and a second signal and may be divided into a first section (260) and a second section (261). The first section (260) may buffer and / or amplify the first signal based on a first level-shifted second signal. The second section (261) may buffer and / or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section (260) may buffer and / or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section (261) may buffer and / or amplify the second signal based on a second level-shifted first signal.

Techniques are disclosed to allow for a switched capacitor digital power amplifier (PA) that operates using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds / Vdg / Vsg.

In at least one embodiment, an amplifier (180) is provided. The amplifier (180) includes an input stage, a plurality of output stages, and a combination stage (106). The input stage includes a first input transistor and a second input transistor to receive an input signal. Each output stage includes at least one output resistor. The plurality of output stages are configured to operate in one of a push mode that outputs a positive period of the input signal to a load or a pull mode that absorbs a negative period of the input signal from the load. The combination stage (106) includes a plurality of combination resistors, each combination resistor forming a star connection with an output resistor of each output stage to receive a first voltage therefrom, and generating an output voltage based on the first voltage to produce a low distortion output signal at the load.

Embodiments of the present disclosure include adaptive bias control of cascode drivers in envelope tracking power amplifier devices, systems, and methods. In some aspects, a wireless communication device is disclosed that includes a power amplifier. The power amplifier may include a driver stage configured to receive a variable voltage supply signal, and a power amplifier stage following the driver stage. In some embodiments, the driver stage includes a cascode gate bias circuit (202) configured to receive a first signal that is based on the variable voltage supply signal; and a cascode amplifier stage (204) comprising a first field effect transistor (Mi) and a second field effect transistor (M2) in a stacked configuration. The cascode gate bias circuit (202) may be further configured to adaptively convert the first signal into a bias signal for a gate of the first field effect transistor (Mi).

The example embodiments are directed to a push-pull amplifier embedded with cross-coupled transistor feedback cancellation. In one example, the amplifier may include a first load, a second load, a circuit comprising first and second field effect transistors (FETs) that are electrically coupled to each other and that are electrically coupled to the first load and the second load, and a feedback cancellation circuit that interconnects the first and second FETs and comprises coupling capacitors configured to increase gain, circuit stability, and Power Added Efficiency (PAE) from the first and second FETs.

A transimpedance amplifier circuit includes an amplifier circuit configured to convert a current signal into a voltage signal with a gain being varied based on a control signal and a gain control circuit configured to generate the control signal based on an amplitude of the voltage signal, an amplitude detection signal in accordance with the amplitude of the voltage signal, an amplitude reference signal, a differential voltage signal obtained by offsetting a voltage difference between the amplitude detection signal and the amplitude reference signal based on an amplitude setting signal, and a differential current signal based on the differential voltage signal. The gain control circuit includes a variable capacitance being varied based on the amplitude setting signal, and is configured to be charged / discharged by the differential current signal and output a charging voltage. The control signal is generated based on the charging voltage.

Examples of circuits, amplifiers, and stages thereof are provided that improve amplifier stability margins while maintaining signal fidelity. Example structures include pre-driver circuitry; a compensation node exhibiting high impedance during operation; a feedforward driver coupled to the pre-driver circuitry; and first and second signal mirrors; and first and second output drivers, each having a control terminal. Example structures further include feedforward circuitry in which a first node thereof is coupled to the output of the feedforward driver, a second node thereof is coupled to the control terminal of the first output driver, and a third node thereof is coupled to the control terminal of the second output driver; and compensation circuitry in which a first node thereof is coupled to the compensation node, a second node thereof is coupled to a first internal node of the first signal mirror, and a third node thereof is coupled to a second internal node of the second signal mirror.

The present disclosure relates to a full-bridge class D amplifier comprising a first and second half-bridge circuit, wherein each half-bridge comprises a half-bridge output terminal (OB1, OB2) between a high-side switch (SH1, SH2) and a low-side switch (SL1, SL2). Wherein the first and second half-bridge circuits are controlled by a respective control signal to operate in differential mode with a predetermined switching frequency and wherein each half-bridge circuit further comprises an output terminal inductor (OL1, OL2) connected between the half-bridge output terminal (OB1, OB2) and ground. The amplifier further comprises a first and second coil (C1, C2) coupled to form a common mode choke, wherein the first half-bridge output terminal (OB1) is connected to an input terminal of the first coil (C1), and wherein the second half-bridge output terminal (OB2) is connected to an input terminal of the second coil (C2).

An analog front-end, AFE, circuit includes a first-stage circuit including a first first-stage transistor including a first first-stage gate electrode connected to an input node of the AFE circuit, a first first-stage source electrode connected to a first supply-voltage node, and a first first-stage drain electrode connected to an output node of the AFE circuit, and a bias-stage circuit connected to the output node of the AFE circuit, the bias-stage circuit including a first bias-stage transistor including a first bias-stage gate electrode, a first bias-stage source electrode connected to the first supply-voltage node, and a first bias-stage drain electrode connected to the first bias-stage gate electrode, and a second bias-stage transistor including a second bias-stage gate electrode connected to the first bias-stage gate electrode, a second bias-stage source electrode connected to the first supply-voltage node, and a second bias-stage drain electrode connected to the output node of the AFE circuit.

This semiconductor device includes: a semiconductor chip which has a main surface; a device region which is partitioned off on the main surface; a differential amplifier which is formed in the device region and which amplifies and then outputs a differential signal that has been input; an insulating layer which is provided on the main surface so as to cover the device region; and a shielding electrode which is incorporated in the insulating layer so as to cover the device region in a view from above and which is fixed to the ground potential.

The present invention provides a linear amplifier including an amplifier stage, a DC-shifting stage, a compensation network and a power stage. The amplifier stage is configured to generate a first signal and a second signal. The DC-shifting stage is configured to adjust a DC voltage of the first signal and a DC voltage of the second signal to generate an adjusted first signal and an adjusted second signal. The compensation network is configured to generate a first driving signal and a second driving signal according to the first signal, the second signal, the adjusted first signal and the adjusted second signal. The power stage is configured to generate an output signal according to the first driving signal and the second driving signal.

A comparator (110) comprises a first stage (101) and a second stage (102). The first stage (101) is configured to provide a first p-voltage signal (115) and a second p-voltage signal (116) in response to a voltage applied to a first (p) input (112) of the first stage. The first stage (101) is further configured to provide a first n-voltage signal (117) and a second n-voltage signal (118) in response to a voltage applied to a second (n) input (111) of the first stage. The first p-voltage signal and the second p-voltage signal are in phase, respectively, and a level of the first p-voltage signal (115) is greater than a level of the second p-voltage signal (116). The first n-voltage signal and the second n-voltage signal are in phase, respectively, and a level of the first n-voltage signal (117) is greater than a level of the second n-voltage signal (118). The second stage (102) comprises a stacked differential pair (106), the stacked differential pair (106) comprising a first branch (107) and a second branch (108). A first p-voltage signal and a second p-voltage signal are applied to the first branch (107), and a first n-voltage signal and a second n-voltage signal are applied to the second branch (108).

The proposed operational amplifier comprises at least one first amplifier circuit (1.1, 1.2, 1.3, 1.4) in a main signal path between input terminals and one or two output terminals of the operational amplifier. A secondary signal path branches off from the main signal path between the input terminals and the first amplifier circuit (1.1, 1.2, 1.3, 1.4), in which a second amplifier circuit (3) is implemented and which is rejoined to the main signal path in the first amplifier circuit (1.1, 1.2, 1.3, 1.4). The first and second amplifier circuits (1.1, 1.2, 1.3, 1.4, 3) are dimensioned such that the signal bandwidth of the main signal path is at least 10 times greater than the signal bandwidth of the secondary signal path and the second amplifier circuit (3) has a lower input offset than the first amplifier circuit (1.1, 1.2, 1.3, 1.4).This makes it possible to implement an operational amplifier with a small input-related offset error voltage while simultaneously having a fast and broadband main signal path and low power consumption.