139results about "Single-ended push-pull amplifiers" patented technology

Apparatus and methods for reconfigurable power amplifiers are disclosed. In certain embodiments, a mobile device includes a transceiver configured to generate a first radio frequency signal of a first frequency band and a second radio frequency signal of a second frequency band, and a front-end system including a push-pull power amplifier configured to selectively amplify one of the first radio frequency signal or the second radio frequency signal based on a band control signal. The push-pull power amplifier includes an input balun, an output balun, and a pair of amplifiers coupled between the input balun and the output balun. The band control signal is operable to control an output capacitance of the pair of amplifiers.

Apparatus and methods for reconfigurable power amplifiers are disclosed. In certain embodiments, a mobile device includes a transceiver configured to generate a first radio frequency signal of a first frequency band and a second radio frequency signal of a second frequency band, and a front-end system including a push-pull power amplifier configured to selectively amplify one of the first radio frequency signal or the second radio frequency signal based on a band control signal. The push-pull power amplifier includes an input balun, an output balun, and a pair of amplifiers coupled between the input balun and the output balun. The band control signal is operable to control an input capacitance of the pair of amplifiers.

In an example, a system includes an amplifier having an output stage configured to provide an output voltage, where the output stage includes a p-channel transistor and an n-channel transistor. The system includes a sense transistor having a gate coupled to a gate of the p-channel transistor, where the sense transistor is configured to sense a current of the p-channel transistor and produce a sense current. The system includes a current mirror coupled to the sense transistor and configured to provide the sense current to a gate of a control transistor, the control transistor having a source coupled to the gate of the p-channel transistor. The system includes a reference current source coupled to the control transistor and configured to provide a reference current. The control transistor is configured to adjust a gate current provided to the p-channel transistor based on comparing the sense current to the reference current.

A power amplifying circuit includes a first amplifier, a second amplifier, a transformer having a primary winding and a secondary winding, and a capacitor. The first amplifier amplifies a signal which is one of differential signals. The second amplifier amplifies a signal which is the other of the differential signals. The primary winding is connected, at its first end, to the first amplifier, and is connected, at its second end, to the second amplifier. The secondary winding is connected, at its first end, to an unbalanced line through which an unbalanced signal is transmitted, and is connected, at its second end, to the ground. The secondary winding is electromagnetically coupled to the primary winding. The capacitor is connected, at its first end, to the midpoint of the primary winding, and is connected, at its second end, to the ground.

A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.

The present invention relates to a high-performance audio amplifier (102) intended to control at least one loudspeaker (R44), the amplifier comprising a preamplifier stage (301) receiving an input signal (S1), a power amplifier stage (302) connected to the preamplifier stage (301), and a negative feedback loop delivering an image of an output signal (3) to the preamplifier stage (301), the power amplifier stage (302) comprising two power supply circuits (155a, 155b), the two power supply circuits comprising MOSFET transistors (M1, M2). The present invention is characterized in that it comprises: a subcircuit for assisting charging, a subcircuit for assisting discharging of the MOSFET transistors (M1, M2), and a voltage shifting subcircuit.

An amplifier circuit (101) is provided with: a first current source circuit (113) that outputs a predetermined amount of current to a first wiring (L1); a voltage amplifier circuit (110) that amplifies the voltage of the input signal; a first level shift circuit (111) which is connected between the first wiring (L1) and the output of the voltage amplifier circuit (110) and shifts the voltage of the signal output from the voltage amplifier circuit (110); a first voltage follower (117) that is connected to the first wiring (L1) and amplifies a signal in the first wiring (L1); and a first capacitor (210) connected between the first wiring (L1) and the output of the voltage amplifier circuit (110).

An example apparatus includes class D amplifier circuitry (130) having a first input, a second input, a third input, and an output, the first input of the class D amplifier circuitry (130) being coupled to the output of the class D amplifier circuitry (130); and class AB amplifier circuitry (140) having a first input, a second input, a third input, and an output, the first input of the class AB amplifier circuitry (140) being coupled to the first input of the class D amplifier circuitry (130) and the output of the class D amplifier circuitry (130), the second and third inputs of the class AB amplifier circuitry (140) are coupled to the second and third inputs of the class D amplifier circuitry (130) and the output of the class AB amplifier circuitry (140).

A sub-1-mm2 die area is presented. This small die with the compact source network (CSN) and compact load network (CLN) can be fully packaged in a small form factor. Previous solutions have integrated all components into the die with complicated matching and bias networks, resulting in a large and expensive die area. Innovative component merging and compact bond-wire matching in the CSN and CLN have substantially reduced the die size for future massive multiple-input-multiple-output (MIMO) small cells. This proposed DPA was designed and fabricated using a commercial 150-nm GaN / silicon carbide (SiC) high electron mobility transistor (HEMT) process to validate architecture and design methodologies.

The invention provides a single-ended non-inductive noise-reduction push-pull LNA circuit, and the circuit comprises a first PMOS tube which is connected with a first current copy port in a grid electrode and is connected with a power input unit in a source electrode; the grid electrode of the first NMOS tube is connected with a second current copy port, the source electrode of the first NMOS tube is grounded, so that the first NMOS tube and the first PMOS tube form a push-pull amplification structure, a main circuit and an auxiliary circuit are connected between the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube, and the main circuit and the auxiliary circuit are connected through a first feedback resistor; drain current is divided into two paths and is converted into feedback voltage on the first feedback resistor; wherein two ends of the first feedback resistor are respectively connected with a radio frequency signal input end and a radio frequency signal output end, and the feedback voltage is fed back to grids of the first PMOS tube and the first NMOS tube so as to offset radio frequency noise. The circuit provided by the invention has the characteristics of low noise, small area, low power consumption, high gain and strong driving capability, and can be applied to various communication circuits.

An amplification circuit for a radio-frequency signal comprises a transistor power amplifier (100) and a fixed regulated power supply (110) for providing an output supply voltage to the transistors (100). The circuit comprises a modulator (160) regulating the output supply voltage in a continuously variable manner, said modulator being dependent on a detector (150) measuring an output radio-frequency signal of the transistor.

In at least one embodiment, an amplifier (180) is provided. The amplifier (180) includes an input stage, a plurality of output stages, and a combining stage (106). The input stage includes a first input transistor and a second input transistor to receive an input signal. Each output stage includes at least one output resistor. The plurality of output stages is configured to operate in a one of a push mode to output a positive cycle of the input signal to a load and a pull mode to absorb a negative cycle of the input signal from the load. The combining stage (106) includes a plurality of combining resistors, each combining resistor forming a star connection with the output resistors for each output stage to receive a first voltage therefrom and to generate an output voltage based on the first voltage to produce a low distortion output signal at the load.

The present invention makes it possible to obtain low noise and low distortion in both of transistors to which a push-pull operation using a balun is applied.　This amplification device comprises: a first field effect transistor in which an input voltage is applied to the gate; a second field effect transistor connected in series to the first field effect transistor; a first inductor connected to the gate of the second field effect transistor; a second inductor connected in series to the source of the first field effect transistor and step-down inductively coupled to the first inductor; and a third inductor connected in series to the source of the second field effect transistor and step-down inductively coupled to the first inductor.

An amplifier comprising a main branch amplifier and an auxiliary branch amplifier, wherein one branch is a constant current-biased branch, and another branch is a voltage biased branch, with the branches connected in predetermined configurations to form a load modulated amplifier.

Analog-to-digital converter (100), ADC, featuring: an input terminal (102) which is configured to receive an analog input voltage signal (VIN); a first ADC stage (108) which is coupled to the input terminal (102) and is configured to output a first digital value (D1) corresponding to the analog input voltage signal (VIN) and a first analog residual signal (VRES1) corresponding to a difference between the first digital value (D1) and the analog input signal (VIN); a first inverter-based residual amplifier (114) configured to receive the first analog residual signal (VRES1), amplify the first analog residual signal (VRES1) and output a first amplified residual signal (VRES1G); a second ADC stage (116) configured to receive the first amplified residual signal (VRES1G) and output a second digital value (D2) corresponding to the first amplified analog residual signal (VRES1G) and output a second analog residual signal (VRES2) corresponding to a difference between the second digital value (D2) and the first amplified analog residual signal (VRES1G); a second inverter-based residual amplifier (118) configured to receive the second analog residual signal (VRES2), amplify the second analog residual signal (VRES2) and output a second amplified residual signal (VRES2G); a third ADC stage (120) configured to receive the second amplified residual signal (VRES2G) and output a third digital value (D3) corresponding to the second amplified analog residual signal (VRES2G); and a control unit (300, 330) coupled to the first ADC stage (108), the second ADC stage (116) and the third ADC stage (120) and configured to combine the first digital value (D1), the second digital value (D2) and the third digital value (D3) into a digital output signal (DOUT) which represents the analog input voltage signal (VIN); wherein the first ADC stage (108) is configured to sample the analog input voltage signal (VIN) during a first operating phase (10, phi1), to convert the analog input voltage signal (VIN) to the first digital value (D1) during a second operating phase (20, phi2), and to retain the first analog residual signal (VRES1) during a third operating phase (30, phi3); wherein the first residual amplifier (114) is deactivated during the first operating phase (10, phi1), is reset during the second operating phase (20, phi2), and is configured to amplify the first analog residual signal (VRES1) during the third operating phase (30, phi3); and wherein the second ADC stage (116) is set up to sample the amplified first analog residual signal (VRES1) during the third operating phase (30, phi3) and to convert the analog input voltage signal (VIN) during the first operating phase (10, phi1), and to convert the amplified first analog residual signal (VRES1) during the first operating phase (10, phi1) and the second operating phase into the second digital value (D2).

A system includes a plug that is shared by high-speed data and analog audio transmission. One or more switches may be included to isolate a high-speed data driver from an audio signal amplifier. Gate driving circuits may be used to turn the switches ON and OFF as well as to provide linearization during an ON state of the switches. Linearization may be achieved, at least in part, by applying an absolute value waveform as a component of the gate driving signal.

The present invention is in the field of booster stage circuit for a power amplifier, and an external supply voltage power amplifier comprising said booster stage circuit, such as for amplifying an electronic signal to a speaker system. These amplifiers may be provided with an external supply voltage.

An amplifier circuit 101 includes: a first current source circuit 113 configured to output a predetermined current amount to a first interconnect L1; a voltage amplifier circuit 110 configured to amplify a voltage of an input signal; a first level shift circuit 111 connected between the first interconnect L1 and an output of the voltage amplifier circuit 110 and configured to shift a voltage of a signal output from the voltage amplifier circuit 110; a first voltage follower 117 connected to the first interconnect L1 and configured to amplify a signal in the first interconnect L1; and a first capacitor 210 connected between the first interconnect L1 and the output of the voltage amplifier circuit 110.

To provide a linear power supply circuit having excellent linearity in input-output characteristic and a small gain error.SOLUTION: A linear power supply circuit 100 includes: an input part 1 to which an input signal Vin is inputted, for outputting first current signals I11, I12; a current-voltage conversion part 2 for converting the first current signals I11, I12 to a first voltage signal V1; a voltage-current conversion part 3 for converting the first voltage signal V1 to second current signals I31, I32; and an output part 4 for generating an output voltage signal Vo from the second current signals I31, I32 by a first current mirror part 41, a second current mirror part 42, and a third current mirror part 43, and outputting the output voltage signal Vo to an output terminal OUT, where the input part 1 and the current-voltage conversion part 2 configure a current feedback type operational amplifier 5.SELECTED DRAWING: Figure 1

A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.

In some aspects, a programmable amplifier (200A) may comprise an n-channel metal-oxide-semiconductor (NMOS) amplification path and a complementary metal-oxide-semiconductor (CMOS) amplification path. In some aspects, the NMOS amplification path may include a first NMOS transistor (N1) and a second NMOS transistor (N2) that are connected in parallel between an input and an output. In some aspects, the CMOS amplification path may include a p-channel metal- oxide-semiconductor (PMOS) transistor (P1) connected in parallel with the first NMOS transistor (N1) between the input and the output. The programmable amplifier (200a) further comprises a plurality of switches that are programmable to switch the PMOS transistor (Pl) off in a first mode, such as an NMOS mode or a high linearity mode, and to switch the second NMOS transistor (N2) off in a second mode, such as a CMOS mode or a low current mode.

A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.

To provide an amplifier circuit that can be suppressed in heat generation and increases in size, and furthermore can materialize high frequency operation and high power.SOLUTION: An amplifier circuit 101 comprises a first current source circuit 113 that outputs a current having a predetermined amount of a current to a first wiring L1, a voltage amplifier circuit 110 that amplifies the voltage of an input signal, a first level shift circuit 111 that is connected between the first wiring L1 and the output of the voltage amplifier circuit 110 and shifts the voltage of the signal output from the voltage amplifier circuit 110, a first voltage follower 117 that is connected to the first wiring L1 and amplifies the signal in the first wiring L1, and a first capacitor 210 that is connected between the first wiring L1 and the output of the voltage amplifier circuit 110.SELECTED DRAWING: Figure 1

Examples include an image sensor comprising a pixel array having at least one column of addressable pixel sensors, and a column amplifier coupled to the at least one column of addressable pixel sensors, the column amplifier comprising a transistor bank including a plurality of transistors, and mode select circuitry coupled to the transistor bank and configured to establish one or more connections among the plurality of transistors to configure the column amplifier to operate in one of a differential mode of operation and a single-ended mode of operation.

A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node.

An apparatus comprising: a positive input for inputting a differential signal; a negative input terminal for the input differential signal; the positive electrode output end is used for outputting differential signals; a negative output terminal for the output differential signal; a first capacitor (C +) comprising a first terminal coupled to the positive output; a second capacitor (C-) comprising a first terminal coupled to the negative output; and a switching network (SWH +, SWL +, SWH-, SWL-) configured to: couple the second terminal of the first capacitor (C +) to the negative input or the positive node based on a mode signal; and coupling a second terminal of the second capacitor (C-) to the positive input or a negative node based on the mode signal (mode).