2 results about "Phase splitter" patented technology

Methods, systems, and devices for techniques for four-phase clocking, and in particular, to a hybrid duty-cycle correction and quadrature error correction (DCC-QEC) circuitry are described. The DCC-QEC circuitry comprises a DCC circuit configured to generate two-phase clock signals based on external clock signals. The DCC circuit is self-calibratable without receiving a reference signal. The DCC-QEC circuitry further comprises one or more QEC circuits coupled to the DCC circuit, each of the QEC circuit comprising a pair of phase splitters configured to convert the two-phase clock signals to four-phase clock signals, and a skew adjuster configured to adjust, based on QEC adjustment codes and in an open loop manner, clock skews associated with a subset of the four-phase clock signals, in which data from multiple lanes of parallel data channels are serialized based on the skew-adjusted four-phase clock signals and transmitted to external of a device comprising the DCC-QEC circuitry.

Methods, systems, and devices for four-phase clocking techniques, and in particular for a hybrid clock cycle correction and quadrature error correction (DCC-QEC) circuit, are described. The DCC-QEC circuit comprises a DCC circuit configured to generate two-phase clock signals based on external clock signals. The DCC circuit is self-calibrating without receiving a reference signal.The DCC-QEC circuit further comprises one or more QEC circuits coupled to the DCC circuit, each of the QEC circuits comprising a pair of phase dividers configured to convert the two-phase clock signals into four-phase clock signals, and an offset matcher configured to match clock offsets associated with a subset of the four-phase clock signals based on QEC matching codes and in an open-loop manner, wherein data from multiple lanes of parallel data channels based on the offset-matched four-phase clock signals are serialized and sent to outside a device comprising the DCC-QEC circuit.