4 results about "Phase splitter" patented technology

Multi-phase clock generators, memory devices, and methods of generating multi-phase clocks are provided. The multi-phase clock generator includes a first variable delay line and a second variable delay line; a first phase splitter configured to phase split a first phase-delayed clock output from a clock tree to output a first divided clock and a third divided clock; a second phase splitter configured to phase split a second phase-delayed clock output from the clock tree to output a second divided clock and a fourth divided clock; a first duty cycle detector configured to detect a first duty cycle error between the first divided clock and the third divided clock; and a second duty cycle detector configured to detect a second duty cycle error between the second divided clock and the fourth divided clock. The first variable delay line is controlled according to the first duty cycle error, and the second variable delay line is controlled according to the second duty cycle error.

Methods, systems, and devices for four-phase clocking techniques, and in particular for a hybrid clock cycle correction and quadrature error correction (DCC-QEC) circuit, are described. The DCC-QEC circuit comprises a DCC circuit configured to generate two-phase clock signals based on external clock signals. The DCC circuit is self-calibrating without receiving a reference signal.The DCC-QEC circuit further comprises one or more QEC circuits coupled to the DCC circuit, each of the QEC circuits comprising a pair of phase dividers configured to convert the two-phase clock signals into four-phase clock signals, and an offset matcher configured to match clock offsets associated with a subset of the four-phase clock signals based on QEC matching codes and in an open-loop manner, wherein data from multiple lanes of parallel data channels based on the offset-matched four-phase clock signals are serialized and sent to outside a device comprising the DCC-QEC circuit.

The invention particularly relates to a method and a system for detecting a phase splitting point of a two-phase absorbent for capturing CO2, and belongs to the technical field of carbon dioxide capturing. The method comprises the following steps: controlling the temperature of an absorbent in a phase splitter, and irradiating with laser with a specific wavelength; a linear array CMOS sensor is used for receiving forward scattered light in the range of 0.1-0.29 degrees and converting the forward scattered light into an electric signal, and a light intensity sequence I (t) is obtained; cO2 is introduced for absorption-standing circulation; by calculating the light intensity relative attenuation rate R (t) and monitoring whether the light intensity relative attenuation rate R (t) is continuously lower than the threshold value Rth for reaching the time Thold or not, the phase splitting point is automatically judged, and the CO2 load is recorded. The system comprises a corresponding optical detection module, a signal processing module and a control analysis module, objective, real-time and high-precision detection of phase splitting points is achieved, and the problems that a traditional naked eye method is large in subjective error, and an existing instrument method is insufficient in sensitivity or difficult to be online are solved.

Methods, systems, and devices for techniques for four-phase clocking, and in particular, to a hybrid duty-cycle correction and quadrature error correction (DCC-QEC) circuitry are described. The DCC-QEC circuitry comprises a DCC circuit configured to generate two-phase clock signals based on external clock signals. The DCC circuit is self-calibratable without receiving a reference signal. The DCC-QEC circuitry further comprises one or more QEC circuits coupled to the DCC circuit, each of the QEC circuit comprising a pair of phase splitters configured to convert the two-phase clock signals to four-phase clock signals, and a skew adjuster configured to adjust, based on QEC adjustment codes and in an open loop manner, clock skews associated with a subset of the four-phase clock signals, in which data from multiple lanes of parallel data channels are serialized based on the skew-adjusted four-phase clock signals and transmitted to external of a device comprising the DCC-QEC circuitry.