270 results about "Analog multiplier" patented technology

A system and method for supplying power to a load and for controlling the power factor presented to the power line. Output voltage is controlled by a digital, outer, control loop, and inner, analog, control loop causes the input current to be substantially proportional to the input voltage at any particular point in the power line cycle. Thus, the system presents a load to the power line that appears to be purely resistive. The use of an analog multiplier is not required, nor is sampling of input voltage. Limiting of inrush current provides for brown-out protection and soft-start.

A notch filter with a high Q factor, which is integrated with a first and a second cascoded LNA, is totally contained on an integrated chip. The notch filter, comprising two Q-enhancement circuits, is coupled to the second differential LNA. The two Q-enhancement circuits are combined to generate sufficient negative impedance to compensate for the loss in the on-chip low Q inductors. To improve the image rejection of the notch filter in a wide frequency band, the notch filter uses an automatic current tuning circuit which consists of an analog multiplier and fixed and voltage controlled current sources. Furthermore, by modifying the connection and location of the tunable varactor, another wideband tunable notch filter is implemented. The notch filter can be applied in all current wireless receiver systems.

Disclosed is a frequency converter including: a passive type analog multiplier configured to output a multiplication result in a current; a buffer outputting a buffering current by buffering the current of the multiplication result; and a current-voltage converter current-voltage converting the buffering current. Alternately, disclosed is a frequency converter including: a passive type analog multiplier configured to output a multiplication result in a current; a buffer outputting a buffering current by buffering the current of the multiplication result; and an integrator integrating the buffering current to output a voltage.

The invention relates to a dual-field analog multiplier/divider which is suitable for an ECC (Elliptic Curve Cypher) algorithm required in high-speed network application and portable mobile equipment application. The analog multiplier/divider comprises four PE operating units, 5 register files (Regfile), a Booth encoding unit, an input register (Load file), a control module (control) and 17 multi-path selectors. The analog multiplier/divider changes the connection of the four PE operating units and the reading position of data through the 17 multi-path selectors so as to complete analog multiplying or analog dividing, has expandability, can support 480-bit analog multiplying/dividing operations maximally, and shares hardware units for multiplying/dividing operations so as to reduce the area of the hardware; and in the algorithm, addition and subtraction and shift operation of long operands are carried out by the unit of byte, therefore, the convergence rate of the algorithm is greatly accelerated, and further the operating speed is multiplied.

A method equalizes a received signal in an optical communications system. The received signal is passed through an analog delay line where it is tapped to generate a set of delayed copies of the received signal. In a set of analog multipliers, each delayed copy of the received signal is multiplied by a corresponding weight to generate a set of weighted signals that are then summed to produce an output signal. The output signal is thresholded and subtracted from the output signal to produce an error signal, which is periodically sampled. In a digital weight updating circuit, the weights are produced from digitized versions of the sampled error signal and samples of the delayed copies of the received signal.

A device, comprising: an array of cells, wherein the cells are arranged in columns and rows; wherein each cell comprises a memristive device; an interfacing circuit that is coupled to each cell of the array of cells; wherein the interfacing circuit is arranged to: receive or generate first variables and second variables; generate memristive device input signals that once provided to memristive devices of the array will cause a change in a state variable of each of the memristive devices of the cells of the array, wherein the change in the state variable of each of the memristive devices of the cells of array reflects a product of one of the first variables and one of the second variables; provide the memristive device input signals to memristive devices of the array; and receive output signals that are a function of at least products of the first variables and the second variables;

The invention discloses an accumulator internal resistance measuring method, which comprises the following steps: first, preparing four terminals with two for measuring and other two for supplying alternating current actuation current signal; second, letting pressure response signal of accumulator multiplied by the sine pressure signal of constant alternating current source in the analog multiplier; third, transforming the alternating current signal output of analog multiplier into direct current signal through low-pass filter circuit; forth, sending the magnified direct current signal into the modular transformation mode.

The invention relates to an extended high base Montgomery analog multiplying algorithm and the circuit structure in the field of integrated circuit technology. It improves multiply characters high base Montgomery analog multiplying algorithm, wherein each step dose left shift operation to the batch N and the multiplicand B but not to the result S so that the delay between the two data path lines can de reduced from two clock weeks to one clock week. The circuit structure comprises: three storages used to store A, B and N operation numbers, a line type data path module which is formed by first stage to p stage processing units, a control module used to control the entire analog multiplier computing course and first-in first-out storage.

The invention discloses a novel fractional order chaotic circuit which comprises two analog multipliers, eight calculation amplifiers, resistors and capacitors. According to the novel fractional order chaotic circuit, oscillograms of X, Y and Z output ends can be observed on an ordinary oscilloscope, and X-Y, X-Z and Y-Z phase diagrams can also be observed. The novel fractional order chaotic circuit is based on an integer order chaotic system, the fractional order calculus theory and a fractional order unit circuit are applied, a frequency domain approximation method based on a bode diagram is adopted, a fractional order chaotic system is realized, and the understand of people on the fractional order chaotic system and the integer order chaotic system is deepened. The novel fractional order chaotic circuit is applicable to chaotic science, experiment teaching and demonstration, science popularization and experiment demonstration and the like in colleges.

The invention discloses an analogy control circuit capable of achieving photovoltaic cell maximum power point tracing, and belongs to the technical field of power electronic application. The analogy control circuit comprises an analogy multiplier, two differentiators, two comparators, an XNOR and a D trigger. According to the analogy control circuit, based on a perturbation and observation method, the change rate of output currents of a photovoltaic cell and the change rate of the output power of the photovoltaic cell are compared, the simple and practical analogy control circuit is used, the output currents and voltages of the photovoltaic cell only need to be sampled, charging-discharging of output end capacitance of the photovoltaic cell is controlled based on on/off, the output currents (or voltages) of the photovoltaic cell are made to achieve maximum power point currents (or voltages), and the maximum power point tracing in the real sense is achieved. The analogy control circuit capable of achieving photovoltaic cell maximum power point tracing is applied to a solar photovoltaic power generating system, and has good engineering application value.

An embodiment of the invention is a predistortion approach to linearize a power amplifier without frequency conversion of the RF signals by using envelope and phase detectors to detect the error to be corrected, and then one or more analog multiplier(s) and a DSP-based processor. For the analog embodiment, the inherent nature of the analog circuitries allows digital predistortion processing structured directly at the RF band, and enables a single power amplifier to support multi-modulation schemes, multi-carriers and multi-channels. As a result, the predistortion architecture is particularly suitable for wireless transmission systems, such as base-stations, repeaters, and indoor signal coverage systems. The wireless system performance can be improved and upgraded just by using the new PA module rather than change or rebuild new subsystem in existing base station. The analog embodiment can also mix and match its analog multipliers with other analog components such as phase splitters, phase shifters, attenuators, filters, couplers, mixers, low-noise amplifiers, buffers, envelope detectors, and etc., to provide additional features.

The invention discloses a multichannel random harmonic modulation sampling radar receiver and a method thereof. The multichannel random harmonic modulation sampling radar receiver comprises a frequency mixer, M analog multipliers, M integrators, M low-speed AD convertors and a target information reconstruction processing module, wherein the frequency mixer is connected with the M analog multipliers; each analog multiplier is connected with one integrator; each integrator is connected with one AD convertor; data collected by the AD convertors are input into the target information reconstruction processing module; and the target information reconstruction processing module achieves the purpose of radar target information estimation through three steps, namely, measurement matrix construction, radar sparse representation matrix construction and reconstruction of radar information. The difficult problem of ultra wide band radar system digital sampling is solved; and a signal reconstruction effect is guaranteed, and the realizing difficulty and the cost of signal hardware modulation are effectively reduced at the same time.

The invention discloses electrostatic interference preventing capacitance measuring circuit and method. The measuring circuit comprises a first signal generator, a second signal generator, a capacitance and voltage conversion module, a band-pass filter, a signal amplifier, an analog multiplier and a low-pass filter; the capacitance and voltage conversion module comprises a capacitance sensor, and a converting module for converting the capacitance detected by the capacitance sensor into voltage; the first signal generator is connected with an exciting electrode of the capacitance sensor; the band-pass filter, the signal amplifier, the analog multiplier and the low-pass filter are sequentially connected in series with the output end of the conversion module; the second signal generator is connected to another signal input port of the analog multiplier; an output signal of the second signal generator has the same frequency with the output siganl of the first signal generator, and the phase difference of the two output signals is zero. Compared with the prior art, the circuit has the advantages that the problem of particle charge interference during charge injection, zero drifting and air and solid flowing as the measuring objects can be overcome, and therefore, measurement deviation can be avoided.

An OFDM receiver having an analog multiplier based I-Q channelizing filter, samples and holds consecutive analog I-Q samples of an I-Q baseband, the I-Q basebands having OFDM sub-channels. A lattice of analog I-Q multipliers and analog I-Q summers concurrently receives the held analog I-Q samples, performs analog I-Q multiplications and analog I-Q additions to concurrently generate a plurality of analog I-Q output signals, representing an N-point discrete Fourier transform of the held analog samples, the I-Q signals having relative phase and magnitude representing bits in the OFDM sub-channels. The phase and magnitude may represent QPSK. Optionally, a phase shift decoder receives the analog transform I-Q output signals and generates a corresponding binary bit data.

A signal reception apparatus in the spread spectrum communication system requires only a small amount of circuitry and consumes a small amount of electric power. A quadrature detector decomposes received signals into in-phase components and quadrature components, and supplies them to a complex-type matched filter. The complex-type matched filter de-spreads the in-phase components and the quadrature components and sends them to a multi-path selector. The multi-path selector selects, from among the received de-spread signals, multiple paths having high levels of signal electric powers and sends the received signals of the selected paths to multiple phase correction blocks. Analog operation circuits calculate phase errors of the received signals of two successive pilot symbol blocks for each path. An analog operation circuit corrects the phases of the received signals of the information symbol block that has been received between the two successive pilot symbol blocks. A rake combiner synchronously combines the phase-corrected de-spread received signals of each path.

The invention discloses a lock-in amplifier of an analog-digital mixed structure and a lock-in amplification method of the lock-in amplifier. The lock-in amplifier comprises an input signal processing system, a reference signal generation system, an analog processing system, an analog-to-digital conversion system and a digital processing system, wherein the first output end and the second output end of the reference signal generation system output two paths of sine wave reference signals which are mutually orthogonal; the analog processing system comprises two analog multipliers and an analog low-pass filter; the digital processing system comprises two digital low-pass filters and a digital operational unit. According to the lock-in amplifier, an aliasing signal is allowed to exist in a signal detection process; through the combination of the analog low-pass filter and the digital low-pass filters, an interference signal in an input signal can be effectively filtered, and a high-frequency interference signal and the aliasing signal are filtered, so that various frequency signals can be detected, the signal to noise ratio is effectively improved, hardware requirements are reduced, and the production cost is lower; the lock-in amplifier can be widely applied to the field of weak signal measurement.

The invention discloses a dual-parameter constant-Lyapunov-exponent four-dimensional autonomous super-chaos system. The dual-parameter constant-Lyapunov-exponent four-dimensional autonomous super-chaos system comprises a math model and a realization circuit, and is characterized in that the realization circuit comprises a first channel circuit, a second channel circuit, a third channel circuit and a fourth channel circuit; the first channel circuit, the second channel circuit, the third channel circuit and the fourth channel circuit comprise three operational amplifiers, and auxiliary resistance and capacitor components that can realize four functions of the math model, respectively; and the realization circuit also comprises four analog multipliers used for realizing two quadratic product terms and a cubic product term of the math model. The realization circuit of the invention is simple in structure and convenient for integration, and can greatly promote the development of the chaos system in the technical fields of electronic measuring, weak signal detection, image encryption and privacy communication.

The invention discloses a beam forming device based on sparse signals and a method of the device. The beam forming device comprises an array element receiving antenna, a multi-input analog adder, an analog multiplier, a pseudorandom sequence generator, an integrator and an A/D convertor, wherein weight coefficients of the multi-input analog adder are submitted to random Bernoulli distribution. After sampling, data reconstruction steps are as follows: 1), main diagonal elements are taken, and sampling data of (K1+1)th row are constructed; 2), the main diagonal elements are taken, and sampling data of (K1+2)th row are constructed; 3); sampling data of left (K2-2) rows are constructed sequentially; and the data of all the rows are summed. According to the beam forming device and the method, a compressed sampling technology is adopted, so that broadband signals can be sampled at a low sampling rate; an airspace projection measurement matrix selects a random Bernoulli array, a phase shifter and a multiplier are not required; a multi-channel structure and a sampling data reconstruction manner are used during time-domain observation projection; and more sampling data comprising a large amount of information can be acquired by the aid of fewer channels.