2 results about "Complex type" patented technology

This invention discloses a training and inference method for complex type inference at the Python repository level. It constructs a semantic graph of types; organizes type semantic contexts and constructs single-round type inference training samples, performing supervised fine-tuning on a large language model to obtain a single-round type inference base model; represents the predicted type and reference type as a type tree, constructing verifiable structured rewards; constructs multi-round refinement objectives according to the depth of the reference type, aggregating round-by-round refinement rewards, termination penalties, and final result rewards to obtain a hierarchical reinforcement learning model; constructs a repository-level scheduling order; for the multi-round refinement process, in each round, multiple candidate outputs are mapped to a depth-constrained abstract type space, and the stage decoding result is obtained through type space self-consistency aggregation, outputting the final predicted type. This invention can simultaneously enhance the cross-process semantic utilization capability, deep structure inference capability, and repository-level type consistency in complex type inference.

The invention relates to the technical field of EDA, in particular to a type definition processing method of an EDA simulator, electronic equipment and a medium, and the method comprises the following steps: respectively creating node structures for type nodes of a simple type and a complex type, obtaining corresponding weights based on a dependency relationship of the node structures, and then constructing a type definition priority queue based on the weights; a type definition of the EDA emulator is generated based on the type definition priority queue. According to the method, the type definition of the EDA simulator can be accurately and quickly processed, and the correct sequence of the type definition during high-level language code generation is ensured, so that the code generation success rate is improved, and the performance of the EDA simulator is improved.