128results about "Amplifier details to increase power/efficiency" patented technology

An apparatus linearizing and technique for linearizing a nonlinear power amplifier used in transmitters of systems for digital wireless communications. Linearization of the nonlinear amplifier is achieved by adding additional signals generated from a specification-given input data stream to the output of the nonlinear power amplifier. The invention allows use of nonlinear power amplifier, which typically enjoys a lower current consumption than that of a linear power amplifier, thus increasing the time between batteries recharges (for user transmitter equipment) and/or reducing the overall size, electric bill expenses, and cooling requirements (for network transmitter equipment). Input data, generated by a given digital wireless standard, is raised to a mathematical power by a required number and converted to RF of a transmitted signal frequency. Then all obtained RF waveforms are added with the same amplitude and the opposite phase to the spectrum of sidelobes generated by nonlinearity of a power amplifier.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage that varies according to a control voltage. The control voltage can be related to a desired output power of the amplifier and/or to an envelope signal of an input signal to the amplifier. Particular biasing for selectively controlling the stacked transistors to operate in either a saturation region or a triode region is also presented. Benefits of such controlling, including increased linear response of an output power of the amplifier, are also discussed.

A monolithic integrated circuit amplifier has a gain stage and a buffer stage. The buffer stage includes an output stage and two separate voltage supplies, the second of which has a greater magnitude than the first. Switching circuitry is included that is connected to the output stage via a regulator bus. When an output demand voltage is less than a switch-over threshold, current to the output stage is provided substantially entirely from the first voltage supply; when the output demand voltage is greater than the switch-over threshold, current to the output stage is provided substantially entirely from the second voltage supply. Collector voltage at the output stage can be maintained greater than the emitter voltage by a predetermined, substantially constant amount. Voltage headroom circuitry is preferably also included for setting a voltage headroom, that is, the lowest voltage constantly available at the second current terminal of the output transistor relative to the first current terminal of the output transistor.

The augmented twin nonlinear two-box modeling and predistortion method for power amplifiers and transmitters provides power amplifier distortion modeling and predistortion linearization. A memoryless nonlinearity is combined with a memory polynomial function that includes cross-terms. The method can utilize an augmented forward twin-nonlinear two-box model, an augmented reverse twin-nonlinear two-box model, or alternatively, an augmented parallel twin-nonlinear two-box model. The present two-box models are validated in modeling and predistortion applications. Measurement results demonstrate the superiority of the present two-box models with respect to conventional state of the art models. The present two-box models lead to better accuracy with reduced complexity.

Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

System and method for integrating an input signal to generate an output signal. The system includes a first integrator configured to receive the input signal and generate an integrated signal based on at least information associated with the input signal, a second integrator configured to receive the integrated signal and generate the output signal based on at least information associated with the integrated signal, and a compensation capacitor coupled to the first integrator and the second integrator. The first integrator includes a first integration capacitor and a first operational amplifier including a first input terminal and a first output terminal, the first integration capacitor being coupled between the first input terminal and the first output terminal. The second integrator includes a second integration capacitor and a second operational amplifier including a second input terminal and a second output terminal.

There is disclosed an amplifier arrangement comprising a plurality of amplifiers each arranged to amplify one of a plurality of different input signals, the arrangement comprising an envelope tracking modulator for generating a common power supply voltage for the power amplifiers, and further comprising an envelope selector adapted to receive a plurality of signals representing the envelopes of the plurality of input signals, and adapted to generate an output envelope signal representing the one of the plurality of envelopes having the highest level at a particular time instant as the input signal for the envelope tracking modulator.

Digital predistortion circuity is disclosed including digital interface circuitry configured to receive a digital input signal having a signal bandwidth (BW) centered about a frequency f₀ and provide a digital transmission signal based on the digital input signal. The digital predistortion circuitry includes circuitry configured to generate a digital correction signal based at least in part on the digital input signal, one or more first signal transmission paths configured to transmit the digital transmission signal, and one or more second signal transmission paths separate from the one or more first signal transmission paths and configured to transmit the correction signal

Improved linearity performance for multi-mode power amplifiers. A power amplifier (PA) assembly can include a radio-frequency (RF) amplification path having a first stage and a second stage, with each stage including a transistor. The PA assembly can further include a biasing circuit having a first bias path between a supply node and the base of a corresponding transistor. The PA assembly can further include a linearizing circuit implemented as either or both of a second bias path and a coupling path relative to the first bias path. The second bias path can be configured to provide an additional base bias current to the base under a selected condition. The coupling path can be configured to improve linearity of the corresponding transistor operating in a first mode while allowing a ballast resistance to be sufficiently robust for the corresponding transistor operating in a second mode.

The digital predistortion system and method with extended correction bandwidth includes a predistortion system that uses a two-box architecture based on the cascade of a memory polynomial followed by a memoryless predistortion function. The memoryless predistorter is identified offline and used to perform a coarse linearization which cancels out most of the static nonlinearity of the device under test allowing for a reduced observation bandwidth for the synthesis of the memory polynomial predistortion sub-function.

The present disclosure includes circuits and methods for wideband biasing. In one embodiment, an amplifier includes a cascode transistor (311) between an input and an output of the amplifier. The cascode transistor (311) receives a bias from a bias circuit comprising a resistor (301) between the power supply (VDD ET) and a first node, a resistor (302) between the first node and a reference voltage, and a capacitor (303) between the power supply (VDD ET) and the first node. The power supply (VDD ET) may be a modulated power supply, which is coupled through the bias circuit to a capacitance (303) at the control terminal of the cascode transistor (311). An inductor (310) is configured between a terminal of the cascode transistor (311) and the power supply (VDD ET). The inductor (310) may isolate the output from the modulated supply signal (VDD ET).

Between resistors 13, 14 and an NPN bipolar transistor 12 are interposed PNP bipolar transistors 21, 22 forming a current mirror 20 that uses a collector current of the NPN bipolar transistor 12 as a reference current, and determines a collector current of an NPN bipolar transistor 11. This makes possible to design a size ratio A of the PNP bipolar transistors 21, 22 so as to approximate a voltage drop DeltaVb to a value close to zero, and to suppress the voltage drop DeltaVb of the base voltage Vb accordingly to achieve a high power output and high efficiency when a high frequency input signal Pin increases and generates a base rectified current.

A linearizer includes: a branch circuit having an input transmission line connected between an input terminal and a branch point, a first output transmission line connected between the branch point and a first output terminal, and a second output transmission line connected between the branch point and a second output terminal; a diode having an anode connected to the branch point and a cathode; and a bias circuit biasing the diode.

A pilot system and method is disclosed that increases the rate of convergence of the second loop alignment control in a feed forward amplifier. Both a pilot generation and detection system and search algorithm controlling the alignment are disclosed. By measuring the frequency of the generated pilot, phase information regarding the second loop cancellation transfer function can be inferred. Changes in the pilot frequency as the search algorithm makes steps in the second loop alignment indicate errors in the direction of the search. Using this pilot frequency measurement along with the existing log-power measurement of the residual pilot power improves the convergence speed because fewer steps will be made to reach the optimal alignment setting.

Embodiments of the present invention disclose a microwave predistorted signal generating method and apparatus. A microwave receiver receives a first received signal that has undergone analog-to-digital conversion; performs channel compensation on the first received signal, to obtain a second received signal; estimates a first transmitted signal according to the second received signal, where the first transmitted signal is a transmitted signal of a microwave transmitter before digital-to-analog conversion; performs predistortion coefficient computation according to the second received signal and the first transmitted signal; performs, by using a first-order coefficient obtained through the predistortion coefficient computation, linear distortion compensation on the second received signal that is before the first transmitted signal is estimated; and sends other predistortion coefficients except for the first-order coefficient to the microwave transmitter, so that the microwave transmitter performs non-linearity predistortion on a transmitted signal.