278results about How to "Reduce the voltage level" patented technology

A write driver circuit including a plurality of programmable fuses for a phase change memory device in which a write operation is correctly performed even in the case where a current output shift in a write current generation circuit; or in the case where a phase change memory cell has a phase change property shift due to an external factor or due a process change. The write driver circuit includes; a write current control unit for outputting a first or second level of voltage selected, by selecting one of a first or second programmable current path, based on whether a first or second selection pulse signal is applied; and a current driving unit for generating a write current controlled by the output voltage of the write current control unit. Each of the first and second programmable current paths includes fuses that can be programmed to adjusted their resistance to adjust the respective selected output voltage to compensate for a current output shift in a write current generation circuit or for a phase change memory cell has a phase change property shift.

A system comprises a primary switch network coupled to a power source, wherein the primary switch network comprises a plurality of power switches, a primary resonant tank coupled to the plurality of power switches, wherein a resonant capacitor of the primary resonant tank is formed by a first variable capacitance network, and wherein the first variable capacitance network is modulated to improve soft switching of the plurality of power switches through reducing a voltage level and a current level of a switch at a turn-on instant and a primary coil coupled to the primary resonant tank.

A multi-battery charging system for reduced fuel consumption and emissions for an automotive vehicle. The system starts the vehicle with a start battery in a fuel savings manner, removing electrical torque from the alternator shaft, and allows a second (run) battery to provide all or some of the current required by the vehicle loads as a fuel savings measure. The system also utilizes an electrically heated catalytic converter (EHC) and a third (EHC or storage) battery to provide a 3 to 15 second preheat and/or a 20 second current, during vehicle start, to the EHC heater coil, e.g., of a small EHC located in series with a standard catalytic converter for emissions reduction to reduce emissions during start. The start battery is recharged after start and switched out of the system fully charged for future vehicle starts. The run battery is recharged when its charge level drops below a predetermined level with an on board battery charging device powered from a 115 volt or 220 volt ac power line source external to the vehicle.

A one-time field programmable (OTP) memory cell with related manufacturing and programming techniques is disclosed. An OTP memory cell in accordance with one embodiment includes at least one resistance change element in series with a steering element. The memory cell is field programmed using a reverse bias operation that can reduce leakage currents through the array as well as decrease voltage levels that driver circuitry must normally produce in program operations. An array of memory cells can be fabricated by switching the memory cells from their initial virgin state to a second resistance state during the manufacturing process. In one embodiment, the factory switching operation can include popping an anti-fuse of each memory cell to set them into the second resistance state. The array of memory cells in the second resistance state are provided to an end-user. Control circuitry is also provided with the memory array that can switch the resistance of selected cells back toward their initial resistance state to program the array in accordance with data received from a user or host device.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage that varies according to a control voltage. The control voltage can be related to a desired output power of the amplifier and/or to an envelope signal of an input signal to the amplifier. Particular biasing for selectively controlling the stacked transistors to operate in either a saturation region or a triode region is also presented. Benefits of such controlling, including increased linear response of an output power of the amplifier, are also discussed.

The release liner includes a release layer constituted of at least one polyolefin resin, wherein the release layer has surface irregularities. The surface irregularities of the release layer may be constituted of recesses and protrusions which are irregularly different in shape and have been disposed in irregular arrangement. The release layer preferably has a surface roughness Ra of 1-3 μm. As the polyolefin resin constituting the release layer can be used at least one polyolefin resin selected from the group consisting of polyethylenes, polypropylene, polybutenes, poly(4-methyl-1-pentene), and copolymers of ethylene with one or more α-olefins having 3-10 carbon atoms.

Systems and methods for detection of charge switching element failure (e.g., charge FET switching element) in a battery system, such as a battery system of an information handling system (e.g. notebook computer), in which an increase in cell voltage is employed as a criteria for detecting charge switching element failure.

A battery charger controller is coupled to DC output terminals of an AC-DC (or DC-DC) adapter containing an AC-DC (or DC-DC) converter. A controlled current flow path between input and output terminals of the battery charger controller circuit is controlled to provide a substantially constant current to charge the battery to a nominal battery voltage. When a constant voltage output of the said adapter transitions to a value that limits available charging current to a value less than programmed constant charging current, current flow drive for the controlled current flow path is increased for a limited time interval. Thereafter, the controlled current flow path gradually reduces charging current as the battery voltage remains at its nominal battery voltage until the charge is complete or otherwise terminated.

A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits.

An electro-luminescence display device includes a supply voltage source; a data driver for driving a plurality of data lines arranged within a panel; a gamma voltage generator for generating gamma voltages to generate analog data voltages corresponding to externally inputted data signals provided to the data driver; and a threshold voltage compensator installed between the gamma voltage generator and the supply voltage source for controlling a supply voltage of the supply voltage source and to apply the controlled voltage to the gamma voltage generator.

A shift circuit of a shift register includes an output terminal, an input terminal, a reset terminal. A voltage is applied to a first wiring in response to the output signal from the preceding stage shift circuit to the input terminal and in accordance with the predetermined voltage to the first wiring, outputting an externally applied signal to the output terminal. A voltage level of the first wiring is reduced in response to the output signal to the reset terminal by the preceding stage shift circuit. The voltage is applied to the second wiring in response to a change in the level of the voltage applied to the first wiring. The voltage is applied to a second wiring in response to the output signal to the reset terminal by the preceding stage shift circuit. A voltage level of the output signal is reduced in response to the predetermined voltage to the second wiring.

A data store and method of storing data is disclosed that comprises: an input for receiving a data value; at least one storage cell comprising: a feedback loop for storing the data value; an output for outputting the stored data value; the feedback loop receiving a higher voltage and a lower voltage as power supply, the data store further comprising: a voltage supply for powering the data store, the voltage supply outputting a high voltage level and a low voltage level; write assist circuitry arranged between the voltage supply and the at least one storage cell, the write assist circuitry being responsive to a pulse signal to provide a discharge path between the high voltage level and a lower voltage level and thereby generate a reduced internal voltage level from the high voltage level for a period dependent on a width of the pulse signal, the reduced internal voltage level being lower than the high voltage level, such that when powered the feedback loop receives the reduced internal voltage level as the higher voltage for a period determined by the pulse width and the high voltage level at other times; and pulse signal generation circuitry for generating said pulse signal.

A silicon-insulator-silicon capacitive (SISCAP) optical modulator is configured to provide analog operation for applications which previously required the use of relatively large, power-consuming and expensive lithium niobate devices. An MZI-based SISCAP modulator (preferably a balanced arrangement with a SISCAP device on each arm) is responsive to an incoming high frequency electrical signal and is biased in a region where the capacitance of the device is essentially constant and the transform function of the MZI is linear.

A semiconductor package has: a first chip; and a second chip. The first chip has: an insulating resin layer formed on a principal surface of the first chip; a bump-shaped first internal electrode group that is so formed in a region of the insulating resin layer as to penetrate through the insulating resin layer and is electrically connected to the second chip; an external electrode group used for electrical connection to an external device; and an electrostatic discharge protection element group electrically connected to the external electrode group. The first internal electrode group is not electrically connected to the electrostatic discharge protection element group.

Provided is a driving circuit of a photosensing touch panel including: a first photodiode coupled between a first voltage source and a sensing node and for generating a first current in accordance with a brightness of an external incident light and a heat of a finger; a second photodiode coupled between the sensing node and a second voltage source and for generating a second current in accordance with the heat of the finger, the second photodiode being shielded from the external incident light; and an amplifier circuit for detecting the brightness of the external incident light regardless of the heat of the finger by subtracting the second current from the first current at the sensing node.

A magnet controller supplied by an AC source controls a lifting magnet. Two bridges allow DC current to flow in both directions in the lifting magnet. During “Lift”, relatively high voltage is applied to the lifting magnet until it reaches its cold current. Then voltage is lowered. After a desired interval, once the magnet has had time to build its electromagnetic field, voltage is further reduced to prevent the magnet from overheating. The magnet lifting forced is maintained due to the magnetic circuit hysteresis. During “Drop”, reverse voltage is applied briefly to demagnetize the lifting magnet. At the end of the “Lift” and the “Drop”, most of the lifting magnet energy is returned to the line source. A logic controller controls current and voltage of the magnet and calculates the magnet's temperature. In one embodiment, a “Sweep” switch is provided to allow reduction of the magnet power to prevent attraction to the bottom or walls of magnetic rail cars or containers.

A pixel driving circuit includes a first driver and a second driver. The first gate driver includes a plurality of stage units connected to odd-numbered gate lines. The second gate driver includes a plurality of stage units connected to even-numbered gate lines. Each of the stage units of the first and second gate drivers includes an input unit, a first signal output unit, and a second signal output unit. The input unit outputs a driving control signal according to a previous stage driving signal output from the previous stage unit and a next stage driving signal output from the next stage unit. The first signal output unit outputs a stage driving signal according to the driving control signal and a driving clock signal. The second signal output unit outputs a gate voltage signal to the corresponding gate line according to the driving control signal and a gate clock signal.

A shift register having a built-in level shifter includes a buffer outputting a shift pulse using a first clock signal and a first supply voltage via voltages at first and second nodes; a first controller controlling the voltage of the first node via the start pulse and the second node; and a second controller controlling the second node voltage using the first and second supply voltage via the start pulse and the second clock signal. The level shifter includes a third controller forming a current path between third supply voltage input line and first supply voltage input line controlling a third node using the first supply voltage and a third supply voltage via the voltage of the second node and two of first to fourth clock signals; and an output part outputting the level-shifted shift pulse using the first and third supply voltage via the voltage at the third node.