26 results about "RC time constant" patented technology

The invention discloses an electrostatic and surge protection circuit, and the circuit comprises a first detection module which is provided with a fixed first RC time constant, is connected with a power supply VDD, and is used for outputting a first control signal when an electrostatic discharge event occurs, and outputting a second control signal when a surge event occurs; the second detection module has an adjustable second RC time constant, is connected with the first detection module and the power supply VDD, and is used for generating a third control signal according to the first control signal or the second control signal; the first end of the first switch is connected with the power supply VDD, the second end of the first switch is grounded, and the control end of the first switch is connected with the second detection module; and the control end of the first switch can control the first end and the second end of the first switch to be electrically conducted according to the third control signal, so that the power supply VDD discharges charges when a surge event and an electrostatic discharge event occur. According to the invention, the protection requirements of electrostatic discharge and surge can be met at the same time in the chip, so that the integration level of electronic equipment is improved and the manufacturing cost is reduced.

The invention discloses an electrostatic discharge clamping circuit capable of preventing false triggering, which belongs to the technical field of electrostatic discharge protection of integrated circuits and comprises a control transistor, a PMOS (P-channel Metal Oxide Semiconductor) current mirror resistor branch, an NMOS (N-channel Metal Oxide Semiconductor) current mirror capacitor branch, an inverter and a clamping transistor, through feedback control and voltage division design, an RC structure formed by a PMOS current mirror resistor branch and an NMOS current mirror capacitor branch has different RC time constant numbers during an electrostatic discharge event and normal power-on or rapid power-on, and has a good anti-false-triggering characteristic; the small capacitor and the small resistor are amplified through two groups of current mirror structures, and the layout area occupied by the resistor and the capacitor is greatly reduced based on the equivalent large resistor and the large capacitor. According to the invention, the problems that the electrostatic discharge clamping tube in the existing integrated circuit is easy to trigger mistakenly and the resistor and the capacitor occupy a large layout area are solved.

An equalizer stage circuit includes a first transistor and a second transistor disposed in a differential configuration. The equalizer stage circuit also includes a first selectable path. The first selectable path includes: a first terminal coupled to an emitter or a source of the first transistor; a second terminal coupled to an emitter or a source of the second transistor; a high-frequency portion comprising a first plurality of high-frequency RC time constant members connected in parallel between the first terminal and the second terminal; a first capacitor coupled to the first terminal; a second capacitor coupled to the second terminal; and a low-frequency portion comprising a second plurality of low-frequency RC time constant members connected between the first capacitor and the second capacitor.

A resistor-capacitor (RC) sensor circuit is provided. The circuit includes a regulator configured to drive a circuit line; one or more current mirrors coupled to the regulator to obtain a representative copy of a current of the circuit line; and an integrator comprising an analog-to-digital converter (ADC). The ADC is coupled to the one or more current mirrors to receive the representative copy of the current of the circuit line and is configured to: integrate the representative copy of the current of the circuit line for a plurality of time intervals to obtain a plurality of charges associated with the respective time intervals; and output digital data that is used to calculate an RC time constant. The plurality of time intervals are within a first ramping time period for ramping the far-end voltage of the circuit line from a first voltage value to a second voltage value.

The phenomenon of charge trapping and its impact on noise performance of an imaging array using thin film transistor switches can be ameliorated by compensation techniques. One such compensation technique is a recovery process by which trapped charges are detrapped through the periodic imposition of thermal, optical, and / or bias energy. Another technique involves a shield line overlying the transistor switches and connected to the gate base to reduce the gate base resistance and hence reduce changes in the RC time constant of the gate bus.

The present disclosure relates to tracking RC time constants through word lines in a memory device. A memory device includes a memory array comprising a plurality of word lines, and control logic operably coupled with the memory array. The control logic causes a measurement programming pulse to be sequentially applied to each of the plurality of word lines of the memory array, and determines respective threshold voltages stored in a plurality of memory cells associated with each of the plurality of word lines. The control logic further determines a difference between the respective threshold voltages based on a location of the plurality of memory cells within each word line, and determines a respective resistance-capacitance, RC, time constant for each of the plurality of word lines in view of the difference between the respective threshold voltages.

A memory device includes a memory array comprising a plurality of wordlines, and control logic, operatively coupled with the memory array. The control logic causes a measurement programming pulse to be sequentially applied to each of the plurality of wordlines of the memory array and determines respective threshold voltages stored in a number of memory cells associated with each of the plurality of wordlines. The control logic further determines a difference in the respective threshold voltages based on a location of the number of memory cells within each wordline and determines a respective resistance-capacitance (RC) time constant for each of the plurality of wordlines in view of the difference in the respective threshold voltages.

The application relates to a PWM control analog quantity output method and device, computer equipment and a storage medium. The method comprises the following steps: obtaining a target analog quantity output value V and converting the target analog quantity output value V into a target fixed-point quantization value D; selecting a time point at which an output analog quantity change rate is lower than a preset threshold value as a stable time point t1, collecting a steady-state duty cycle P1, a steady-state quantization value D1 and a steady-state analog quantity output value V1 at the stable time point t1, and calculating an RC time constant of a capacitor at the stable time point t1 according to the steady-state duty cycle P1, the steady-state quantization value D1 and the steady-state analog quantity output value V1; selecting a corresponding segmented processing strategy according to the target fixed-point quantization value D and the steady-state quantization value D1 at the stable time point to generate a PWM output duty cycle P; performing integral correction on the PWM output duty cycle P to obtain a corrected duty cycle P'; updating the corrected duty cycle P' after correction to a PWM register to obtain an actual output analog quantity, and the value of the actual output analog quantity is an actual analog quantity output value V'. The application has the effect of improving the real-time performance of PWM control analog quantity output.

An equalizer stage circuit includes a first transistor and a second transistor disposed in a differential configuration. The equalizer stage circuit also includes a first selectable path. The first selectable path includes: a first terminal coupled to an emitter or a source of the first transistor; a second terminal coupled to an emitter or a source of the second transistor; a high-frequency portion comprising a first plurality of high-frequency RC time constant members connected in parallel between the first terminal and the second terminal; a first capacitor coupled to the first terminal; a second capacitor coupled to the second terminal; and a low-frequency portion comprising a second plurality of low-frequency RC time constant members connected between the first capacitor and the second capacitor.

A resistor-capacitor (RC) sensor circuit of an electronic device drives a representative copy of a current driving an electronic circuit line of the electronic device to a drive voltage. The RC sensor circuit is to sample a voltage indicative of an RC time constant of the electronic circuit line. A first sample voltage is determined by sampling a first representative voltage generated at the RC sensor circuit by driving the RC sensor circuit with the representative copy of the current for a first period of time. A second sample voltage is determined by sampling a second representative voltage generated at the RC sensor circuit by driving the RC sensor circuit with the representative copy of the current for a second period of time. A ratio of the first sample voltage to the second sample voltage is indicative of the RC time constant of the electronic circuit line.

To improve performance such as RC time constant reduction and slew rate improvement regarding analog signal settling. A settling acceleration circuit includes a first transistor having an output terminal where a capacitive component exists, a gate electrode being connected to the output terminal; a first capacitor connected to a source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from a drain terminal of the first transistor to output the amplified current to an output node; a second constant current source connected to the output node; and a first switch disposed between the output terminal and the output node. Then, after an end of the settling acceleration period in which the first switch is made conductive to accelerate the settling of the voltage of the output terminal, the first switch is cut off, and the reading circuit connected to the output terminal reads the voltage of the output terminal. The present technology can be applied to, for example, an imaging element such as a CMOS image sensor.

An RC sensor circuit includes a driver circuit including an output configured to drive the RC sensor circuit to a drive voltage using a representative copy of a current of a driver electronic circuit line. The RC sensor circuit includes an integration capacitor. The integration capacitor is configured to integrate the representative copy of the current over a first time period to generate a first representative voltage and integrate the representative copy of the current over a second time period to generate a second representative voltage. The RC sensor circuit includes a sampling circuit coupled to the integration capacitor. The sampling circuit is configured to determine a first sampled voltage by sampling the first representative voltage and determine a second sampled voltage by sampling the second representative voltage. A ratio of the first sampled voltage to the second sampled voltage is indicative of an RC time constant of the electronic circuit line.

Circuits and methods for generating a bypass pulse to an RF circuit that increases the response time of the circuit to mode changes. Embodiments include a pulse generation circuit that it is self-initiated and self-terminated, generating a bypass pulse as a function of voltages V1 and V2 along a signal path. Voltage V3, a scaled version of V1, is compared to a voltage V4 derived from V2 and a pulse is output while V3>V4. The pulse temporarily lowers the signal path impedance, reducing the RC time constant of the signal path and allowing fast charging of components coupled to the signal path. The pulse may be used with any other circuit that needs a faster settling time after a mode change but is slowed down by an RC time constant. Usage also extends to providing for rapid discharge of the signal path by adding additional logic components.

This invention discloses a pseudo-resistor circuit, an RC filter circuit, a current mirror circuit, and a chip. The pseudo-resistor circuit includes a first MOSFET and a bias circuit. The bias circuit provides a bias voltage between the gate and source of the first MOSFET to enable the first MOSFET to operate in the subthreshold region, and adjusts the resistance value of the first MOSFET by adjusting this bias voltage. The pseudo-resistor circuit, RC filter circuit, current mirror circuit, and chip of this invention can achieve a high resistance value with a smaller area. This reduces the resistor area and allows for a smaller capacitor value to achieve the same RC time constant, thus reducing the capacitor area. Furthermore, the resistance value of this pseudo-resistor is less affected by process voltage-temperature (PVT), ensuring that the filtering effect of the RC filter does not change significantly with variations in PVT.

The invention relates to real-time circuit line resistance-capacitance detection. A resistance-capacitance (RC) sensor circuit is provided. The circuit includes: a regulator configured to drive a circuit line; one or more current mirrors coupled to the regulator to obtain a representative copy of the current of the circuit line; and an integrator including an analog-to-digital converter (ADC). The ADC is coupled to the one or more current mirrors to receive the representative replica of the current of the circuit line and is configured to: integrate the representative replica of the current of the circuit line over a plurality of time intervals to obtain a plurality of charges associated with the respective time intervals; and outputting digital data for calculating the RC time constant. The plurality of time intervals are within a first ramp period that ramps a distal voltage of the circuit line from a first voltage value to a second voltage value.

An equalizer stage circuit includes a first transistor and a second transistor disposed in a differential configuration. The equalizer stage circuit also includes a first selectable path. The first selectable path includes: a first terminal coupled to an emitter or source of the first transistor; a second terminal coupled to an emitter or a source of the second transistor; a high frequency portion including a first plurality of high frequency RC time constant components connected in parallel between the first terminal and the second terminal; a first capacitor coupled to the first terminal; a second capacitor coupled to the second terminal; and a low frequency portion including a second plurality of low frequency RC time constant components connected between the first capacitor and the second capacitor.

The invention discloses an RC time constant calibration system based on an ADC system, and relates to the field of RC time constant calibration. The system comprises a control module, an RC charging circuit and a capacitor network, the RC charging circuit is used for charging the energy storage capacitor to a preset target voltage; the control module is used for controlling on and off of charging of the RC charging circuit and recording calibration time when the energy storage capacitor is charged to a preset target voltage; determining a compensation capacitance value according to a difference value between the calibration time and preset theoretical time; the capacitor network comprises a plurality of capacitor units which are connected in parallel, and the control module is further used for controlling the number of the energy storage capacitor units connected into the capacitor network according to the compensation capacitance value. According to the invention, the technical problem that the RC time constant is easy to deviate and cannot be efficiently and accurately calibrated and corrected in the ADC design in the prior art is solved.

The application discloses a mistaken trigger prevention electrostatic discharge clamping circuit, and belongs to the technical field of integrated circuit electrostatic discharge protection, which comprises a control transistor, a PMOS current mirror resistance branch, an NMOS current mirror capacitance branch, an inverter and a clamping transistor; through feedback control and voltage division design, the RC structure composed of the PMOS current mirror resistance branch and the NMOS current mirror capacitance branch has different RC time constants in electrostatic discharge events and normal or fast power-on, and has good mistaken trigger prevention characteristics; the application also amplifies small capacitance and small resistance through two groups of current mirror structures, and based on equivalent large resistance and large capacitance, greatly reduces the layout area occupied by the resistance and capacitance. The application solves the problems of easy mistaken trigger of the electrostatic discharge clamping transistor and large layout area occupied by the resistance and capacitance in the existing integrated circuit.

A circuit arrangement for charge integration comprises an input (1) for applying a signal representing a charge pulse, an output (2) for providing an integrated signal, and an integration circuit (3) connected between the input (1) and the output (2), comprising a resistance circuit (5) and a capacitor (6) and having an RC time constant which is a function of the resistance circuit (5) and the capacitor (6). The circuit arrangement further comprises a feedback control circuit (7) connected at its input to the output (2) of the circuit arrangement and providing at its output a control signal, wherein at least one of the resistance circuit (5) and the capacitor (6) has a variable value which depends on the control signal.

An equalizer stage circuit includes a first transistor and a second transistor disposed in a differential configuration. The equalizer stage circuit also includes a first selectable path. The first selectable path includes: a first terminal coupled to an emitter or a source of the first transistor; a second terminal coupled to an emitter or a source of the second transistor; a high-frequency portion comprising a first plurality of high-frequency RC time constant members connected in parallel between the first terminal and the second terminal; a first capacitor coupled to the first terminal; a second capacitor coupled to the second terminal; and a low-frequency portion comprising a second plurality of low-frequency RC time constant members connected between the first capacitor and the second capacitor.

The reserve tank element of the present invention has a plurality of units, and the units constituting the plurality of units are respectively connected to at least one other unit, and the plurality of units respectively include: an input terminal for inputting a first signal and a resistor connected to the input terminal; a capacitor connected to the side of the resistor opposite to the input terminal and located between the resistor and a reference potential; a switching element connected to the capacitor; and an output terminal connected to the switching element, and the RC time constant of at least one of the plurality of units is different from that of the other units.

The invention belongs to the technical field of clock signal synchronization, and particularly relates to an adjustable delay circuit, which comprises a current starvation driving module used for outputting a driving signal with preset current magnitude according to an input signal of the adjustable delay circuit; the current enhancement driving module is used for enhancing the current of the driving signal; the RC adjusting module is used for adjusting an RC time constant of the adjustable delay circuit, so that the driving signal is output after being delayed for preset time; the RC adjusting module comprises an adjustable resistor; the adjustable capacitor comprises at least one long delay capacitor and a plurality of MOS (Metal Oxide Semiconductor) capacitors, and the long delay capacitor and each MOS capacitor are respectively provided with a corresponding transmission gate, so that the long delay capacitor and each MOS capacitor are connected to the adjustable delay circuit or disconnected from the adjustable delay circuit; and the capacitance value of the long delay capacitor is at least greater than the capacitance value of any MOS capacitor. According to the adjustable delay circuit provided by the invention, the high-precision and wide-range delay adjustment requirements can be met by adjusting the resistance, the capacitance and the driving capability.

A reservoir element includes a plurality of units. Each of units constituting the plurality of units is connected to at least one or more different units. Each of the plurality of units includes an input terminal to which a first signal is input, a resistor which is connected to the input terminal, a capacitor which is connected to an opposite side of the resistor to the input terminal and is provided between the resistor and a reference potential, a switching element which is connected to the capacitor, and an output terminal which is connected to the switching element. At least one of the plurality of units differs from other units in an RC time constant.

To improve performance such as RC time constant reduction and slew rate improvement regarding analog signal settling.SOLUTION: A settling acceleration circuit comprises: a first transistor in which a gate electrode is connected to an output terminal where a capacitive component is present; a first capacitor connected to a source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from a drain terminal of the first transistor to output the amplified current to an output node; a second constant current source connected to the output node; and a first switch arranged between the output terminal and the output node. After the end of a settling acceleration period in which the first switch is made conductive to accelerate the settling of the voltage of the output terminal, the first switch is cut off, and a read-out circuit connected to the output terminal reads out the voltage of the output terminal. The present technique can be applied, for example, to an image pickup device such as a CMOS image sensor.SELECTED DRAWING: Figure 1

Circuits and methods for generating a bypass pulse to an RF circuit that increases the response time of the circuit to mode changes. Embodiments include a pulse generation circuit that it is self-initiated and self-terminated, generating a bypass pulse as a function of voltages V1 and V2 along a signal path. Voltage V3, a scaled version of V1, is compared to a voltage V4 derived from V2 and a pulse is output while V3>V4. The pulse temporarily lowers the signal path impedance, reducing the RC time constant of the signal path and allowing fast charging of components coupled to the signal path. The pulse may be used with any other circuit that needs a faster settling time after a mode change but is slowed down by an RC time constant. Usage also extends to providing for rapid discharge of the signal path by adding additional logic components.

The application provides a slow start high-voltage circuit suitable for silicon detectors with various sensitive layer thicknesses, in a high-frequency oscillation circuit, when a transistor is turned on, an induced electromotive force is generated in a primary coil of a transformer, when the transistor is saturated, the induced electromotive force generated in the primary coil of the transformer prevents the decrease of current, thereby a circulating oscillation signal is formed, after the power supply is powered on, the voltage can be adjusted through the adjustment of an RC circuit; a voltage doubling rectifier circuit doubles the oscillation signal; the slow start circuit adjusts the time length of slow start through an RC time constant circuit, the time length of power supply to the silicon detector is delayed after the RC time constant circuit is powered on through a field effect transistor, the impact current when the power supply is powered on is reduced through the slow start circuit, the output current is extremely small, is a microampere level current, the detector can work in a full depletion state, and is suitable for systems with high power consumption requirements.