This invention discloses a fractional phase-locked loop (PLL) based on multi-path quantization
noise compensation. It introduces a
data synchronization circuit based on the falling edge of the reference
clock, ensuring that the divider signals of all paths have reached
steady state before the
phase detector is triggered by the next rising edge of the PFD, thus completely eliminating dynamic timing interference in the mixed-
signal path. By introducing a multi-path retimer with a
sign bit, the compensable quantization
noise range is expanded. The current-DAC type
charge pump proposed in this invention adopts a
charge pump architecture based on a source switch array and a static
discharge current. The source switch array utilizes the
low impedance characteristics of the source nodes of the
current source transistors, significantly improving the switching speed and reducing the
settling time. The static
discharge current forces the loop to maintain a fixed non-
zero phase offset in the locked state, permanently shifting the
charge pump operating point out of the nonlinear region and deeply suppressing fractional spurious emissions.