71 results about "Low jitter" patented technology

The invention provides a transaction data processing method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring the market information of an electric power spot market in a current period, declaration strategies of a plurality of users and execution return in a previous period; performing priority ranking on the users based on the strategy and the market information to obtain a ranked user sequence; obtaining a target order of the user based on a standard price determined by the market information and the strategy, a price change step length and a transaction electric quantity in the strategy and the user sequence; carrying out comparison processing on the target order and the hung order executing the return to obtain a comparison result; and generating an order execution operation in the current period based on the comparison result, the target order and the hung order. According to the method, aggregation and account-level concurrency control in a period can be realized, so that stable throughput and low jitter can be kept under multiple parallel users, and high concurrency stability in a transaction data processing process is improved.

The invention discloses a power supply control method and system based on a real-time slope adjustment algorithm, and the method comprises the steps: monitoring the load impedance characteristics of a power supply and environment noise data in real time, and obtaining an independent control time slice set; obtaining a time sequence identifier of the control time slice set, and obtaining a dynamic mode parameter packet bound with the current load characteristic; obtaining a real-time voltage / current regulation instruction set with a feed-forward compensation coefficient according to the dynamic mode parameter packet and the error tolerance data; analyzing the real-time voltage / current regulation instruction set, and combining the historical working condition similarity data to obtain an optimized PID coefficient matrix and a feed-forward gain vector; and executing the optimized PID coefficient matrix and the feed-forward gain vector, and generating and outputting a four-dimensional space trajectory signal which is completely matched with the target slope trajectory as a direct driving reference of a power supply power device. According to the embodiment of the invention, high-precision and low-jitter real-time slope tracking control can be realized, and the dynamic response speed and anti-interference robustness of a power supply system are improved.

The invention belongs to the technical field of laser precision machining and control, and particularly relates to a femtosecond laser single-point trigger control system and method based on subnanosecond synchronization, and the method comprises the following steps: S1, building a system synchronization clock locked with a femtosecond laser pulse signal phase; the specific mode of establishing the system synchronous clock is that phase locking is carried out on pulse synchronous signals or frequency division signals output by an internal high-frequency clock source and a femtosecond laser source through a digital phase-locked loop technology, and the low-jitter system synchronous clock which is strictly synchronous with a laser pulse sequence is generated. According to the invention, a system clock locked with a laser pulse phase can be generated through a digital phase-locked loop, and the influence of inherent frequency drift of a laser and circuit delay temperature drift is effectively overcome by combining real-time delay calculation based on a prediction algorithm and a high-resolution DDS delay line technology; the synchronization precision between the triggering moment of the single pulse and the external instruction is stabilized at the subnanosecond level, and the requirement of leading-edge application for the extreme time sequence precision is met.

The application relates to the technical field of time synchronization, and discloses a mixed time service method based on Beidou satellite navigation and TSN, which comprises the following steps: acquiring network topology structure information and historical time service error data of each synchronization node in a target distributed system, and constructing a dynamic time delay state set for jitter identification; based on the dynamic time delay state set, a current global time reference is extracted through a time calibration algorithm, a time difference reference vector sequence is generated, and initial synchronization adjustment is carried out on a TSN master node; according to the response stability of a slave node, a clock convergence function curve between nodes is constructed, whether the synchronization network is in a low jitter interval is judged based on time offset rate and time drift trend change; in combination with the node time state after directional offset suppression, a multi-channel redundant time adjustment mechanism in a time window is applied, a weight adjustment coefficient is extracted, and a non-uniform calibration factor is introduced; and according to a regression correction result, a time service stability index is evaluated in real time. The application has the advantages of improving time service stability.

The invention provides a three-dimensional stacked packaging substrate device and a manufacturing method, and relates to the technical field of semiconductor packaging, and the three-dimensional stacked packaging substrate device comprises a substrate which is a multi-layer stacked substrate; a drop point area corresponding to the vertical interconnection terminal is provided with a backflow channel, and the backflow channel comprises a grounding via hole array or a grounding metal ring surrounding the drop point area and is used for providing a continuous reference loop for a high-speed signal transmitted through the vertical interconnection terminal. Providing a core plate, carrying out multi-layer lamination, and manufacturing a backflow channel in a corresponding vertical interconnection terminal drop point area; manufacturing blind holes or micro holes in the substrate to realize interlayer interconnection; the substrate is divided into a high-speed digital area, an analog / radio frequency area and a power supply area according to functions for partition wiring, and the ground plane of each partition is kept continuous; a decoupling device is arranged at the near end of the vertical interconnection drop point or the chip power supply inlet. The system has the beneficial effects that low reflection, low jitter and low bit error rate of high-speed signal transmission are realized, and the electromagnetic compatibility and the working reliability of the system are improved.

Embodiments of the present disclosure disclose a key point identification method and device, electronic equipment and storage medium, wherein the method comprises: inputting a target video frame into a preset model, outputting at least three predicted positions of each key point in the target video frame based on the preset model; determining candidate regions of the key points in the target video frame according to the at least three predicted positions of the key points; and determining the final position of the corresponding key point in the target video frame from each candidate region according to the final position of the key point in the adjacent frame earlier than the target video frame in time sequence. Without manual adjustment of parameters, the method can significantly reduce jitter and ensure the accuracy of key point prediction.

The present application relates to electronic endoscope technical field, specifically, it relates to a kind of endoscope multiplexing line built-in MIPI-CSI signal long-distance transmission isolation enhancement device.It includes the control end module, receiving end module and power management unit integrated in multiplexing line, and power management unit is used to power control end module, receiving end module.Power management unit in the present application, by the high integration of control end module, receiving end module and power management unit in multiplexing line, signal conditioning and isolation enhancement unit of control end can effectively process original signal and inhibit common-mode interference, then with the equalization compensation and clock data recovery circuit of receiving end repair signal attenuation and timing distortion problem caused by long-distance transmission, to realize in complex electromagnetic environment still can stable output low jitter, high integrity video signal, fundamentally solve the problem of affecting diagnostic accuracy due to image delay, quality decline.

This invention relates to the field of phase-locked loop (PLL) technology, specifically to a method for achieving low jitter over a wide locking range by optimizing the PLL structure. The method includes: outputting a first error signal through a phase detector, obtaining the characteristics of the first error signal, and constructing a first error signal function; obtaining a first adaptive loop bandwidth; constructing a multi-band voltage-controlled oscillator (VCO) matching mechanism, including VCOs in multiple frequency bands; during PLL locking, selecting a frequency band based on the input signal frequency and the center frequency band of the VCO to obtain a first matching frequency band; and calculating the root mean square (RMS) of the first error signal based on further analysis of the first error signal characteristics, and combining the initial feedback gain and the initial error signal RMS to obtain a first feedback gain adjustment value. This invention achieves low jitter over a wide locking range through adaptive loop bandwidth adjustment, a multi-band VCO matching mechanism, and adaptive feedback gain adjustment.

The invention provides an FPGA-based programmable periodic pulse signal generation method and application thereof, and belongs to the technical field of electronic measurement. In order to solve the problems that the large dynamic range and the high resolution are difficult to consider at the same time and hardware resources are consumed synchronously by multiple channels in the prior art, according to the method, coarse delay is achieved through FPGA system clock counting, and next pulse parameters are calculated through accumulation of remaining decimal parts; picosecond-level fine delay is realized by constructing a three-level cascade architecture consisting of a lookup table, a coarse carry chain and a fine carry chain; and XOR synthesis waveforms after rising edges and falling edges are independently generated respectively. In addition, the inter-channel transmission delay difference is compensated by correcting the initial calculation parameters. According to the multi-channel pulse signal generation circuit, high-precision, low-jitter and strictly-aligned-phase multi-channel pulse signals can be generated only by utilizing pure logic resources of the FPGA.

The invention provides a low-jitter pulse signal generation circuit, which relates to the technical field of synchronous control signals and comprises an FPGA (Field Programmable Gate Array) chip U1 and a low-jitter clock phase-locked loop chip U2, the low-jitter clock phase-locked loop chip U2 is connected with the FPGA chip U1, and the low-jitter clock phase-locked loop chip U2 is connected with the crystal oscillator U5 or the external reference clock input interface U6; the low-jitter clock phase-locked loop chip U2 is connected to the FPGA chip U1; the clock fan-out chip U3 is connected to the low-jitter clock phase-locked loop chip U2; the high-speed driving chip U4 is connected to the clock fan-out chip U3, the high-speed driving chip U4 is connected to the FPGA chip U1, and the high-speed driving chip U4 is connected to the digital pulse signal output interface U7. The circuit has the advantages of extremely low output signal jitter, excellent time sequence margin and reliability, high flexibility and expandability, capability of supporting internal and external clock reference and wide application scene.

The invention discloses a high-precision low-jitter clock recovery method, relates to the field of digital signal processing, and solves the problem of inaccuracy during clock jitter deviation recovery. Preprocessing the original clock signal and generating a corresponding square wave diagram based on the preprocessed processing clock signal; the clock fluctuation period of the processing clock signal is analyzed based on the square wave diagram, and the existence condition of the jitter deviation corresponding to the processing clock signal is judged; calculating the clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period in combination with the square wave diagram; inputting a processing clock signal into the ultrafast clock fan-out buffer, and performing comprehensive jitter recovery on the clock jitter deviation of the clock fluctuation period; and calculating the proportion of the processing clock signal output by the ultrafast clock fan-out buffer, and judging the validity of the ultrafast clock fan-out buffer. The method and the device provided by the invention realize accurate identification and recovery of the clock jitter deviation.

The utility model discloses E1 interface equipment for connecting PCM (Pulse Code Modulation) equipment and signaling conversion equipment, which belongs to the technical field of telecommunication and comprises an E1 interface A, an E1 interface B, an E1 interface C, an E1 interface D, an E1 transceiver A, an E1 transceiver B, an E1 transceiver C, an E1 transceiver D, an FPGA (Field Programmable Gate Array) controller A, an FPGA controller B, a DPS chip A, a DPS chip B, a clock synchronization circuit, a 232 communication module, a communication interface, a power supply circuit and a 12V power supply interface. By adopting the FPGA / DSP cooperative low-jitter clock buffer and isolation protection circuit, precise clock synchronization of multiple paths of E1 signals is realized, the technical problems of clock drifting and hardware processing capability bottleneck in a traditional system are effectively solved, task separation and efficient cooperation can be realized, a consistent and low-jitter reference clock is provided, and the reliability of the system is improved. The method has obvious advantages in clock synchronization, data processing and module division.

This invention relates to a data acquisition system based on an ADC chip for use in power detection equipment. The system includes a data acquisition circuit that acquires voltage and current traveling wave signals, performs signal conditioning, impedance matching, and differential drive processing; an ADC chip that performs analog-to-digital conversion on the signals output from the data acquisition circuit; an FPGA chip that receives digital signals, performs buffering, processing, and digital filtering operations, extracts the characteristics of power frequency signals and traveling wave signals in the power system, and performs data synchronization processing; and a CNV processing circuit that performs synchronization processing and edge shaping on the system master clock signal, outputting a synchronization signal to the FPGA to keep the sampling timing of the ADC chip synchronized with the system master clock. This invention converts the system master clock and drives the ADC sampling trigger path, achieving system-wide clock unification. After buffering and trigger shaping, the CNV signal has sharp edges and low jitter, suitable for high-speed ADC sampling. During long-term operation, the sampling points will not drift relative to the system clock, facilitating multi-module data alignment and synchronization processing.

The invention discloses a high-precision handle interaction method based on adaptive filtering and deep learning, and aims to solve the problems of jitter, delay and insufficient target selection precision of existing handle interaction. The method comprises the following steps: unifying handle original position input through coordinate transformation; one Euro filtering is adopted, the cut-off frequency is dynamically adjusted based on the handle speed, and low-speed shake resistance and high-speed hand following are achieved; learning historical position and speed features by using an LSTM model, and predicting a future trajectory to compensate system delay; dynamically fusing the current smooth position and the predicted position according to the current speed; the user intention is judged through the continuous frame distance, and precise target selection is achieved in combination with magnetic attraction locking. The method does not need extra hardware, considers low jitter, low delay and high precision, is suitable for scenes such as VR / AR and a virtual sand table, and significantly improves the interaction stability and accuracy.

The invention discloses an anti-radiation low-jitter phase-locked loop based on double-loop redundancy switching, belongs to the field of clock generation, and aims to solve the problems that an existing phase-locked loop is not provided with anti-radiation design, the reliability of a single-loop architecture is insufficient, and the jitter suppression capability in an irradiation environment is poor. The system comprises a main phase-locked loop, a standby phase-locked loop, a redundancy switching control module, an anti-radiation reinforcing unit and a low-jitter optimization module, wherein the main phase-locked loop and the standby phase-locked loop are consistent in structure and are optimized based on an automatic calibration architecture. The anti-radiation reinforcing unit is integrated on the core device, and the anti-radiation capability is improved through a specific structure, layout optimization and a redundant transistor; the redundancy switching control module monitors the double-loop state and the radiation condition in real time, fault seamless switching is achieved, and a fault loop can be self-repaired; the low jitter optimization module suppresses jitter through noise cancellation and adaptive damping. The functions of radiation resistance, redundant backup and low jitter are integrally realized, the stability and high precision of clock signals are ensured, and the method is suitable for aerospace, nuclear industry and other scenes.

The invention discloses a dynamic link control system and method based on positioning and motion trend analysis, and belongs to the technical field of link control, and the method specifically comprises the steps: obtaining the dynamic state information of a kart, and obtaining the dynamic state information of the kart based on the preset geometric constraint information of a racing track and the current state change rate of the kart; direction offset calculation, curvature change judgment and boundary proximity judgment are carried out on the dynamic state information, a trend indication quantity is generated, the trend indication quantity is mapped to a link coverage structure of a UWB base station, the interference level, the blocking probability and the time delay change trend of a corresponding link are calculated according to the area where the kart drives in, and the dynamic state information of the kart is obtained. Forming a link quality estimation result, and regulating and controlling channel allocation, communication power and a priority communication path between the kart and the UWB base station according to the link quality estimation result; according to the invention, the method achieves the sequential management of link resources in a multi-base-station coverage environment, and enables a kart to maintain a continuous and low-jitter communication link in a high-speed driving process.

Embodiments of the present disclosure provide a TSN resource scheduling system, method, device, medium and product, relating to the technical field of communication devices, to solve the problem that a general resource scheduling method cannot guarantee low delay and low jitter of TSN. The TSN resource scheduling system comprises a TSN controller and a plurality of network nodes; the plurality of network nodes comprise a start node and a destination node; the start node and the destination node are configured with a TSN configuration agent (TCB) client; the TCB client is configured to collect service requirement information of a node to which the TCB client belongs, and send the service requirement information to the TSN controller; and the TSN controller is configured to perform resource scheduling according to the service requirement information.

The invention discloses a scheduling adaptation method for an industrial PON and an industrial Ethernet, and the method comprises the steps: constructing a protocol-optical resource mapping semantic model, abstracting the communication demands of different industrial Ethernet protocols into a unified data structure containing a time-sensitive service level, a flow feature and a communication period parameter, mapping to generate corresponding scheduling demand parameters required by the industrial PON management platform; target traffic is sensed in real time based on a port mirroring technology, protocol identification is carried out by using a protocol-optical resource mapping semantic model, the bandwidth demand and transmission time sequence characteristics of industrial Ethernet service flow are further analyzed, the analyzed bandwidth demand and transmission time sequence characteristics are mapped into scheduling demand parameters of an industrial PON, and the scheduling demand parameters of the industrial PON are mapped to the target traffic. And the industrial PON management platform generates and issues a deterministic scheduling instruction based on the received scheduling demand parameters, so that deterministic transmission service is realized. According to the invention, low-delay, low-jitter and high-reliability transmission service can be provided for the multi-protocol industrial equipment.

The invention relates to the technical field of communication, and discloses a clock synchronization network and method, an FPGA chip and a clock synchronization network, the clock synchronization network comprises a clock processing module and a routing module, the clock processing module is in bidirectional communication connection with the routing module, and the clock processing module is used for generating a receiving clock signal based on a reference clock signal; adjusting the reference clock signal based on the adjusting clock signal to obtain a sending clock signal; the routing module is used for sending the receiving clock signal and the sending clock signal to each communication channel; and a receiving clock signal of any communication channel is used as an adjusting clock signal and is sent to the clock processing module, so that the clock in the sending direction follows the clock in the receiving direction, and the core advantages of low time delay and low jitter of the synchronous network are ensured.

The invention discloses a high-speed multi-channel low-jitter USB device capable of being used for infrared circuit clock configuration, the device comprises a shell, a USB socket is fixedly assembled on one side of the shell, a frequency adjusting and distributing unit is arranged in the shell, a programmable clock in the frequency adjusting and distributing unit is electrically connected with a microcontroller, and the microcontroller is electrically connected with the USB socket. The clock buffer is electrically connected with the programmable clock, the clock buffer is used for receiving a clock signal of the programmable clock and distributing the clock signal into six pairs of differential clocks, through the programmable clock chip and a precision algorithm, the 1Hz precision linear continuous adjustment of the output frequency within the range of 10 MHz to 810 MHz is realized, and meanwhile, the output frequency of the programmable clock chip is greatly improved. The integrated clock buffer can synchronously distribute one path of high-quality clock into six pairs of differential signals to ensure that the multi-channel infrared imaging system obtains synchronous low-jitter clock input.

The invention provides a multi-order pseudo-random sequence generation circuit, which can complete undisturbed switching among a first-order random code generator, a second-order random code generator and a third-order random code generator by configuring a control signal, and caches a rising edge sequence and a falling edge sequence of corresponding orders to a third memory and a fourth memory respectively to ensure that subsequent output is synchronous and burr-free. The output switching of the corresponding-order random code generator triggered by the rising edge sequence and the falling edge can be realized by taking the hour hand signal as a reference, the double-edge double-sequence output is realized in one clock period, and systems with different time sequence requirements are adapted; and the time sequence alignment of the first-order clock period delay, the second-order clock period delay and the third-order clock period delay is automatically completed through the series difference of the registers, and finally a continuous, configurable and low-jitter feedback pseudo-random code stream is formed.

To make it possible to reduce jitter while suppressing an increase in circuit size of a phase-locked circuit. A phase-locked circuit includes a sample hold circuit configured to sub-sample an input signal, on the basis of a reference signal, a voltage-to-time converter configured to convert a voltage of the input signal sub-sampled by the sample hold circuit into a time difference, and a time-to-digital converter configured to detect the time difference converted by the voltage-to-time converter. The sample hold circuit, the voltage-to-time converter, and the time-to-digital converter may constitute a time domain ADC. The phase-locked circuit may further include a digitally-controlled oscillator configured to generate the input signal.

The invention relates to the technical field of network communication, and discloses a deterministic forwarding processing method and device based on an IPv4 network, and the method comprises the steps that a controller issues service flow information to a head node, and the head node matches a corresponding service flow according to a service flow feature strategy in the service flow information, inserting a corresponding outer layer IPv4 header, a segment routing header field SRH and a segment routing operation field SR-OPT in front of an original IPv4 header for the service flow, and performing packaging to obtain a message; the head node carries out deterministic forwarding processing on the message according to a deterministic processing method parameter table DNET and an outer layer IPv4 head destination address in the message; and if the transmission path from the sending end to the receiving end is not congested and has no link fault, judging whether nodes except the head node on the transmission path from the sending end to the receiving end support deterministic forwarding or not. According to the application, the determined low-delay, low-jitter and high-reliability service guarantee capability can be realized.

The present disclosure provides a transaction data processing method and device, an electronic device and a storage medium. The method comprises: acquiring market quotations of a power spot market, bidding strategies of a plurality of users and an execution return in a previous period in a current period; performing priority ranking on the users based on the strategies and the market quotations to obtain a ranked user sequence; acquiring target orders of the users based on a reference price determined by the market quotations and the strategies, a price change step in the strategies, a transaction power and the user sequence; performing comparison processing on the target orders and orders that have been hung based on the execution return to obtain a comparison result; and generating an order execution operation in the current period based on the comparison result, the target orders and the orders that have been hung. The method can realize aggregation in a period and account-level concurrent control, so that stable throughput and low jitter can be maintained under multiple parallel users, thereby improving high-concurrent stability in the transaction data processing process.

The invention discloses an adaptive load balancing WebSocket service system and method, and relates to the technical field of computer network communication, and the method comprises the steps: collecting the operation load data of a WebSocket node in real time, predicting the future load trend through a load prediction model, and generating an expected report of the future load of the WebSocket node; the load distribution state information of the WebSocket node and the cluster is dynamically evaluated, the load abnormity and the recovery state of the WebSocket node are identified, and a load operation state record is generated; health assessment and load analysis are carried out according to the load operation state record, and global load balance state information is generated. By executing the cross-cluster migration operation, the self-adaptive load balancing effect with high availability, high stability and low jitter is finally achieved.

This invention discloses an image processing circuit for autonomous vehicles, belonging to the field of image processing technology. It solves the problems of unexpected refraction and scattering of light due to physical defects in optical microlenses and color filters, and charge coupling caused by parasitic capacitance in pixel units, leading to leakage of optical / electrical signals from a single pixel to adjacent pixels, resulting in color aliasing and blurred image edges. The circuit includes a main image sensor module, a reference image sensor module, and an analog signal preprocessing and multiplexing module. This invention coordinates the synchronous signal acquisition of the main and reference image sensors through a low-jitter clock distribution module. After integration by the analog signal preprocessing module, a dynamic crosstalk compensation module generates an inverse compensation signal based on the reference signal. A high-precision differential correlation dual sampling module then performs noise suppression and crosstalk elimination on the main signal. Finally, a programmable gain amplifier module outputs the purified differential signal.

The invention relates to the technical field of rail transit communication, provides a rail transit vehicle deterministic communication and control network architecture based on a time-sensitive network, and provides a train network deterministic data transmission scheduling control method based on the architecture. Then establishing a system model, constructing a TSN traffic scheduling problem constraint, ensuring that the end-to-end delay is less than the maximum delay requirement, and formulating a forwarding strategy of all scheduling traffic in the network on the basis of meeting jitter and delay; and an application verification scheme example and a mapping scheme of a data category and a time-sensitive network priority in the train communication network are given. According to the method, low-time-delay low-jitter high-reliability transmission of train time-sensitive flow is ensured, the real-time performance and reliability of train communication network data transmission are remarkably improved, and the method is particularly suitable for scenes such as high-speed railways and urban rail transit which have extremely high requirements on the real-time performance and reliability of data transmission.

The application belongs to the technical field of digital-analog hybrid integrated circuit design, and specifically discloses a low-jitter sub-sampling phase-locked loop based on a discrete-time elimination technology, which comprises a sub-sampling phase-locked loop, a pulse generator and a discrete-time phase noise elimination path; wherein the discrete-time phase noise elimination path comprises a process, voltage and temperature tracking biasing device, a second sub-sampling phase detector, a direct current compensator and a level shifter; the application extracts output noise at the second sub-sampling phase detector and eliminates compensation before a ring oscillator, thereby significantly suppressing the phase noise of the sub-sampling phase-locked loop, and simultaneously adopting adaptive gain mismatch adjustment to ensure that the phase noise elimination maintains the best effect in process, voltage and temperature changes, compared with a traditional phase-locked loop based on a noise elimination module, the application eliminates the limitation on working frequency and power consumption, and avoids complex calibration.