120 results about "Low jitter" patented technology

The invention relates to the technical field of time synchronization, and discloses a hybrid time service method based on Beidou satellite navigation and a TSN, which comprises the following steps: acquiring network topology structure information and historical time service error data of each synchronization node in a target distributed system, and constructing a dynamic time delay state set for jitter identification; based on the dynamic time delay state set, a current global time reference is extracted through a time calibration algorithm, a time difference reference vector sequence is generated, and initial synchronization adjustment is carried out on the TSN main node; constructing an inter-node clock convergence function curve according to the slave node response stability, and judging whether the synchronous network is in a low jitter interval or not based on the time offset rate and the time drift trend change; in combination with the node time state after directional offset suppression, a multi-channel redundant time synchronization mechanism in a time window is applied, a weight adjustment coefficient is extracted, and an unbalanced calibration factor is introduced; and according to a regression correction result, evaluating a time service stability index in real time. The method has the advantage of improving the time service stability.

The invention relates to the technical field of satellite communication networks and on-board buses, in particular to a data deterministic transmission scheduling method for a satellite-borne time-sensitive network. The method comprises the following steps: constructing a satellite-borne network architecture, connecting each terminal and a bus gateway by a TSN management node to form a unified data bus, distributing priority and monitoring link state; performing feature modeling on the data frames to define six-tuple parameters; designing a hierarchical queue architecture comprising a key task queue, a load data queue and a background traffic queue; a dynamic shaping mechanism is adopted, corresponding shaping devices are arranged for different queues, and parameters are set; the invention further provides an anti-disturbance scheduling strategy which comprises dynamic priority improvement and elastic bandwidth allocation. And finally, performing output scheduling according to a strict priority and a weighted fair queue rule. According to the method, by constructing a unified TSN bus and integrating heterogeneous subsystems, low-delay and low-jitter transmission of key task data is realized, the bandwidth utilization rate of scientific load data is improved, the network reconstruction time is shortened, the anti-interference capability is enhanced, and satellite-borne mixed data stream transmission in a high-dynamic and multi-task scene is effectively optimized.

The invention discloses a method and a device for outputting large-energy picosecond pulse laser with external synchronization picosecond-level jitter. The device comprises a high-precision time sequence controller, a semiconductor picosecond pulse seed source, an optical isolator and a high-gain and high-stability regenerative amplifier. The semiconductor picosecond pulse seed source outputs low-energy picosecond-level (10-12J, pJ) and low-jitter picosecond-level (10-12s, ps) picosecond pulse seeds under the trigger of a time sequence controller of a high-precision external clock, the picosecond pulse seeds enter the high-gain high-stability regenerative amplifier through the optical isolator, and the high-gain high-stability regenerative amplifier outputs high-energy picosecond-level (10-12s, ps) picosecond pulse seeds under the control and adjustment of the high-precision time sequence controller. The picosecond pulse seed is locked to be regenerated and amplified in the regenerative amplifier, and the energy of the picosecond pulse seed with low energy and low jitter at a picofocus (pJ) level is amplified to uJ-mJ (10 <-6 > J-10 <-3 > J), so that low jitter and large energy output of laser pulses and trigger signals are realized, and application development of high-precision laser ranging, laser communication, time-frequency transmission and the like is effectively promoted.

The invention discloses a fast-locking low-jitter sub-sampling phase-locked loop structure. The sub-sampling phase-locked loop comprises a sub-sampling Bang-Bang phase discrimination circuit, a self-adaptive variable step size digital filter circuit, a delta sigma digital-to-analog conversion circuit and an oscillator circuit. The sub-sampling Bang-Bang phase discrimination circuit generates a phase discrimination output digital control signal according to an input reference signal and a feedback oscillator signal phase error, the adaptive variable step size digital filter circuit adaptively adjusts a filtering gain according to the phase discrimination output digital control signal, and the output of the filter circuit realizes digital-analog conversion after oversampling modulation. And the output analog signal controls the voltage-controlled oscillator to realize rapid low-jitter phase locking of the output and the reference signal.

A phase alignment circuit aligns a phase of an output signal with a phase of an input clock signal. The circuit operates in phase alignment modes comprising two or more of: a single step alignment mode; a multiple step alignment mode; and a random or pseudo-random step alignment mode. In an embodiment, the circuit receives an input clock signal Clk-in and a low jitter reference clock Ref-clk, and generates in block 220 a clock signal Clk-out having the same frequency as the input clock but with the low jitter of signal Ref-clk. Circuit block 260 outputs a clock signal B-clk and a frame synchronisation pulse Fsync. The circuit maintains phase alignment between the input clock and the output frame synchronisation signal. Phase alignment is achieved by extending one or more cycles of the B-clk signal to achieve a constant number of B-clk cycles per frame synchronisation output signal Fsync.

The invention provides a transaction data processing method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring the market information of an electric power spot market in a current period, declaration strategies of a plurality of users and execution return in a previous period; performing priority ranking on the users based on the strategy and the market information to obtain a ranked user sequence; obtaining a target order of the user based on a standard price determined by the market information and the strategy, a price change step length and a transaction electric quantity in the strategy and the user sequence; carrying out comparison processing on the target order and the hung order executing the return to obtain a comparison result; and generating an order execution operation in the current period based on the comparison result, the target order and the hung order. According to the method, aggregation and account-level concurrency control in a period can be realized, so that stable throughput and low jitter can be kept under multiple parallel users, and high concurrency stability in a transaction data processing process is improved.

A circuit and method are described for generating a low jitter output clock having an arbitrary non-integer divide ratio relative to a high-frequency clock. Integer divide ratios of the high-frequency clock may be achieved by dividing the high-frequency clock by the reference clock and phase locking the output clock to the high-frequency clock. Non-integer divide ratios can be achieved by dividing the high-frequency clock by the nearest integer, rounded down, and then delaying the resultant output clock by the modulus of the division. The delay can then be rotated across to create a clock with a non-integer divide ratio relative to the high-frequency clock. By doing so, a high-frequency clock may be used that is not constrained by having a frequency that is an integer multiple of each desired component-specific output clock signal.

The present invention discloses a CSS-PD (Charge-Steering-Sampling Phase Discriminator), a DLF (Digital Loop Filter) and a CSS-ADPLL (Charge-Steering-Sampling All Digital Phase-Locked Loop) thereof The CSS-PD includes a Frac-N C-DAC, a CSS, and a SAR-ADC. The CSS-PD has a controlling method including four steps: (1) charge presetting; (2) charge-steering sampling; (3) fractional charge compensating; (4) digitalizing. Wherein when ΔVerr,pn sampled by the CSS included two errors ΔVerr,pn and ΔVerr,frac, ΔVerr,frac had fractional charge compensating by setting part of the capacitors of the Cfrac of the Frac-N C-DAC to a Vref,adc. Vref,adc was satisfied the following formula: ΔVerr,frac=Dfrac·Cunit / (Cfrac+Csar)·Vref,adc. Cunit is for capacitance of Cfrac, Cfrac is also for capacitance of Cfrac, Csar is also for capacitance of Csar of the SAR-ADC, Dfrac is the output signal of the Frac-N C-DAC. A CSS-ADPLL with the CSS-PD can obtain the performance of low jitter, low fractional division spurious and low reference spurious at the same time.

The invention discloses a power supply control method and system based on a real-time slope adjustment algorithm, and the method comprises the steps: monitoring the load impedance characteristics of a power supply and environment noise data in real time, and obtaining an independent control time slice set; obtaining a time sequence identifier of the control time slice set, and obtaining a dynamic mode parameter packet bound with the current load characteristic; obtaining a real-time voltage / current regulation instruction set with a feed-forward compensation coefficient according to the dynamic mode parameter packet and the error tolerance data; analyzing the real-time voltage / current regulation instruction set, and combining the historical working condition similarity data to obtain an optimized PID coefficient matrix and a feed-forward gain vector; and executing the optimized PID coefficient matrix and the feed-forward gain vector, and generating and outputting a four-dimensional space trajectory signal which is completely matched with the target slope trajectory as a direct driving reference of a power supply power device. According to the embodiment of the invention, high-precision and low-jitter real-time slope tracking control can be realized, and the dynamic response speed and anti-interference robustness of a power supply system are improved.

The invention belongs to the technical field of laser precision machining and control, and particularly relates to a femtosecond laser single-point trigger control system and method based on subnanosecond synchronization, and the method comprises the following steps: S1, building a system synchronization clock locked with a femtosecond laser pulse signal phase; the specific mode of establishing the system synchronous clock is that phase locking is carried out on pulse synchronous signals or frequency division signals output by an internal high-frequency clock source and a femtosecond laser source through a digital phase-locked loop technology, and the low-jitter system synchronous clock which is strictly synchronous with a laser pulse sequence is generated. According to the invention, a system clock locked with a laser pulse phase can be generated through a digital phase-locked loop, and the influence of inherent frequency drift of a laser and circuit delay temperature drift is effectively overcome by combining real-time delay calculation based on a prediction algorithm and a high-resolution DDS delay line technology; the synchronization precision between the triggering moment of the single pulse and the external instruction is stabilized at the subnanosecond level, and the requirement of leading-edge application for the extreme time sequence precision is met.

The application relates to the technical field of time synchronization, and discloses a mixed time service method based on Beidou satellite navigation and TSN, which comprises the following steps: acquiring network topology structure information and historical time service error data of each synchronization node in a target distributed system, and constructing a dynamic time delay state set for jitter identification; based on the dynamic time delay state set, a current global time reference is extracted through a time calibration algorithm, a time difference reference vector sequence is generated, and initial synchronization adjustment is carried out on a TSN master node; according to the response stability of a slave node, a clock convergence function curve between nodes is constructed, whether the synchronization network is in a low jitter interval is judged based on time offset rate and time drift trend change; in combination with the node time state after directional offset suppression, a multi-channel redundant time adjustment mechanism in a time window is applied, a weight adjustment coefficient is extracted, and a non-uniform calibration factor is introduced; and according to a regression correction result, a time service stability index is evaluated in real time. The application has the advantages of improving time service stability.

The invention relates to the technical field of radio frequency integrated circuits, and particularly provides a low-jitter injection locking phase-locked loop based on multiphase injection, which comprises an injection locking path unit, a locking unit and an injection locking ring oscillator, the injection locking path unit can generate a multi-phase injection signal and a complementary injection signal according to the received reference signal; the injection locking ring oscillator receives the multi-phase injection signal and the complementary injection signal and then generates an oscillation signal; and then the locking unit locks the injection locking phase-locked loop according to the generated oscillation signal. According to the invention, the injection locking path unit generates the multi-phase injection signal and the complementary injection signal, so that the injection locking ring oscillator is subjected to multi-phase direct injection and cross coupling complementary injection, and the multi-phase direct injection can reduce the jitter of the phase-locked loop based on the ring oscillator. And phase deviation generated by multi-phase direct injection is eliminated through cross coupling complementary injection, so that the injection intensity is further improved, and the noise suppression bandwidth is effectively expanded.

The invention provides a high-precision low-jitter waveform generation method and device based on an FPGA, and relates to the technical field of signal processing. According to the phase accumulated value obtained through preprocessing, calculation is carried out according to a preset mathematical model, and a model output value is determined; performing phase comparison according to the phase accumulated value, and performing waveform selection in combination with a model output value to obtain an initial output waveform; according to the phase accumulated value, generating a sine wave through a preset CORDIC IP; according to the initial output waveform and the sine wave, waveform selection is carried out, and a secondary output waveform is determined; and performing digital-to-analog conversion according to the secondary output waveform and a preset reference clock signal, and outputting a final waveform. By combining the high-precision characteristic of DDS frequency control and the flexibility of edge interpolation, low-jitter pulse waves with adjustable parameters such as edge time, pulse width, duty ratio and degree of symmetry are generated; advantages of linear interpolation and nonlinear interpolation are integrated, and edge jitter of pulse signals is effectively reduced.

The invention provides a three-dimensional stacked packaging substrate device and a manufacturing method, and relates to the technical field of semiconductor packaging, and the three-dimensional stacked packaging substrate device comprises a substrate which is a multi-layer stacked substrate; a drop point area corresponding to the vertical interconnection terminal is provided with a backflow channel, and the backflow channel comprises a grounding via hole array or a grounding metal ring surrounding the drop point area and is used for providing a continuous reference loop for a high-speed signal transmitted through the vertical interconnection terminal. Providing a core plate, carrying out multi-layer lamination, and manufacturing a backflow channel in a corresponding vertical interconnection terminal drop point area; manufacturing blind holes or micro holes in the substrate to realize interlayer interconnection; the substrate is divided into a high-speed digital area, an analog / radio frequency area and a power supply area according to functions for partition wiring, and the ground plane of each partition is kept continuous; a decoupling device is arranged at the near end of the vertical interconnection drop point or the chip power supply inlet. The system has the beneficial effects that low reflection, low jitter and low bit error rate of high-speed signal transmission are realized, and the electromagnetic compatibility and the working reliability of the system are improved.

Embodiments of the present disclosure disclose a key point identification method and device, electronic equipment and storage medium, wherein the method comprises: inputting a target video frame into a preset model, outputting at least three predicted positions of each key point in the target video frame based on the preset model; determining candidate regions of the key points in the target video frame according to the at least three predicted positions of the key points; and determining the final position of the corresponding key point in the target video frame from each candidate region according to the final position of the key point in the adjacent frame earlier than the target video frame in time sequence. Without manual adjustment of parameters, the method can significantly reduce jitter and ensure the accuracy of key point prediction.

An anti-radiation Serdes transceiver CDR circuit based on phase interpolation abandons the traditional CDR circuit completely based on the PLL structure, and uses a data and edge dual high-speed sampler, an anti-radiation CDR state machine, a high-precision phase interpolator and a general PLL based on an LC oscillator to recover high-speed data and clocks of 0.5 to 12.5 Gbps, achieving strong loop stability, single-event radiation resistance, short phase capture time, high linearity and low jitter of the CDR.

The present application relates to electronic endoscope technical field, specifically, it relates to a kind of endoscope multiplexing line built-in MIPI-CSI signal long-distance transmission isolation enhancement device.It includes the control end module, receiving end module and power management unit integrated in multiplexing line, and power management unit is used to power control end module, receiving end module.Power management unit in the present application, by the high integration of control end module, receiving end module and power management unit in multiplexing line, signal conditioning and isolation enhancement unit of control end can effectively process original signal and inhibit common-mode interference, then with the equalization compensation and clock data recovery circuit of receiving end repair signal attenuation and timing distortion problem caused by long-distance transmission, to realize in complex electromagnetic environment still can stable output low jitter, high integrity video signal, fundamentally solve the problem of affecting diagnostic accuracy due to image delay, quality decline.

This invention relates to the field of phase-locked loop (PLL) technology, specifically to a method for achieving low jitter over a wide locking range by optimizing the PLL structure. The method includes: outputting a first error signal through a phase detector, obtaining the characteristics of the first error signal, and constructing a first error signal function; obtaining a first adaptive loop bandwidth; constructing a multi-band voltage-controlled oscillator (VCO) matching mechanism, including VCOs in multiple frequency bands; during PLL locking, selecting a frequency band based on the input signal frequency and the center frequency band of the VCO to obtain a first matching frequency band; and calculating the root mean square (RMS) of the first error signal based on further analysis of the first error signal characteristics, and combining the initial feedback gain and the initial error signal RMS to obtain a first feedback gain adjustment value. This invention achieves low jitter over a wide locking range through adaptive loop bandwidth adjustment, a multi-band VCO matching mechanism, and adaptive feedback gain adjustment.

This application relates to real-time high-speed clock signals for industrial network simulation. An industrial simulation system exchanges data between a virtualized industrial system and an industrial controller at high frequency and high accuracy without requiring additional network simulation hardware. Rather than using an operating system clock to time the sending of simulation device data packets from the simulation system to the industrial controller, the simulation system uses the arrival event of a data packet received from the industrial controller as a driving clock signal for sending data packets from the virtual system to the controller. Using the arrival time of a data packet from the industrial controller as a clock signal rather than the operating system's system clock can produce high-accuracy, low-jitter data exchange during simulation.

The invention provides an FPGA-based programmable periodic pulse signal generation method and application thereof, and belongs to the technical field of electronic measurement. In order to solve the problems that the large dynamic range and the high resolution are difficult to consider at the same time and hardware resources are consumed synchronously by multiple channels in the prior art, according to the method, coarse delay is achieved through FPGA system clock counting, and next pulse parameters are calculated through accumulation of remaining decimal parts; picosecond-level fine delay is realized by constructing a three-level cascade architecture consisting of a lookup table, a coarse carry chain and a fine carry chain; and XOR synthesis waveforms after rising edges and falling edges are independently generated respectively. In addition, the inter-channel transmission delay difference is compensated by correcting the initial calculation parameters. According to the multi-channel pulse signal generation circuit, high-precision, low-jitter and strictly-aligned-phase multi-channel pulse signals can be generated only by utilizing pure logic resources of the FPGA.

The invention provides a low-jitter pulse signal generation circuit, which relates to the technical field of synchronous control signals and comprises an FPGA (Field Programmable Gate Array) chip U1 and a low-jitter clock phase-locked loop chip U2, the low-jitter clock phase-locked loop chip U2 is connected with the FPGA chip U1, and the low-jitter clock phase-locked loop chip U2 is connected with the crystal oscillator U5 or the external reference clock input interface U6; the low-jitter clock phase-locked loop chip U2 is connected to the FPGA chip U1; the clock fan-out chip U3 is connected to the low-jitter clock phase-locked loop chip U2; the high-speed driving chip U4 is connected to the clock fan-out chip U3, the high-speed driving chip U4 is connected to the FPGA chip U1, and the high-speed driving chip U4 is connected to the digital pulse signal output interface U7. The circuit has the advantages of extremely low output signal jitter, excellent time sequence margin and reliability, high flexibility and expandability, capability of supporting internal and external clock reference and wide application scene.

The present invention discloses a monitoring and anti-theft system for a vending machine, comprising: a vibration monitoring module, configured to monitor the vibration energy of a vending machine body included in the vending machine, and generate a video acquisition instruction and send it to a video acquisition module when it is determined that the vibration energy is greater than a vibration energy threshold; the video acquisition module, configured to acquire a monitoring video within a preset range of the vending machine body and perform preprocessing to obtain a target video when receiving the video acquisition instruction, and send the target video to a transmission module; the transmission module, configured to send the target video to an alarm platform. Through the monitoring and anti-theft system for a vending machine provided by the present invention, it is possible to effectively collect a clear monitoring video with extremely low jitter degree and send it to the alarm platform when the vending machine vibrates with too strong energy due to being damaged and impacted, which helps the staff quickly determine the theft situation of the damaged vending machine and lock down the lawbreakers.

The invention discloses a high-precision low-jitter clock recovery method, relates to the field of digital signal processing, and solves the problem of inaccuracy during clock jitter deviation recovery. Preprocessing the original clock signal and generating a corresponding square wave diagram based on the preprocessed processing clock signal; the clock fluctuation period of the processing clock signal is analyzed based on the square wave diagram, and the existence condition of the jitter deviation corresponding to the processing clock signal is judged; calculating the clock jitter deviation of the processing clock signal in the corresponding clock fluctuation period in combination with the square wave diagram; inputting a processing clock signal into the ultrafast clock fan-out buffer, and performing comprehensive jitter recovery on the clock jitter deviation of the clock fluctuation period; and calculating the proportion of the processing clock signal output by the ultrafast clock fan-out buffer, and judging the validity of the ultrafast clock fan-out buffer. The method and the device provided by the invention realize accurate identification and recovery of the clock jitter deviation.

A charge-pump based low dropout (LDO) regulator is provided that overcomes latch-up issues. The LDO regulator is a high PSR low noise LDO regulator that uses a latch-up mitigated charge-pump voltage doubler which includes a N-type metal-oxide-semiconductor field-effect transistor (MOSFET), NMOS, pass transistor. This LDO regulator architecture may be used to provide a very low-noise supply regulated output voltage with high power supply rejection for an on-chip low jitter oscillator. Latch-up is mitigated using control circuitry and a power supply timing sequence. This scheme ensures that parasitic diodes associated with various transistors in the regulator are not forward biased.

The utility model discloses E1 interface equipment for connecting PCM (Pulse Code Modulation) equipment and signaling conversion equipment, which belongs to the technical field of telecommunication and comprises an E1 interface A, an E1 interface B, an E1 interface C, an E1 interface D, an E1 transceiver A, an E1 transceiver B, an E1 transceiver C, an E1 transceiver D, an FPGA (Field Programmable Gate Array) controller A, an FPGA controller B, a DPS chip A, a DPS chip B, a clock synchronization circuit, a 232 communication module, a communication interface, a power supply circuit and a 12V power supply interface. By adopting the FPGA / DSP cooperative low-jitter clock buffer and isolation protection circuit, precise clock synchronization of multiple paths of E1 signals is realized, the technical problems of clock drifting and hardware processing capability bottleneck in a traditional system are effectively solved, task separation and efficient cooperation can be realized, a consistent and low-jitter reference clock is provided, and the reliability of the system is improved. The method has obvious advantages in clock synchronization, data processing and module division.

This invention relates to a data acquisition system based on an ADC chip for use in power detection equipment. The system includes a data acquisition circuit that acquires voltage and current traveling wave signals, performs signal conditioning, impedance matching, and differential drive processing; an ADC chip that performs analog-to-digital conversion on the signals output from the data acquisition circuit; an FPGA chip that receives digital signals, performs buffering, processing, and digital filtering operations, extracts the characteristics of power frequency signals and traveling wave signals in the power system, and performs data synchronization processing; and a CNV processing circuit that performs synchronization processing and edge shaping on the system master clock signal, outputting a synchronization signal to the FPGA to keep the sampling timing of the ADC chip synchronized with the system master clock. This invention converts the system master clock and drives the ADC sampling trigger path, achieving system-wide clock unification. After buffering and trigger shaping, the CNV signal has sharp edges and low jitter, suitable for high-speed ADC sampling. During long-term operation, the sampling points will not drift relative to the system clock, facilitating multi-module data alignment and synchronization processing.

The invention discloses a high-precision handle interaction method based on adaptive filtering and deep learning, and aims to solve the problems of jitter, delay and insufficient target selection precision of existing handle interaction. The method comprises the following steps: unifying handle original position input through coordinate transformation; one Euro filtering is adopted, the cut-off frequency is dynamically adjusted based on the handle speed, and low-speed shake resistance and high-speed hand following are achieved; learning historical position and speed features by using an LSTM model, and predicting a future trajectory to compensate system delay; dynamically fusing the current smooth position and the predicted position according to the current speed; the user intention is judged through the continuous frame distance, and precise target selection is achieved in combination with magnetic attraction locking. The method does not need extra hardware, considers low jitter, low delay and high precision, is suitable for scenes such as VR / AR and a virtual sand table, and significantly improves the interaction stability and accuracy.

The invention relates to a laser-triggered multi-path high-voltage spark switch system which is composed of a laser-triggered spark main switch circuit and an electric-triggered spark sub-switch circuit. The laser trigger spark main switch can trigger the multiple electric trigger sub-switch circuits at the same time. The system can be applied to different environment conditions, especially research on synchronous triggering of multiple plasma guns in a magnetic inertial confinement fusion vacuum cavity, effectively solves the problem that a spark switch is triggered by laser in a special environment scene which is not suitable for spatial light path transmission, avoids triggering the spark switch by the laser through optical fiber transmission, and is high in reliability. The triggering system is simple, convenient to operate and low in cost; because laser trigger is used as a main switch to trigger a plurality of sub-switches, the laser trigger spark switch has the characteristics of small delay and low jitter, and the Rogowski coil has the characteristics of clean current signal acquisition and low noise.

The patent of the invention is based on a lightweight consensus networking technology. The invention discloses a lightweight consensus algorithm based on distributed network nodes, and aims to solve the problem of data consistency of each distributed node in a system. According to the algorithm, transmission data is organized through a reasonable data structure, and consensus data is stored by adopting a Merkle tree, so that the communication cost is greatly reduced; on the basis of acquiring whole network node information by initial consensus, a node with an optimal network topology structure (shortest path to a logic neighbor node) and optimal communication performance (high bandwidth, small delay and small jitter) is selected as an optimal main node, and topology resource information consensus is changed in advance through the optimal main node; and the optimal main nodes distribute the topological resource information to the logical neighbor nodes to efficiently synchronize the changed topological resource information of the whole network, so that the distributed node data consistency is quickly realized.

The invention discloses an anti-radiation low-jitter phase-locked loop based on double-loop redundancy switching, belongs to the field of clock generation, and aims to solve the problems that an existing phase-locked loop is not provided with anti-radiation design, the reliability of a single-loop architecture is insufficient, and the jitter suppression capability in an irradiation environment is poor. The system comprises a main phase-locked loop, a standby phase-locked loop, a redundancy switching control module, an anti-radiation reinforcing unit and a low-jitter optimization module, wherein the main phase-locked loop and the standby phase-locked loop are consistent in structure and are optimized based on an automatic calibration architecture. The anti-radiation reinforcing unit is integrated on the core device, and the anti-radiation capability is improved through a specific structure, layout optimization and a redundant transistor; the redundancy switching control module monitors the double-loop state and the radiation condition in real time, fault seamless switching is achieved, and a fault loop can be self-repaired; the low jitter optimization module suppresses jitter through noise cancellation and adaptive damping. The functions of radiation resistance, redundant backup and low jitter are integrally realized, the stability and high precision of clock signals are ensured, and the method is suitable for aerospace, nuclear industry and other scenes.