30 results about "Serial processor" patented technology

A method for scheduling cell transmissions through a switch with rate and delay guarantees and with low jitter is proposed. The method applies to a classic input-buffered N×N crossbar switch without speedup. The time axis is divided into frames each containing F time-slots. An N×N traffic rate matrix specifies a quantized guaranteed traffic rate from each input port to each output port. The traffic rate matrix is transformed into a permutation with NF elements which is decomposed into F permutations of N elements using a recursive and fair decomposition method. Each permutation is used to configure the crossbar switch for one time-slot within a frame of size F time-slots, and all F permutations result in a Frame Schedule. In the frame schedule, the expected Inter-Departure Time (IDT) between cells in a flow equals the Ideal IDT and the delay jitter is bounded and small. For fixed frame size F, an individual flow can often be scheduled in O(log N) steps, while a complete reconfiguration requires O(N log N) steps when implemented in a serial processor. An RSVP or Differentiated Services-like algorithm can be used to reserve bandwidth and buffer space in an IP-router, an ATM switch or MPLS switch during a connection setup phase, and the proposed method can be used to schedule traffic in each router or switch. Best-effort traffic can be scheduled using any existing dynamic scheduling algorithm to fill the remaining unused switch capacity within each Frame. The scheduling algorithm also supports multicast traffic.

Methods, systems, and products are disclosed for broadcasting collective operation contributions throughout a parallel computer. The parallel computer includes a plurality of compute nodes connected together through a data communications network. Each compute node has a plurality of processors for use in collective parallel operations on the parallel computer. Broadcasting collective operation contributions throughout a parallel computer according to embodiments of the present invention includes: transmitting, by each processor on each compute node, that processor's collective operation contribution to the other processors on that compute node using intra-node communications; and transmitting on a designated network link, by each processor on each compute node according to a serial processor transmission sequence, that processor's collective operation contribution to the other processors on the other compute nodes using inter-node communications.

A microprocessor architecture comprises a plurality of processing elements arranged in a single instruction multiple data SIMD array, wherein each processing element includes a plurality of execution units, each of which is operable to process an instruction of a particular instruction type, a serial processor which includes a plurality of execution units, each of which is operable to process an instruction of a particular instruction type, and an instruction controller operable to receive a plurality of instructions, and to distribute received instructions to the execution units in dependence upon the instruction types of the received instruction. The execution units of the serial processor are operable to process respective instructions in parallel.

The invention provides a switching circuit based on multiplexing of multiple-processor serial ports on a single board. The switching circuit is arranged on the single board and comprises at least two processors, one selector switch, one electrical level shifter, a control circuit for serial port switching and a panel serial port socket, wherein the panel serial port socket is respectively connected with the electrical level shifter and the control circuit for serial port switching, the electrical level shifter is respectively connected with the first processor and the second processor through the selector switch, and a signal controlling pin of the serial port switching circuit is connected with the selector switch. The invention further provides a switching method based on multiplexing of the multiple-processor serial ports on the single board. Thus, the serial ports of the processors can share one panel serial port socket, through plugging-in and plugging-out, the panel serial port socket can be connected to different processor serial ports, and panel space of the single board is saved.

The apparatus comprises: a control unit used for controlling the interpolation processing unit and generating the sample data, interpolation factor and control signal required by the interpolation processing unit; and an interpolation processing unit used for, under the control of the control unit, using the sample data, interpolation factor and control signal to make the multiply and summation calculation for the sample data, and transmitting the processed sample data to the control unit in order to output it.

The invention discloses a digital pre-distortion processing method adaptive to a quick-change signal. The digital pre-distortion processing method comprises the following steps of: storing one group of training signals in a concurrent processor, when a system is started, sending the training signals to a power amplifier by the concurrent processor, acquiring an input signal and an output signal of the power amplifier to be provided to a serial processor, calculating a filter coefficient of eliminating a memory effect, after the serial processor eliminates time delay, calculating a passband ripple of the system, calculating a coefficient of reversely correcting the filter, providing the coefficient to the concurrent processor for correcting the memory effect; after the system is started, continuously acquiring the input signal and the output signal of the power amplifier by the concurrent processor, updating and correcting a memoryless and nonlinear search table in real time after eliminating time delay and gain difference; and when the system normally works, carrying out memoryless and nonlinear correction on the input signal by the concurrent processor, eliminating the memory effect, and outputting the memory effect to an emitting link. The invention is suitable for the quick-changing modern communication signal, and has the advantages of reducing out-of-band leakage and increasing frequency spectrum utilization rate and system capacity.

The invention provides a multi-channel digital audio signal real-time sound effect processing method and system, comprising: a host computer sends filter parameters, gain parameters and delay parameters to a parallel processor; the parallel processor receives the filter parameters and gain parameters And the audio signal to be processed is sent to the serial processor; the serial processor calculates and obtains the filter coefficient and gain adjustment coefficient according to the received filter parameter and gain parameter and the audio signal to be processed and sends it to the parallel processor; parallel processing The filter performs time domain filtering, gain adjustment and delay processing on the audio signal to be processed according to the received filter coefficients, gain adjustment coefficients and delay parameters. The present invention uses serial architecture processors and parallel architecture processors to jointly process sound effect data, reduces the delay in the sound effect processing process, realizes parallel processing of multi-channel audio data, and makes the sound effect processing have higher real-time performance.

It is a metal probe in lossless electromagnetism measurement technique field. The digital signal processor generates two paths of signals through two direct digital systemization chips into two multipliers that get two paths of separation signals through two low-pass filters. The data through the A / D conversion is sent to the digital signal processor for analysis and judgments. The human and machine dialogue system comprises single machines communicated with digital signal serial processors.

The invention discloses a belt deviation alarm and emergency stop method for belt edge detection, which adopts a conveyor belt deviation detection system based on laser lateral scanning belt edge distance measurement, including laser scanner A, laser scanner B and the conveyor belt. In the same plane, it is used to obtain the lateral distance between the edge of the belt and the edge support of the belt pulley; the laser scanning data can be sent to the Ethernet by the serial port processor for remote transmission; the upper computer realizes the online belt running according to the measurement data of the laser scanner A and B Real-time calculation of the offset angle and offset during the deviation process; the sound and light alarm and emergency stop device make corresponding judgments after data processing by the host computer, and control the operation of the sound and light alarm and emergency stop device. The invention makes up for the current situation that there is no high-precision non-contact belt conveyor real-time deviation detection system in the field. The invention has the advantages of simple and convenient measurement, strong anti-interference ability, high detection precision and strong real-time performance, and is not affected by the external environment on the determination of material distribution.

The invention discloses a self-controlled computer mainboard, which comprises a COMe mainboard, a CPCI pinboard, and a power module for supplying power for the COMe mainboard and the CPCI pinboard. The COMe mainboard comprises a processor, a bridge ribbon and a memory; the CPCI pinboard comprises a PCIe to PCI bridge chip; the processor adopts a Loongson 3A serial processor; the bridge ribbon adopts a Loongson 2H chip; the memory adopts a DDR3 memory grain chip; the Loongson 3A serial processor is connected with the Loongson 2H chip through an HT bus; the Loongson 3A serial processor and the Loongson 2H chip are connected with the DDR3 memory grain chip through memory channels; an EJTAG debugging interface used for carrying out reliability testing on the Loongson 3A serial processor and the Loongson 2H chip is also arranged on the COMe mainboard. According to the self-controlled computer mainboard provided by the invention, the Loongson 3A serial processor and the Loongson 2H matched bridge chip with full autonomy proprietary intellectual property rights are adopted, and the hardware interface of a mainboard platform is arranged, so that higher product domestication rate can be realized, the demands on information safety and self-controllability are met, and the technical risks and the uncontrollable hidden dangers in product use and maintenance are eliminated.