30 results about "Serial processor" patented technology

A method for scheduling cell transmissions through a switch with rate and delay guarantees and with low jitter is proposed. The method applies to a classic input-buffered N×N crossbar switch without speedup. The time axis is divided into frames each containing F time-slots. An N×N traffic rate matrix specifies a quantized guaranteed traffic rate from each input port to each output port. The traffic rate matrix is transformed into a permutation with NF elements which is decomposed into F permutations of N elements using a recursive and fair decomposition method. Each permutation is used to configure the crossbar switch for one time-slot within a frame of size F time-slots, and all F permutations result in a Frame Schedule. In the frame schedule, the expected Inter-Departure Time (IDT) between cells in a flow equals the Ideal IDT and the delay jitter is bounded and small. For fixed frame size F, an individual flow can often be scheduled in O(logN) steps, while a complete reconfiguration requires O(NlogN) steps when implemented in a serial processor. An RSVP or Differentiated Services-like algorithm can be used to reserve bandwidth and buffer space in an IP-router, an ATM switch or MPLS switch during a connection setup phase, and the proposed method can be used to schedule traffic in each router or switch. Best-effort traffic can be scheduled using any existing dynamic scheduling algorithm to fill the remaining unused switch capacity within each Frame. The scheduling algorithm also supports multicast traffic.

Methods, systems, and products are disclosed for broadcasting collective operation contributions throughout a parallel computer. The parallel computer includes a plurality of compute nodes connected together through a data communications network. Each compute node has a plurality of processors for use in collective parallel operations on the parallel computer. Broadcasting collective operation contributions throughout a parallel computer according to embodiments of the present invention includes: transmitting, by each processor on each compute node, that processor's collective operation contribution to the other processors on that compute node using intra-node communications; and transmitting on a designated network link, by each processor on each compute node according to a serial processor transmission sequence, that processor's collective operation contribution to the other processors on the other compute nodes using inter-node communications.

A multi-core processor configured to improve processing performance in certain computing contexts is provided. The multi-core processor includes multiple processing cores that implement barrel threading to execute multiple instruction threads in parallel while ensuring that the effects of an idle instruction or thread upon the performance of the processor is minimized. The multiple cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate inter-cache coherency issues. The barrel-threading can minimize the latency impacts associated with a shared data cache. In some examples, the multi-core processor can also include a serial processor configured to execute single threaded programming code that may not yield satisfactory performance in a processing environment that employs barrel threading.

It is a metal probe in lossless electromagnetism measurement technique field. The digital signal processor generates two paths of signals through two direct digital systemization chips into two multipliers that get two paths of separation signals through two low-pass filters. The data through the A/D conversion is sent to the digital signal processor for analysis and judgments. The human and machine dialogue system comprises single machines communicated with digital signal serial processors.

A microprocessor architecture comprises a plurality of processing elements arranged in a single instruction multiple data SIMD array, wherein each processing element includes a plurality of execution units, each of which is operable to process an instruction of a particular instruction type, a serial processor which includes a plurality of execution units, each of which is operable to process an instruction of a particular instruction type, and an instruction controller operable to receive a plurality of instructions, and to distribute received instructions to the execution units in dependence upon the instruction types of the received instruction. The execution units of the serial processor are operable to process respective instructions in parallel.

The invention discloses a self-controlled computer mainboard, which comprises a COMe mainboard, a CPCI pinboard, and a power module for supplying power for the COMe mainboard and the CPCI pinboard. The COMe mainboard comprises a processor, a bridge ribbon and a memory; the CPCI pinboard comprises a PCIe to PCI bridge chip; the processor adopts a Loongson 3A serial processor; the bridge ribbon adopts a Loongson 2H chip; the memory adopts a DDR3 memory grain chip; the Loongson 3A serial processor is connected with the Loongson 2H chip through an HT bus; the Loongson 3A serial processor and the Loongson 2H chip are connected with the DDR3 memory grain chip through memory channels; an EJTAG debugging interface used for carrying out reliability testing on the Loongson 3A serial processor and the Loongson 2H chip is also arranged on the COMe mainboard. According to the self-controlled computer mainboard provided by the invention, the Loongson 3A serial processor and the Loongson 2H matched bridge chip with full autonomy proprietary intellectual property rights are adopted, and the hardware interface of a mainboard platform is arranged, so that higher product domestication rate can be realized, the demands on information safety and self-controllability are met, and the technical risks and the uncontrollable hidden dangers in product use and maintenance are eliminated.

The invention discloses a digital predistortion processing method which comprises the following steps: (1) a parallel processor controls an analog-to-digital converter (ADC) to grab power amplifier input signals z(n) and amplifier output signals y(n) continuously, and time alignment is executed; (2) the parallel processor calculates elements of an autocorrelation matrix Ryy of the amplifier output signals y(n), calculates elements of a cross-correlation matrix Ryz of the amplifier input signals z(n) and the amplifier output signals y(n), and transmits the elements Ryz of the Ryy to a serial processor; (3) the serial processor receives the elements Ryz of the Ryy, generates the Ryy first and obtains inversion of the autocorrelation matrix Ryy, and finally times the Ryz to calculate predistortion coefficient; and (4) the parallel processor receives the predistortion coefficient and conducts predistortion processing. By means of the digital predistortion processing method, a simplifying method of the parallel processor for calculating the elements of the autocorrelation matrix is provided, data length of predistortion coefficient calculation is increased, and a predistortion processing effect is improved.

The invention relates to a dynamic overloading method for a DSP (Digital Signal Processor). The method comprises the following steps: 1, generating mapping files; 2, initializing the DSP; 3, guiding and copying overloading kernels in the mapping files into an internal storage of the DSP so as to cover primary application programs through overloading interface functions; 4, guiding and copying application programs in the mapping files which are stored in an external storage space into the internal storage of the DSP so as to cover the overloading kernels through the overloading kernels in the internal storage, and generating application programs to be operated; and 5, executing the application programs to be operated so as to finish dynamic overloading. As the traditional boot loading mode of an embedded type signal processing ADSP-TS20xS serial processor hardware platform cannot satisfy requirements of system functional reconstruction, the dynamic overloading method is additionally provided with the overloading kernels, and can use the overloading kernels to realize the real-time dynamic overloading operation for program mapping, so that the reconstruction ability of an embedded system is improved.

The invention discloses RF amplification and digital signal processing equipment, including laser head amplifier, radio frequency amplifier, synchronous detection amplifier, data separator, automatic gain controller, automatic amplitude limiter, demodulator, error correction device and serial-parallel processor , EFM demodulator, copy protection decryptor, descrambling device, format interface, the laser head amplifier, radio frequency amplifier, synchronous detection amplifier, data separator are connected in turn, and the automatic gain controller is connected with the automatic limiter, The demodulator is connected to the error correction device, and the automatic gain controller and the demodulator are respectively connected to the data separator. The invention enhances DVD data through laser head amplifier, radio frequency amplifier, synchronous detection amplifier, data separator, automatic gain controller, automatic limiter, demodulator, error correction device, serial-parallel processor and EFM demodulator processing, and then improve the stability of the data decryption performance of the DVD player through the copy protection decryptor.