23 results about "Speedup" patented technology

The invention discloses an efficient and parallel PIC / MCC rapid calculation method and system. According to the method, a PIC / MCC calculation process is divided into a charge distribution module, an electric field solution module, a particle propulsion module and a collision processing module, and parallel execution is carried out on a GPU through an independent kernel function. All simulation data are resident in a GPU video memory, and storage access is optimized by adopting a structured array and row main sequence layout. GPU atomic operation is introduced in charge distribution to ensure data consistency; selecting a parallel algorithm to accelerate Poisson equation solution according to dimensions in electric field solution; an electric field is obtained through interpolation in particle propulsion, and the particle motion state is updated; and adopting a Monte Carlo method to judge the collision type in parallel in the collision processing. Synchronous control among the modules is realized through a GPU event mechanism, and self-consistency of a physical process is ensured. According to the method, the bottleneck of traditional serial calculation is broken through, the speed-up ratio of more than 30 times is realized while the calculation precision is kept, and the efficiency and expandability of plasma numerical simulation are remarkably improved.

A technique for optimizing attention mechanism computations in transformer-based language models improves computational efficiency during both prefill and decode phases. The approach unequally partitions attention operations across multiple streaming multiprocessors of a hardware processing unit (e.g., such as a graphics processing unit, or GPU) to maximize hardware utilization. By leveraging the associative property of online softmax calculation as a reduction operation and employing stream-K style decomposition, the technique enables parallelization across all modes of the attention matrix, including the context length dimension. This allows for efficient distribution of computational workload across available GPU resources while ensuring equal total work allocation. The approach delivers significant speedup over existing methods, particularly for long context lengths, by maintaining near 100% GPU occupancy through optimal workload distribution and single-kernel execution.

The invention relates to the technical field of computers, and discloses a multi-FPGA collaborative deep neural network parallel acceleration method. According to the method, unified compiling and automatic calculation graph segmentation mapping based on a dynamic programming algorithm are carried out on a deep neural network model through a host control node, a heterogeneous strategy fusing data, the model and assembly line parallel is generated, and the problems of single FPGA computing power resource limitation and memory wall are effectively solved; direct communication between the FPGAs is achieved through a high-speed point-to-point internet, an asynchronous assembly line execution mechanism and a hardware-level data packaging technology are combined, communication delay is reduced, assembly line bubbles are eliminated, and a multi-FPGA cluster reaches a near-linear speed-up ratio; computing distribution is optimized in real time through a global load balancing unit, and the equipment utilization rate is increased; and meanwhile, a transparent deployment interface is provided through the hardware abstraction layer, so that the super-large-scale neural network can efficiently run on a multi-FPGA platform with low delay, and the overall calculation efficiency is improved.

The present invention relates to a computing offloading and resource allocation method applicable to a CPU-GPU heterogeneous cluster, which considers joint computing offloading and resource allocation in a CPU-GPU heterogeneous network to achieve lower system overhead and higher GPU utilization. Each task is decomposed into a serial segment and a parallel segment, which can be offloaded to the CPU and GPU respectively. Based on the resource sharing technology of the GPU, the computing power of the GPU is discretized, and the computing resource allocation is formulated as an integer programming. Then the task scheduling is modeled as a mixed integer non-linear programming problem to minimize the total overhead composed of latency and energy consumption. We decompose the mixed integer non-linear programming problem so that the computing offloading and resource allocation can be alternately optimized, which leads to an algorithm combining simulated annealing and convex optimization. Numerical simulations are carried out to evaluate the performance of the proposed solution, which is optimal in terms of system overhead, the number of benefited UEs and speedup ratio compared with traditional methods.

The application discloses a feature and knowledge driven optimal parallelism prediction method, system and medium, the method comprises the following steps: obtaining the multivariate runtime features of a target parallel program and embedding and coding to obtain multivariate fusion features; inputting the multivariate fusion features into a pre-trained speedup ratio prediction model to predict the speedup ratios of the target parallel program under a plurality of given parallelisms, the speedup ratio prediction model is a neural network prediction model, and a mapping relationship between the multivariate fusion features of the parallel program and the speedup ratios under the plurality of given parallelisms is established by training the training sample of the multivariate fusion features of the parallel program sample and the speedup ratio prior knowledge under different parallelisms; selecting the parallelism with the maximum speedup ratio as the optimal parallelism obtained by prediction. The application aims to realize efficient, accurate and reliable prediction of the optimal parallelism of the program, improve the computing efficiency, reduce the system resource consumption and reduce the execution time of the program.

The invention discloses a computing power prediction method and device, equipment and a storage medium. The method comprises the steps that hardware characteristic data of a jth first computing power chip and the first number of samples needed when the jth first computing power chip operates an ith measurement model are obtained, j is an integer from 1 to J, and i is an integer from 1 to I; inputting the first number into the first sub-model to obtain a first prediction speed-up ratio when the jth first computing power chip uses the first number of samples to operate the ith measurement model; inputting the hardware characteristic data of the jth first computing power chip into the second sub-model to obtain a first predicted computing power value when the jth first computing power chip uses the first number of samples to operate the ith measurement model; and correcting the first predicted computing power value according to the first predicted acceleration ratio to obtain a corresponding first corrected computing power value. Therefore, according to the embodiment of the invention, the measurement cost of the computing power value can be reduced, and the acquisition efficiency of the computing power value is improved.

Embodiments of the present disclosure provide enhanced systems and methods for implementing enhanced retiming of multiple clock netlists to improve integrated circuit (IC) design quality and provide enhanced retiming with reduced retiming runtime. Disclosed embodiments provide effective and efficient retiming without sacrificing netlist quality, and yield significant speedup of retiming runtime over traditional retiming.

A hardware accelerated solution of the SPM (Sequential Pattern Mining) is proposed using Micron's Automata Processor (AP), a hardware implementation of non-deterministic finite automata (NFAs) The Generalized Sequential Pattern (GSP) algorithm for SPM searching exposes massive parallelism, and is therefore well-suited for AP acceleration. The multi puss pruning strategy of the GSP is implemented is the APs fast reconfigurability. A generalized automaton structure is proposed by flattening sequential patterns to simple strings to reduce compilation time and to minimize overhead of reconfiguration. Up to 90× and 29× speedups are achieved by the AP-accelerated GSP on six real-world datasets, when compared with the optimized multicore CPU (Central Processing Unit) and GPU (Graphics Processing Unit) GSP implementations, respectively. The proposed CPU-AP solution also outperforms the state-of-the-art PrefixSpan and SPADE (Sequential PAttern Discovery using Equivalence classes algorithms on multicore CPU by up to 452× and 49× speedups.

The invention relates to a mercuric chloride NPU operator automatic tuning method and system based on fusion operator performance modeling, and the method comprises the steps: firstly constructing an end-to-end performance analysis model of a fusion operator for collaborative execution of a Cube core and a Vector core, and employing two modes to accurately predict execution delays under different parameter configurations through dynamic discrimination of a calculation speed relation between double cores; on the basis, a heuristic design space exploration algorithm with minimization of data movement amount as guidance is provided, and the algorithm is combined with the multilevel storage characteristic of the mercuric chloride NPU, adopts a two-stage strategy of block size optimization and buffer area allocation collaboration, and automatically searches for optimal parameter configuration meeting on-chip storage capacity constraints. According to the method, automatic performance adjustment and optimization of the fusion operator are realized, compared with traditional manual adjustment and optimization or compiler default configuration, near-optimal configuration can be found within a few minutes, the average performance prediction error is lower than 5%, the maximum performance speed-up ratio of part of operators can reach 1.46 times, and the efficiency of operator development and deployment on the mercuric chloride NPU is remarkably improved.

The application discloses a GPU-based Spark SQL acceleration method, which comprises the following steps: Spark SQL is composed of projection, data and condition, which respectively correspond to result, data and operation in the SQL query process, and a SQL statement is described in the order of result, data and operation; the read-in SQL statement is parsed to distinguish the keywords and expressions in the SQL statement, so that whether the SQL statement is standard is judged, and then an execution tree is formed, the execution tree and a data dictionary are bound and executed, and an optimal plan is selected from the plans for execution; and the GPU uses Cuda statements to realize common data combination and sorting operations in the SQL, so that the data query and other operations are greatly accelerated. The application combines the GPU with the Spark platform, transfers the operation operation of the SQL from the CPU to the GPU for execution, and realizes the speedup of the Spark SQL operation. No application code modification is needed, no additional server node is needed, and the hardware investment and system maintenance cost can be directly saved.

A computational architecture employing self-pruning fractal branch management for achieving supercomputer-class performance on standard hardware and noisy intermediate-scale quantum (NISQ) devices. Unlike conventional parallel computing systems requiring massive hardware resources or genetic algorithms requiring extensive population evolution, this invention utilizes hierarchical fractal doubles—modular computational units organized in self-similar tree structures—with real-time adaptive pruning eliminating non-promising solution branches based on geometric performance metrics computed via √2-scaled fractal analysis. Controlled perturbations (branch shaking) inject stochastic exploration preventing premature convergence while pruning maintains computational efficiency. The system achieves quantum-competitive performance on classical hardware through fractal interference patterns mimicking quantum superposition, and enables NISQ quantum computers to operate effectively despite hardware noise by pruning decoherence-corrupted branches before they contaminate computation. Core innovation: geometric pruning criterion comparing branch trajectory fractal dimension against optimal threshold, triggering instant elimination of branches exhibiting non-productive exploration patterns. Applications include neural architecture search, protein folding simulation, quantum system modeling, combinatorial optimization, and multi-agent coordination—all achieving 10-100× speedup versus conventional approaches while consuming 60-80% less energy through aggressive branch elimination. Technical advantages: (1) no training dataset required (deterministic pruning), (2) hardware-agnostic (runs on CPU / GPU / QPU), (3) noise-tolerant (quantum error mitigation via pruning), (4) energy-efficient (eliminates wasted computation), (5) scalable (fractal recursion to arbitrary depth).

The present invention discloses a method, system and medium for reducing the search space of compilation option sequences. The present invention includes sequentially enabling programs in a single compilation option sampling template program set, and obtaining speedup data relative to a preset compilation option sequence under each compilation option; calculating the harmonic mean, and screening out an effective compilation option set; constructing a two-dimensional option matrix, comparing the acceleration effects of binary option sequences and establishing a directed graph of compilation option relationships; using depth-first search to obtain a set of candidate compilation option sequences; and using a genetic algorithm to iteratively optimize on a target program to generate an optimal compilation option sequence with the shortest running time. The purpose of the present invention is to address the problem of low optimization efficiency caused by numerous and complexly related compilation options of a compiler. By establishing a compilation option relationship model and generating a set of candidate compilation option sequences, the search space is reduced, the number of iterations of the genetic algorithm is reduced, and while ensuring the optimization of program performance, the compilation optimization overhead is significantly reduced.

This invention discloses a high-efficiency XMSS computation unit architecture design method supporting the SPHINCS+ protocol, relating to the field of hardware acceleration technology, and solving the problem of slow hardware computation speed of traditional SPHINCS+ XMSS signatures. Firstly, at the algorithm level, the Merkle tree construction logic is optimized by adjusting the key pair selected during signing and reducing the number of nodes to be computed during signing, thereby reducing the overall overhead of tree construction. Secondly, in terms of hardware architecture, a parallel processing approach using multiple hash chains is adopted, optimizing the overall pipeline layout. Furthermore, an innovative method of alternating dual-key pair input is used, effectively reducing the overall clock cycles required for key pair generation and signature computation, significantly improving hardware utilization. Experimental results show that this design achieves speedups of 3.86 and 3.87 for key generation and signature computation, respectively, on an FPGA platform. This invention has promising application prospects in the field of hardware acceleration of post-quantum cryptography algorithms supporting the SPHINCS+ protocol.

The application provides a data grouping method, system and computing device for GPU architecture, and relates to the technical field of parallel computing.The method gradually distributes sub-grids to different GPU groups in an iterative manner, and dynamically evaluates load balancing and communication overhead during the distribution process to realize a final grouping scheme.The method gives up the calculation cost of finding an absolute global optimal solution, limits the inter-group communication overhead to a specific threshold by relaxing the constraint condition, and realizes load balancing under the premise.The method does not depend on a specific CFD grid type, adopts multi-element scoring and threshold constraint, and when the number of GPU cluster nodes increases, the grouping algorithm can still maintain high execution speed and excellent parallel speedup ratio.In addition to the CFD field, it can also be migrated to other scientific and engineering computing fields such as electromagnetic field simulation, finite element analysis and other grid communication dependent fields.

The present invention relates to a blocked sample-based application speedup device and method, and the device includes a blocked sample generation unit that samples events occurring regardless of whether a thread is in a CPU execution state or a blocked state, to generate blocked samples, a first profiler that analyzes an on-CPU event and an off-CPU event of the blocked samples in an integrated manner and identifies a performance bottleneck of an application, a second profiler that analyzes the interdependence between the on-CPU event and the off-CPU event and predicts speedup for the performance bottleneck through virtual optimization of a specific event, and an optimization strategy generation unit that generates an optimization strategy for the specific event.

The present invention relates to an improved method of increasing the speed of the cosine calculations. Preferably the improved methodology comprises a GPU-accelerated cosine similarity implementation for Tandem Mass Spectrometry (MS / MS) with approximately 1000-fold speedup compared to the MatchMS reference at a rate of 0.005% incorrect matches and a rate of 0.002% incorrect scores.

The invention discloses a WASM smart contract bytecode loop vector optimization method suitable for hardware acceleration, and aims to solve the problems that in a block chain scene, a smart contract exists in a WASM bytecode form, and an existing optimizer does not support loop optimization starting from the WASM bytecode, the optimization of Pass is expanded in a Binaryen framework, and the optimization of the WASM bytecode is realized. By combining formalized constraint verification and runtime check, a single-layer linear loop is converted into a single-instruction multi-data SIMD instruction, the theoretical 4-time speed-up ratio is achieved, and meanwhile semantic equivalence and runtime safety are ensured. The method comprises four core layers, namely an analysis input layer, a protocol preprocessing layer, a constraint condition verification layer and an optimization generation layer, wherein the constraint condition verification layer and the optimization generation layer are realized through a five-stage optimization Pass based on a Binaryen framework. According to the method, the execution efficiency of the intelligent contract containing the high-frequency linear single cycle is remarkably improved, the method is suitable for optimization preprocessing before block chain transaction execution, the execution speed of the intelligent contract can be improved, and the overall performance of the block chain is improved.

This invention relates to the field of motion control technology for embedded systems, specifically a low-computational-overhead acceleration / deceleration planning method suitable for embedded systems. It addresses the technical problem that existing acceleration / deceleration planning methods cannot simultaneously balance computational complexity, dynamic adaptability, and discrete-domain model errors. The method comprises four steps: preprocessing before planning, activation of the planning module, planning execution, and dynamic parameter adjustment. Its core principle is to smooth the position curve through multi-layer window moving average planning, combined with module overlay to achieve real-time adjustment of the target position and running speed. The window size is determined based on the embedded system control cycle, avoiding discrete errors from the design perspective. Each control cycle only requires one calculation mainly involving addition, significantly reducing CPU resource consumption. This invention allows for flexible adjustment of motion smoothness, adapting to various industrial automation scenarios such as CNC machine tools, robots, and semiconductor equipment, balancing motion smoothness, computational efficiency, and real-time system response capabilities.

This invention relates to the field of artificial intelligence technology, providing a multi-operator optimization scheduling method, electronic device, and storage medium. The method includes: acquiring performance data of the model to be optimized on target computing hardware; calculating the overall model speedup ratio based on the execution time proportion of each operator in the performance data, and sorting them to obtain an operator optimization priority queue; sequentially executing optimization iterations on each operator in the operator optimization priority queue as a target operator; acquiring the performance test results of the target operator in the current iteration cycle and evaluating them based on a preset termination criterion; if the preset termination criterion is met, stopping the optimization iteration of the target operator and scheduling the next operator to continue the optimization iteration. This invention achieves automated scheduling that balances global performance and single-operator computing resource utilization by prioritizing based on the overall model speedup ratio and automatically controlling the iteration termination of operators using a preset termination criterion, resulting in reasonable allocation of computing resources and improved overall optimization efficiency.

This invention comprises three layers of parallelism: 1. A 64-bit parallel layer, using a single 64-bit instruction within a single 64-bit CPU core to simultaneously process arithmetic operations on eight base-64 data columns, each column consisting of 6 data bits and 2 carry bits. 2. A multi-core parallel layer, executing 64-bit instructions simultaneously on multiple CPU cores, with each core executing independently. 3. A hyper-threaded parallel layer, using two hardware threads within each core to simultaneously execute different tasks, sharing an execution unit. These three layers are independent, requiring no synchronization between them, resulting in a total performance improvement to multiplicative level rather than additive level. Real-world testing shows a 128x speedup on an 8-core, 16-thread CPU, breaking the Amdahl's Law limitation and achieving linear scalability without a saturation point compared to traditional architectures.

The invention discloses a heterogeneous resource scheduling method and system and a storage medium, and relates to the technical field of computers. The heterogeneous resource scheduling method comprises the steps of obtaining a plurality of computing power clusters based on a current computing task; obtaining a first computing power cluster from each computing power cluster; for each first computing power cluster, acquiring a corresponding communication efficiency value; obtaining a target computing power cluster based on each communication efficiency value; and based on the target computing power cluster, executing the current computing task. The method has the core advantages that the limitation that the computing power cluster is constructed only through the resource quota in a traditional method is broken through, the physical interconnection topology characteristics of the computing power node bottom layer are fully considered, the cross-device communication bottleneck can be avoided, the linear speed-up ratio reduction risk is further reduced, and the problem of computing power islands is fundamentally solved.

This invention relates to a resource scheduling method and related equipment for a hybrid computing cluster. The method includes: acquiring computing tasks and extracting task characteristic parameters; estimating the quantum computing speedup ratio based on the task characteristic parameters; if the quantum computing speedup ratio is greater than a threshold, allocating the computing task to a quantum computing unit for execution; acquiring the physical state parameters of each quantum computing unit to calculate a quantum resource health score; dividing the computing task based on coherence time constraints according to the quantum resource health score and a decoherence time window, generating multiple quantum subtasks; before the execution of the quantum subtasks, if it is determined that the estimated execution time of any quantum subtask exceeds the corresponding decoherence time window, or the quantum resource health score is lower than the score threshold, triggering an automatic rollback mechanism to schedule the corresponding quantum subtask to a classical computing unit for computation. This solves the problems of poor resource scheduling and low task processing efficiency in related technologies.

The invention discloses a signal interface test method and system based on a configuration table. The method comprises the steps of performing normalization design on a signal interface function test design script and an execution script; a component test framework is adopted for the test case, and the component test framework is automatically constructed through source codes; automatically executing an execution record generated by result analysis, if the function realized by the control code is consistent with the data requirement in the IO configuration table, passing the use case, otherwise, not passing the use case; analyzing the problem, and then carrying out iteration again until all the use cases pass the operation; the system comprises a signal interface module, a test framework module, an execution recording module and an iteration module. The efficiency is improved, and the speed is increased by more than ten times compared with manual testing; testing is sufficient, closed-loop data is achieved, detailed test case execution results are automatically generated, and rapid defect positioning is assisted; the cost is optimized, the labor hour is reduced, the automation of the test process is realized in continuous integration, and the product iteration is accelerated.