11 results about "Terabit" patented technology

An artificial-intelligence computing device integrates at least two compute stacks and a hybrid memory subsystem of volatile and non-volatile high-bandwidth memory within an all-silicon domain. The volatile memory stores frequently written activations and key-value caches, while the non-volatile memory stores largely static model weights. Compute stacks communicate over silicon interconnects exceeding one hundred terabits per second, enabling sustained trillion-parameter inference locally without external storage and with energy below one picojoule per bit.

The utility model discloses an edge server with a radio frequency signal receiving function, which comprises a radio frequency module and a conversion module, and the radio frequency module comprises three filtering units which are electrically connected in sequence. The first filtering unit comprises an amplitude limiter, a digital step attenuator, a first amplifier, a first filter, a first frequency mixer and a first local oscillation source, the amplitude limiter, the digital step attenuator, the first amplifier, the first filter and the first frequency mixer are electrically connected in sequence, and the first local oscillation source is electrically connected with the first frequency mixer. According to the edge server with the radio-frequency signal receiving function, the radio-frequency signal is received by adopting the radio-frequency module, and the radio-frequency signal is directly filtered, so that unwanted frequency bands in the radio-frequency signal are filtered out, and a radio-frequency signal receiving device which needs to be additionally used in the prior art is omitted; and the data is transmitted to an edge server in a gigabit or 10 gigabit mode, so that the arrangement and carrying of the edge in a scene are easier.

The utility model discloses a 10 gigabit Ethernet lightning stroke protection isolation transformer. The 10 gigabit Ethernet lightning stroke protection isolation transformer comprises a packaging part; the substrate is arranged on the inner side of the packaging part, the substrate comprises a plurality of channels and at least one real grounding circuit, each channel comprises a common-mode noise suppression coil and an isolation transformer, an overvoltage protection unit is arranged between a center tap port of the isolation transformer and the real grounding circuit, and the overvoltage protection unit comprises an overvoltage protection circuit and an overvoltage protection circuit. And the input loss of the channel is not more than 1.5 dB when the frequency is 1 to 200 MHz, is not more than 2.0 db when the frequency is 200 to 400 MHz, and is not more than 3.0 db when the frequency is 400 to 500 MHz. According to the utility model, the anti-interference capability and lightning protection performance of the 10 gigabit Ethernet can be effectively improved, more stable and reliable high-speed transmission quality is provided, and the requirements of modern communication equipment for high efficiency and high reliability are met.

The utility model discloses a storage control blade based on FT2000 + / 64, which comprises a processor unit, and the processor unit is electrically connected with a bridge piece unit, a BMC health management unit, a 10-gigabit network card unit, a gigabit network card unit, a CPLD unit, an IPMB interface unit, a clock unit, a hot plug unit and a power rail. The BMC health management unit is electrically connected with the IPMB interface unit; the clock unit and the hot plug unit are electrically connected with the power rail. A domestic Feiteng FT2000 + / 64 core processor is used as a core, front-end data comprehensive processing is completed, and operation resource support is provided for achieving functions of task management, system management, data fusion, comprehensive detection, comprehensive identification and the like. In addition, a Feiteng X100 bridge chip is adopted, and the system has the advantages of being high in universality, flexible in expansion, low in power consumption and the like. The application requirements of various markets can be met, the method can be widely applied to the market fields of desktops / portable terminals, servers, embedded type and the like, and the product competitiveness is effectively improved.

The invention relates to a virtualized multi-master shared concurrent access architecture and a driving method thereof.The architecture comprises a physical hardware layer, a hardware abstraction layer, a virtualization management layer, a kernel driving layer and a user application layer which are sequentially connected, all the layers interact through standardized interfaces, the physical hardware layer comprises PCIe hardware equipment, and the kernel driving layer comprises a kernel driving layer and a kernel driving layer; the PCIe hardware equipment comprises a hard disk, a gigabit network card, a 10-gigabit network card and a secure clock board card; the hardware abstraction layer comprises BIOS firmware; the virtualization management layer comprises a Hypervisor, a centralized management unit, a HyperCall request processor and a second-stage page table mapping module; the kernel driving layer comprises a driving program running on an SVM (Support Vector Machine) and SCB (Service Control Block) driving components respectively running on business virtual machines, and the business virtual machines comprise a ReWorks virtual machine and an RT-Linux virtual machine; and the user application layer comprises a real-time service application program running in each service virtual machine. Compared with the prior art, concurrent access of multiple virtual machines to the same secure clock board card is realized, and the real-time performance of data access and the hardware utilization rate are improved.

The present application relates to communication methods and communication apparatuses. An example method includes obtaining a matrix U. The matrix U is a channel space basis matrix having a mapping relationship with a matrix V, where the matrix V is a steering vector-based matrix. The disclosed techniques can establish a mapping relationship between the matrix U and multi-path based RF map, which could be used to solve the pilot design problem for terabit multiple-input and multiple-output (T-MIMO) system where there is a large number for transmitter and receiver antenna ports and large bandwidth.

A modular artificial-intelligence computing device includes a silicon substrate assembly carrying multiple vertically bonded semiconductor stacks interconnected by wiring layers and through-substrate interconnections. The stacks include compute and memory assemblies communicating through on-substrate signal paths that provide aggregate bandwidth above one hundred terabits per second. The architecture provides exa-scale inference performance using standardized cooling and power delivery methods and power dissipation of less than 1 kW.

Methods, apparatus, and systems for forward error correction (FEC) that involves inner and outer zipper codes are disclosed. In some embodiments, a message being sent from a transmitter in a network is encoded with a first zipper code, bits of the message are interleaved, and a second zipper code is encoded. The encoded message can then be sent to a receiver in the network where it is decoded to correct transmission errors. Decoding involves decoding the first and second zipper codes and de-interleaving bits. In some embodiments, one soft decoder and one hard decoder are used, and decoding is performed iteratively. In some embodiments, encoding the first and / or second zipper codes involves excluding some parity bits of the respective zipper code from having copies in that code's virtual buffer. Embodiments may provide improvements in the power consumption and performance of FEC, especially for 1.6 terabit-per-second optical communication.

Methods, apparatus, and systems for forward error correction (FEC) that involves inner and outer zipper codes are disclosed. In some embodiments, a message being sent from a transmitter in a network is encoded with a first zipper code, bits of the message are interleaved, and a second zipper code is encoded. The encoded message can then be sent to a receiver in the network where it is decoded to correct transmission errors. Decoding involves decoding the first and second zipper codes and de-interleaving bits. In some embodiments, one soft decoder and one hard decoder are used, and decoding is performed iteratively. In some embodiments, encoding the first and / or second zipper codes involves excluding some parity bits of the respective zipper code from having copies in that code's virtual buffer. Embodiments may provide improvements in the power consumption and performance of FEC, especially for 1.6 terabit-per-second optical communication.

A system for providing efficient, reliable, and accurate calibration and measurements of a satellite communication (SATCOM) test system, especially in E-band frequencies where precision of measurement and calibration plays a large role in reliable communications at terabit data rates. The system may include a vector network analyzer (VNA), at 67 GHz operation, calibrated using SOLT-type calibrations. The vector network analyzer (VNA) may be communicatively coupled to a device under test (DUT) or system under test (SUT) to obtain calibration and measurement data. The system may also include a signal generator for generating at least one signal. The system may further include an active mixer communicatively coupled to the signal generator. The active mixer may up-convert the least one signal to E-band frequencies. In some examples, the vector network analyzer (VNA), the local oscillator (LO) signal generator, and the active mixer may be synchronized or phase-locked using a reference.

The invention discloses an advanced 3D packaging platform with adaptive thermal management, and belongs to the technical field of semiconductor packaging. Comprising a shape memory alloy network, phase change material microcapsules, a prestressed filler system, through silicon vias and a monitoring system, the warping compensation of the shape memory alloy network is lower than 2 microns through a shape memory alloy wire with the diameter of 100 microns, and the shape memory alloy network has 8% reversible strain; the phase-change material microcapsule provides thermal buffer of 180 Joules per gram, and the cycle stability is greater than 10,000 times; the prestress filling material system has the initial pressure stress of-50 MPa; the silicon through holes have the diameter of 5 microns and the spacing of 10 microns, and the bandwidth of 8 bits per second is realized. Phase-change material microcapsules (packaging a paraffin base material, and having a transformation temperature of 55 DEG C) provide a high-thermal-conductivity buffer of 180 Joules / g, and can quickly absorb local hot spot heat; and meanwhile, the cycle stability is up to 10,000 times, no performance degradation is caused after long-term use, and the material is adaptive to a high-frequency thermal cycle scene.