353 results about "Ferroelectric capacitor" patented technology

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

The invention provides a ferroelectric memory and a data reading method and a data writing method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem of low storage density. The ferroelectric memory comprises a memory cell array, the memory cell array comprises a plurality of memory cells arranged in an array, each memory cell stores n bits of data, each memory cell comprises a transistor and 2n-1 ferroelectric capacitors coupled with the transistor, and n is a positive integer greater than 1; a plurality of word lines, each word line being coupled to the memory cells arranged in rows in the memory cell array; and a plurality of bit lines, each bit line being coupled to the memory cells arranged in columns in the memory cell array. 2n storage states can be determined by using the polarization directions of the 2n-1 ferroelectric capacitors, and each storage state corresponds to one type of data, so that the 2n-1 ferroelectric capacitors store n-bit data, multi-state storage of the ferroelectric memory is realized, and the storage density of the ferroelectric memory is improved.

The invention belongs to the field of microelectronics, and particularly relates to a full-transparent HfO2-based ferroelectric capacitor and a preparation method and application thereof, and the full-transparent HfO2-based ferroelectric capacitor comprises a substrate, a bottom electrode, a ferroelectric medium layer and a top electrode which are sequentially stacked from bottom to top. Insertion layers are respectively arranged between the ferroelectric medium layer and the bottom electrode and between the ferroelectric medium layer and the top electrode. And the intercalation layer is a TiOx intercalation layer. Compared with the prior art, the defects that in the prior art, the ferroelectric performance of a transparent ferroelectric device is poor, a high annealing temperature is needed, and then the thermal budget requirement of a back-end process is not met are overcome; the TiOx intercalation layers are introduced to the two sides of the ferroelectric dielectric layer, so that the grain orientation is improved, the annealing temperature can be reduced to 400 DEG C, and the method can be compatible with a back-end process.

The invention discloses a ferroelectric memory circuit capable of improving an imprinting effect and an imprinting effect improving method, the ferroelectric memory circuit comprises a plurality of memory units distributed in rows and columns, each memory unit comprises a ferroelectric capacitor, one polar plate of each ferroelectric capacitor is connected to a plate line PL, the plate line PL is connected with a plate line voltage driving circuit, and the plate line voltage driving circuit is connected with a ferroelectric capacitor. The board line voltage driving circuit is provided with a signal input IN, and comprises a high-low level switching circuit which is used for outputting a high level to a board line PL or outputting a low level to the board line PL according to the high-low level of the signal input IN; and the high-level voltage selection circuit is connected to the at least two high-level voltage outputs and is used for applying the selected high-level voltage to the board line PL when the high level is output to the board line PL according to the signal input IN. The circuit structure of the ferroelectric memory is optimized and improved, the ferroelectric memory is tested before leaving a factory, and voltage compensation adjustment is carried out according to the test, so that memory unit failure possibly caused by an imprinting effect can be prevented, and the read-write frequency of the memory unit is obviously increased.

The invention provides a ferroelectric storage array and a preparation method thereof, a memory and electronic equipment, relates to the technical field of semiconductors, and aims to enlarge a read-write data window of the memory and reduce power consumption of the memory. The ferroelectric storage array comprises a plurality of storage units, each storage unit comprises a ferroelectric capacitor and a transistor, the ferroelectric capacitor comprises a first electrode and a second electrode which are oppositely arranged, and a ferroelectric layer and an insertion layer which are located between the first electrode and the second electrode. An insertion layer can be arranged between the ferroelectric layer and the first electrode, or between the ferroelectric layer and the second electrode, or between the ferroelectric layer and the first electrode and between the ferroelectric layer and the second electrode. The intercalation layer comprises electric dipoles, and the electric dipoles are distributed on the two opposite surfaces of the intercalation layer in the direction from the first electrode to the second electrode. The ferroelectric memory array can be applied to a ferroelectric random access memory to realize reading and writing of data.

The invention discloses a flexible multi-valued hafnium oxide-based ferroelectric capacitor and a preparation method thereof, the flexible multi-valued hafnium oxide-based ferroelectric capacitor still has stable ferroelectricity in a bending deformation state, can realize 32 storage states, not only meets the requirement of storage pool calculation for multi-valued storage, but also effectively solves the problem that a ferroelectric material is difficult to maintain stability under strain in the wearable field.

The invention relates to the technical field of nonvolatile memories, in particular to a 2T1FC ferroelectric memory cell with a memory gate line and a preparation method of the 2T1FC ferroelectric memory cell. The 2T1FC ferroelectric storage unit with the storage gate line comprises a ferroelectric capacitor and a storage transistor which realizes read-write operation of data through polarization modulation of the ferroelectric capacitor; the control transistor is used for enabling a bit line to perform gating access; and the storage gate line is used for controlling the gate of the storage transistor and improving the holding capability of the written data. According to the invention, the special storage gate line is used, so that self-charge dissipation after writing is prevented, and the non-volatility is enhanced; separation of the storage path and the control path minimizes accidental flipping in the read / write cycle; the service life of the device is prolonged by lower write-in current stress and an isolated gate structure; low-voltage writing with high retentivity can be realized, and the method is suitable for energy-limited edge AI equipment.

The invention discloses a tunable magnetoelectric antenna and a preparation method thereof. The tunable magnetoelectric antenna comprises a substrate, wherein a selected surface of the substrate is provided with a first region and a second region which are sequentially arranged along a first direction; the magnetoelectric antenna is arranged in the first area, and a resonant cavity is formed between the magnetoelectric antenna and the first area; and the trench capacitor is arranged in the second area, and the trench capacitor is connected with the bulk acoustic wave excitation magnetoelectric antenna in series. The tunable magnetoelectric antenna is formed by connecting the magnetoelectric antenna and the ferroelectric capacitor in series, the ferroelectric capacitor is of a groove structure, the capacitance value of the capacitor can be effectively increased, and transverse leakage of sound waves can be restrained.

The invention discloses a method for improving the performance of an HZO ferroelectric capacitor through plasma interface treatment. The method comprises the following steps: forming a TiN bottom electrode on a Si substrate material through deposition; zrO2 and HfO2 are deposited on the TiN bottom electrode through an atomic layer to form an HZO ferroelectric medium layer; performing plasma treatment on the upper surface of the HZO ferroelectric dielectric layer; after processing, a TiN top electrode is formed on the upper surface of the HZO ferroelectric dielectric layer through deposition; carrying out rapid thermal annealing treatment in an N2 atmosphere; according to the method, plasma is adopted to process the upper surface of the ferroelectric film, and the oxygen vacancy distribution uniformity of the upper surface of the HZO film can be optimized, so that the wake-up effect is inhibited, and the performance of the ferroelectric film is improved; plasma is adopted to process the upper surface of the ferroelectric film, and generation of oxygen vacancies on the upper surface of the HZO film can be inhibited, so that electric leakage is reduced, the fatigue effect and the imprinting effect are inhibited, and the performance of the ferroelectric film is improved.

The invention belongs to the field of microelectronics, and particularly relates to a ferroelectric capacitor, a preparation method thereof and a three-dimensional ferroelectric memory array, and the ferroelectric capacitor comprises a substrate, a bottom electrode, a ferroelectric dielectric layer, a deoxidizing layer and a top electrode which are sequentially arranged from bottom to top; the ferroelectric medium layer is an Hf < 1-x > Zr < x > O < 2 > layer, 0 lt; xlt; the Hf-rich composition is realized by controlling the Hf: Zr super-cycle ratio of atomic layer deposition; the thickness of the ferroelectric medium layer is 1-6 nm, and the thickness of the bottom electrode is 0.1-5 nm. Compared with the prior art, the problems of polarization characteristic degradation caused by thinning of the ferroelectric layer in the hafnium-based ferroelectric capacitor and crosstalk in the FeRAM in the prior art are solved. According to the scheme, the oxygen vacancy concentration is accurately adjusted to inhibit the formation of a non-ferroelectric phase, so that the ultra-thin ferroelectric film can still maintain relatively high remanent polarization while the size is reduced, a storage window is effectively improved, and the wake-up requirement is reduced.

A memory device includes a substrate and vertically stacked ferroelectric capacitors formed on the substrate. A first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a constant voltage is applied. First and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors. In some instances, a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. The different thicknesses allow the capacitive output for each capacitor to produce different electric field outputs. Accordingly, a combination of different output signals can be produced based on different threshold voltage levels for each capacitor contributing to the output.

The invention belongs to the field of microelectronics, and particularly relates to a ferroelectric capacitor for improving initial state polarization intensity and a preparation method and application thereof.The ferroelectric capacitor comprises a substrate, a bottom electrode, an ultrathin ferroelectric medium layer and a top electrode which are sequentially stacked from bottom to top; the ultra-thin ferroelectric dielectric layer is an Hf < 1-x > Zr < x > O < 2 > thin film, 0 lt; xlt; and in the atomic layer deposition process, the Hf-rich thin film is grown and formed by controlling the Hf: Zr super-cycle ratio. Compared with the prior art, the ferroelectric capacitor solves the problems that in the prior art, in order to improve the initial-state polarization intensity of the ferroelectric capacitor, a function matched with the HZO thin film is added, the thickness is increased due to layers, and the improvement effect is limited. According to the scheme, the doping proportion of Hf in the ultra-thin ferroelectric dielectric layer is properly increased, the formation energy of a non-ferroelectric T phase is remarkably improved, stable existence of a ferroelectric O phase is further promoted, and therefore the ferroelectric O phase with ferroelectric hysteresis close to the situation that awakening is not needed, a high initial state 2Pr value and a high content is achieved.

Provided are a three-dimensional (3D) ferroelectric random access memory (FeRAM) with an increased memory window per unit area and reduced process difficulty and distribution and a method of manufacturing the same. The 3D FeRAM includes a substrate, bit lines extending in a first horizontal direction spaced apart from each other in a second horizontal direction, word lines disposed over the bit line, extending in the second horizontal direction, and spaced apart from each other in the first horizontal direction, semiconductor patterns arranged at certain intervals on corresponding portions of the word lines, and ferroelectric capacitor (FeCap) structures disposed over the semiconductor patterns, wherein the FeCap structure includes a first electrode including a body portion and at least two horizontal extensions, a ferroelectric layer covering outer walls of the first electrode, and second electrodes covering the ferroelectric layer on the horizontal extensions.

The embodiment of the invention provides a ferroelectric capacitor and a preparation method thereof, a storage array, a memory and electronic equipment, relates to the technical field of semiconductors, and is used for reducing M phases in a ferroelectric layer in the ferroelectric capacitor and improving the reliability of the ferroelectric capacitor. The ferroelectric capacitor includes a first electrode, a second electrode, and a ferroelectric layer between the first electrode and the second electrode. Wherein the first electrode is a polycrystal, the first electrode comprises a first columnar crystal grain, a first included angle exists between the extension direction of the first columnar crystal grain and the first reference plane, and the first included angle is larger than 0 degree or equal to 90 degrees. The ratio of the number of the first columnar crystal grains to the number of all crystal grains in the first electrode is greater than or equal to 50%. The first reference plane is parallel to a portion of the surface of the ferroelectric layer opposite the first columnar grains. A ferroelectric capacitor is applied to an electronic device to improve the performance of the electronic device.

The present invention proposes a method for realizing in-memory computing based on a small-signal ferroelectric capacitor with non-destructive readout, belonging to the field of novel computing architectures. The present invention realizes the linearly inseparable comparison operation of a content-addressable memory (CAM) unit and the local multiplication operation of a signed synaptic unit on a ferroelectric capacitor, reducing the hardware cost. Compared with the method of distance measurement based on the traditional CAM architecture, it has higher computational linearity and detection range, as well as lower search power consumption; at the same time, compared with the resistive synaptic array, it has no DC power consumption and no potential DC conduction path, avoiding the "IR drop" problem of large-scale arrays, and has lower computational power consumption, showing significant advantages in edge machine learning tasks based on feature retrieval and neural network hardware acceleration.

The invention discloses an in-memory encryption method based on a cross-point array ferroelectric capacitor array, and belongs to the field of data security and computing security. According to the invention, a cross-point array ferroelectric capacitor FeCAP array is respectively adopted as a key array and a complementary key array, and array-level XOR operation is executed between a plaintext and a key by the generated operation through a diagonal data coding mode and a coupling signal subtraction circuit, so that high-parallel XOR encryption in a memory is realized. And data decryption can be symmetrically realized by applying the ciphertext to the input and using the same key array and the complementary key array. In combination with the artificial intelligence calculation accelerator based on the cross point array ferroelectric capacitor array, high-density, high-energy-efficiency and data security enhanced in-memory calculation application can be realized.

The invention discloses a method for realizing PUF (Physical Unclonable Function) by using homomorphic write-in of an FRAM (Frequency Random Access Memory) of a 2T2C structure, which comprises the following steps of: firstly, carrying out independent write-in operation on two ferroelectric capacitors and writing same data, and carrying out homomorphic storage; then, the two ferroelectric capacitors are recovered to different residual polarization states by using the manufacturing difference of the ferroelectric capacitors; then applying a reverse level to enable the two ferroelectric capacitors to reach a saturated polarization state from a residual polarization state; and finally, comparing a difference value delta I of the polarization current responses of the two ferroelectric capacitors, and outputting a corresponding binary numerical value according to the difference value delta I and a set judgment condition, thereby generating a random PUF response. According to the invention, the PUF response with high randomness and uniqueness is generated through homomorphic storage of the 2T2C FRAM and by using the polarization characteristic of the ferroelectric material.

The invention relates to an HZO ferroelectric film with a controllable coercive field, a ferroelectric capacitor and a preparation method of the ferroelectric capacitor. The HZO ferroelectric film is provided with at least one microbeam gallium ion implantation region; and the gallium ion injection amount of each micro-beam gallium ion injection region is 1.3 * 10 < 14 >-5.2 * 10 < 14 > ion / cm < 2 >. According to the HZO ferroelectric film with the controllable coercive field provided by the invention, the coercive field of the HZO ferroelectric film can be accurately regulated and controlled by adjusting the gallium ion injection amount in the micro-beam gallium ion injection region, and meanwhile, the high polarization intensity, the structural uniformity and the electrical stability of the ferroelectric film can be maintained. Moreover, different injection amounts of gallium ions are injected into different regions of the HZO ferroelectric film, different coercive fields can be shown in different regions, the HZO ferroelectric film can be applied to a multi-valued memory, and the storage density is greatly improved.

The invention provides a PbZrO3 antiferroelectric capacitor and a preparation method thereof, and relates to the technical field of ferroelectric materials, the PbZrO3 antiferroelectric capacitor comprises a first electrode layer, a PbO layer, a solid solution ferroelectric antiferroelectric layer, a LaNiO3 layer and the like, and phases in the solid solution ferroelectric antiferroelectric layer comprise PbZrO3, a ferroelectric and an Ag-containing Au phase. The invention also provides a preparation method of the capacitor, and the method comprises the following steps: depositing a LaNiO3 precursor solution on a single crystal substrate, and carrying out the crystallization; mixing the PbZrO3 precursor solution with the ferroelectric precursor solution, and then adding Au nanoparticles containing Ag; the LaNiO3 layer is coated with the mixed solution, and crystallization is carried out; depositing the PbO precursor solution on the surface of the antiferroelectric layer of the solid solution ferroelectric, and crystallizing; and carrying out gold electrode deposition to obtain the PbZrO3 antiferroelectric capacitor. The capacitor is high in energy storage efficiency and high in dielectric constant.

The invention provides an epitaxial hafnium oxide-based ferroelectric capacitor and an atomic layer deposition preparation method thereof, and the preparation method comprises the steps: providing a substrate layer, and depositing a zirconia epitaxial buffer layer on the substrate layer through employing an atomic layer deposition technology; forming a hafnium oxide-based epitaxial ferroelectric layer on the zirconium oxide epitaxial buffer layer by adopting an atomic layer deposition process; photoresist is spin-coated on the hafnium oxide-based epitaxial ferroelectric layer, exposure and development are carried out, and the shape of a top electrode is defined; preparing a top electrode on the hafnium oxide-based epitaxial ferroelectric layer; and annealing by adopting a rapid annealing process to realize the ferroelectricity of the hafnium oxide-based epitaxial ferroelectric layer. According to the application, the zirconium oxide epitaxial buffer layer is arranged between the ferroelectric layer and the substrate layer, so that the hafnium oxide-based epitaxial ferroelectric layer grown through ALD presents a highly oriented epitaxial lattice structure, the leakage current of the hafnium oxide-based ferroelectric capacitor can be reduced, and the cycle performance of the capacitor is improved.

The invention discloses a 2T2FC ferroelectric memory cell and a preparation method thereof, and the 2T2FC ferroelectric memory cell comprises a memory transistor; the source electrode of the control transistor is connected to the drain electrode of the storage transistor; one end of the first ferroelectric capacitor is connected with a first plate line, and the other end is coupled to the grid electrode of the storage transistor; one end of the second ferroelectric capacitor is connected with a second plate line, and the other end is coupled to the grid electrode of the storage transistor; a word line connected to the gate of the memory transistor; a bit line connected to the drain of the control transistor; a source line connected to the source of the memory transistor; a control line connected to the gate of the control transistor; the control transistor is configured to selectively enable or disable access to the memory transistor. By adopting one storage transistor and one control transistor, a storage path is separated from a control path, the reliability of data reading and writing is improved, meanwhile, the leakage current is reduced, and the memory is increased.

This application provides a ferroelectric random access memory and a terminal, and relates to the field of storage technologies, to improve strength of a read signal and read efficiency in a read phase, and reduce an area of the ferroelectric random access memory. The ferroelectric random access memory includes bit lines, an ith plate line, a multiplexer, a sense amplifier, and a plurality of ferroelectric memory cells. Each ferroelectric memory array of the plurality of ferroelectric memory cells includes m columns of ferroelectric memory cells arranged in array, and the ferroelectric memory cell includes one ferroelectric capacitor and one first transistor. In any row, a ferroelectric capacitor of the (m*n+i)th column of ferroelectric memory cells is electrically connected to the ith plate line; and in the read phase, each plate line in the ith plate line inputs a high level to the ferroelectric memory cell in a time division manner, where m is an integer greater than or equal to 2, n is an integer greater than or equal to 0, and i is a positive integer less than or equal to m. Each column of ferroelectric memory cells are electrically connected to one of the bit lines, and every m bit lines are electrically connected to a same multiplexer. Each sense amplifier is electrically connected to one multiplexer.

A memory device includes a substrate and vertically stacked ferroelectric capacitors formed on the substrate. A first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a constant voltage is applied. First and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors. In some cases, a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. The different thicknesses allow the capacitive output for each capacitor to produce different output electric fields. Accordingly, a combination of different output signals can be generated based on different threshold voltage levels for each capacitor contributing to the output.

Provided is a semiconductor device capable of reading data from a ferroelectric capacitor having a small amount of polarization. The semiconductor device includes first to fourth transistors, first and second capacitive elements, and first and second inverters. A first terminal of the first capacitive element is connected to a first terminal of each of the first and second transistors and to an input terminal of the first inverter. A first terminal of the second capacitive element is connected to a first terminal of each of the second and third transistors and to an input terminal of the second inverter. An output terminal of the first inverter is connected to a second terminal of each of the first and second transistors. An output terminal of the second inverter is connected to a second terminal of each of the third and fourth transistors. A gate of each of the first and third transistors is connected to first wiring. A gate of each of the second and fourth transistors is connected to second wiring.

The invention provides a ferroelectric capacitor and a preparation method thereof, the ferroelectric capacitor comprises a bottom electrode, a ferroelectric layer and a top electrode which are sequentially arranged from bottom to top, the ferroelectric layer is a lanthanum-doped hafnium zirconium oxide film prepared by an atomic layer deposition method, and the doping concentration of lanthanum in the lanthanum-doped hafnium zirconium oxide film is less than 1 at%. The ferroelectric capacitor can solve the problems that in the prior art, a ferroelectric capacitor based on an HZO cannot give consideration to a high k value and strong ferroelectricity, and is difficult to meet a low-power-consumption application scene.

The invention provides a semiconductor device, a preparation method thereof and an electronic device, and the method comprises the steps: providing a substrate, and forming a first interlayer dielectric layer on the substrate; forming a first pole plate layer, a ferroelectric medium layer and a second pole plate layer on the first interlayer dielectric layer, wherein the second pole plate layer comprises tungsten; forming a patterned first bottom anti-reflection layer, a first oxide hard mask layer, a first metal hard mask layer and a second bottom anti-reflection layer on the second polar plate layer; and etching the second polar plate layer, the ferroelectric dielectric layer and the first polar plate layer by taking the first bottom anti-reflection layer, the first oxide hard mask layer, the first metal hard mask layer and the second bottom anti-reflection layer as masks to form the ferroelectric capacitor. According to the scheme, the second pole plate layer comprises tungsten, the first bottom anti-reflection layer, the first oxide hard mask layer, the first metal hard mask layer and the second bottom anti-reflection layer serve as masks, the second pole plate layer, the ferroelectric medium layer and the first pole plate layer are etched to form the ferroelectric capacitor, and the product performance is improved.

The embodiment of the invention provides a memory array and a preparation method thereof, a memory and electronic equipment, relates to the technical field of semiconductors, and is used for reducing the power consumption of a ferroelectric memory. The memory array includes a substrate and a plurality of ferroelectric capacitors. The substrate comprises a first area and a plurality of second areas, and the first area is located between every two adjacent second areas. A plurality of ferroelectric capacitors are located on the plurality of second regions. The ferroelectric capacitor includes a first plate, a second plate, and a ferroelectric layer. The first pole plate extends along the thickness direction of the substrate. The second pole plate is located on the surface of the first pole plate away from the substrate. The ferroelectric layer is located between the second pole plate and the first pole plate. Wherein the second pole plates of the plurality of ferroelectric capacitors located on the same second area are connected to form plate lines, and the plate lines located on different second areas are arranged at intervals. The storage array is applied to the electronic equipment, and the performance of the electronic equipment is improved.

The present disclosure provides a ferroelectric memory and a data reading method and a data writing method thereof, and relates to the technical field of semiconductor technology, and is used to solve the technical problem of low storage density. The ferroelectric memory comprises a storage cell array, the storage cell array comprises a plurality of storage cells arranged in an array, each storage cell stores n-bit data, wherein each storage cell comprises a transistor and 2 n -1 ferroelectric capacitor coupled to the transistor, n is a positive integer greater than 1; a plurality of word lines, each word line is coupled to the storage cells arranged in a row in the storage cell array; a plurality of bit lines, each bit line is coupled to the storage cells arranged in a column in the storage cell array. The polarization direction of the 2 n -1 ferroelectric capacitor can determine 2 n a storage state, each storage state corresponds to one data, so that the 2 n -1 ferroelectric capacitor stores n-bit data, realizes the multi-state storage of the ferroelectric memory, and improves the storage density of the ferroelectric memory.

In accordance with at least one example of the description, a method comprises forming a substrate, and forming transducer elements over the substrate, each transducer element including a ferroelectric capacitor and a conductive element spaced from the ferroelectric capacitor by a dielectric material, the ferroelectric capacitor being between the conductive element and the substrate.

The present invention relates to a semiconductor memory device including a ferroelectric capacitor and a manufacturing method thereof, and more particularly, to a semiconductor memory device capable of preventing electrons from being captured in an interface layer (IL) by adding a ferroelectric capacitor to a location where an oxide filler is formed inside a channel structure and forming the ferroelectric capacitor between the channel structure and a bottom electrode, and a manufacturing method thereof.