31 results about "Ferroelectric capacitor" patented technology

In accordance with at least one example of the description, a method comprises forming a substrate, and forming transducer elements over the substrate, each transducer element including a ferroelectric capacitor and a conductive element spaced from the ferroelectric capacitor by a dielectric material, the ferroelectric capacitor being between the conductive element and the substrate.

This application provides a chip and its fabrication method, chip packaging structure, and electronic device, relating to the field of semiconductor technology. In this semiconductor structure, a ferroelectric capacitor is placed within the second dielectric layer of a first back-end trace layer. If the capacitance value of the ferroelectric capacitor meets the requirements, there is no need to add an additional sub-transfer layer. This eliminates the impact of the additional sub-transfer layer on the semiconductor structure performance (e.g., it can eliminate the impact of the additional sub-transfer layer on the signal transmission speed of logic circuits in the semiconductor structure). Even if the thickness of the first back-end trace layer cannot meet the capacitance requirement of the ferroelectric capacitor, and an additional sub-transfer layer is needed to increase the space for the ferroelectric capacitor, the additional sub-transfer layer only serves to supplement space, and its thickness is relatively thin, resulting in a relatively small impact on the semiconductor structure performance.

This invention discloses a method and apparatus for awakening the polarization of a large-area ferroelectric capacitor at the wafer level. The wafer consists of a bottom electrode, a ferroelectric layer, and a patterned, independent top electrode array stacked sequentially from bottom to top. The bottom electrode is electrically connected to one end of a pulse voltage generator, and the conductive film on the surface of a flexible conductive roller is electrically connected to the other end of the pulse voltage generator. By controlling the horizontal movement of the wafer stage, the flexible conductive roller is driven to roll and contact the surface of the top electrode array; simultaneously, a preset pulse voltage is applied between the bottom electrode and the conductive film using the pulse voltage generator, increasing the ferroelectric remanent polarization intensity of the ferroelectric film covered by the top electrode in the contact area, thus achieving ferroelectric polarization awakening. This invention, after a high-temperature heat treatment at over 200°C, efficiently and over a large area awakens the polarization of the ferroelectric film corresponding to the top electrode array, ensuring high stability and consistency in its ferroelectric remanent polarization intensity.

Memory device with series-connected ferroelectric transistor and capacitor, associated electronic circuit, programming method and reading method. The present invention relates to a memory device (14) comprising: - a ferroelectric field-effect transistor (20) having a gate electrode (21) and first (22) and second (23) conduction electrodes; - a ferroelectric capacitor (25) having first (27) and second (28) charge electrodes; the transistor (20) and the ferroelectric capacitor (25) being connected according to a first connection configuration (C1) in which the first conduction electrode (22) is connected to a reference potential (GND) and the second conduction electrode (23) is connected to the first charge electrode (27);or according to a second connection configuration in which the first conduction electrode (22) is connected to the first charging electrode (27) and the second conduction electrode (23) is connected to the second charging electrode (28). Figure for the abbreviation: Figure 2;

The application relates to the technical field of semiconductor storage, and discloses a 3D chain ferroelectric storage array structure and a preparation method thereof. The 3D chain ferroelectric storage array structure comprises an alternating medium stack as a base body, a horizontal cavity formed through wet etching, a ring channel transistor prepared in the cavity and surrounding a vertical bit line, and a storage unit formed by integrating a ferroelectric capacitor. The vertical bit line serves as a source-drain electrode, and a horizontal metal gate forms a word line, so that a three-dimensional stacked structure is realized. The preparation process of the application is compatible with the existing NAND process, the gate control capability is effectively improved, the short channel effect is inhibited, and the storage density and the device reliability are improved.

A semiconductor device includes a memory cell including a transistor and a capacitor that includes a ferroelectric; a word line; a bit line; and a plate line. A gate of the transistor is electrically connected to the word line. One of a source and a drain of the transistor is electrically connected to the bit line. The other of the source and the drain of the transistor is electrically connected to one electrode of the capacitor. The other electrode of the capacitor is electrically connected to the plate line. The semiconductor device has a function of supplying a potential that controls an on state or an off state of the transistor to the word line, a function of supplying a first potential or a second potential to the bit line, and a function of supplying a third potential, a fourth potential, or a fifth potential to the plate line.

The application provides a method for reducing a flipping electric field of a ferroelectric material, which can be applied to the technical fields of ferroelectric materials and semiconductor devices, and comprises the following steps: arranging a top electrode and a bottom electrode on opposite sides of the ferroelectric material respectively to form a ferroelectric capacitor; and connecting the ferroelectric capacitor and a dielectric capacitor in series to form a ferroelectric-dielectric system, so as to inhibit the ferroelectricity of the ferroelectric material and reduce the flipping electric field of the ferroelectric material. The reduction degree of the flipping electric field of the ferroelectric material is related to the capacitance value of the dielectric capacitor. The method for reducing the flipping electric field of the ferroelectric material by connecting the ferroelectric body and the dielectric body in series breaks through the limitation of the traditional scheme and has the characteristics of simple principle, non-destructiveness, small implementation difficulty and large regulation range.

A method for fabricating an inverse ferroelectric capacitor memory based on lateral window readout is disclosed. The device includes a substrate, a TiO2 interlayer, a superlattice HZO ferroelectric layer, a top electrode, and a bottom electrode. The substrate includes P-type doped regions and N-type doped regions. The TiO2 interlayer is disposed on the substrate and covers at least one interface between the P-type and N-type doped regions. The superlattice HZO ferroelectric layer is disposed on the TiO2 interlayer. The top electrode is disposed on the superlattice HZO ferroelectric layer, and the bottom electrode is disposed on the substrate and covers the N-type doped region. This invention introduces a TiO2 interlayer-superlattice HZO synergistic structure into the inverse ferroelectric capacitor, increasing the lateral window from less than 1 V to 2.5 V, thereby achieving 3-bit multi-value based on the lateral window readout method. Simultaneously, it retains the high speed and high durability advantages of ferroelectric technology while avoiding the defects of millisecond programming and low reliability.

The application provides a hafnium-based ferroelectric capacitor based on an island-shaped metal layer and a preparation method thereof and a ferroelectric random access memory, and comprises the following steps: providing a substrate; sequentially forming a lower electrode and a first hafnium-based ferroelectric layer on the substrate; forming a discontinuous island-shaped metal structure on the first hafnium-based ferroelectric layer; sequentially forming a second hafnium-based ferroelectric layer and an upper electrode on the island-shaped metal structure; and performing a rapid thermal annealing treatment to crystallize hafnium-based ferroelectric materials in the first hafnium-based ferroelectric layer and the second hafnium-based ferroelectric layer. The metal layer in an island-shaped distribution is formed to constitute a five-layer superlattice capacitor structure, which can not only effectively shield the depolarization electric field inside the ferroelectric layer, enhance the stability of the polarization state, prolong the data retention time, but also greatly reduce the nucleation barrier of the ferroelectric domain, so that the polarization reversal can be quickly completed under a lower applied electric field, and the problem of how to improve the performance of the hafnium-based ferroelectric capacitor is solved.

The application discloses a method for neural network online training and reasoning based on a CMOS transistor hybrid memory circuit, which adopts a CMOS transistor synapse device and a CMOS capacitor to form a synapse unit, replaces a traditional memristor and a ferroelectric capacitor, the writing durability of the CMOS transistor synapse device is far superior to that of the traditional memristor, the reading operation of the CMOS capacitor is non-destructive, the life loss caused by data rewriting is avoided, the whole process is realized based on a standard CMOS process, is fully compatible with an existing integrated circuit manufacturing process, and the hardware production cost is reduced, only analog weights are called in the reasoning stage to perform operation, and there is no additional data transmission; in the weight transmission stage, an external DAC is not needed, digital-to-analog conversion is realized by using a circuit parasitic parameter, and the energy consumption of an edge device is greatly reduced.

The application provides a precursor, a preparation method of the precursor and a ferroelectric capacitor, a chip, a memory and an electronic device, relates to the technical field of semiconductors, and provides an interface intercalation and improves the material of the precursor used for preparing the interface intercalation, so that the problems of the performance reduction of the ferroelectric capacitor caused by impurities generated in the preparation process and the influence of etching materials on the surface morphology of the film layer caused by the fact that the intermediate product contains the etching materials are solved on the basis of the improvement of the defects of the ferroelectric layer and the guarantee of the high thermal stability of the precursor. The precursor comprises a central atom and a plurality of ligands coordinated with the central atom. The central atom comprises a group Vb metal atom, and the plurality of ligands comprise a tert-butylimido and a multidentate ligand.

This application discloses a ferroelectric memory and a method for fabricating a ferroelectric memory. The ferroelectric memory includes a memory array comprising an X-row × Y-column memory structure. Each memory structure includes Z memory cells stacked sequentially; X, Y, and Z are integers greater than 1. Each memory cell includes multiple ferroelectric capacitors and a transistor stacked sequentially. The transistors in the Z memory cells of each memory structure share a common source or drain. The common source or drain in each memory structure extends through the corresponding memory structure along the stacking direction of the Z memory cells. Each memory structure includes Z gates. Using this application, a low-cost, high-capacity memory can be realized.

A capacitor structure including a ferroelectric capacitor and a semiconductor device are provided. The semiconductor device includes a transistor structure and a capacitor structure connected to the transistor structure. The capacitor structure includes a plate line extending in a first direction, a ferroelectric capacitor connected to the plate line, a global plate line disposed at the same height as the plate line, and a plate line selection transistor connected to the global plate line and the plate line. The transistor structure includes an access transistor having a gate connected to a word line, one end connected to the ferroelectric capacitor, and the other end connected to a bit line.

A ferroelectric non-volatile memory component, comprising: a first electrode comprising a first metal; a ferroelectric portion; and a second electrode comprising a second metal; the ferroelectric portion placing the first electrode and the second electrode into electronic communication with one another, the ferroelectric portion optionally contacting at least one of the first electrode and the second electrode, the ferroelectric portion comprising AlxSc(1-x)N, the component optionally comprising a non-ferroelectric interlayer disposed between the ferroelectric portion and the first electrode and / or between the ferroelectric portion and the second electrode, and the component optionally exhibiting at least one of (a) an operating voltage of less than 15 V at 600° C., (b) an on / off ratio of greater than 1 at a temperature at 600° C., and (c) retention of a polar state following exposure to 1 Mrad Cobalt-60 (60Co) gamma radiation. A ferroelectric capacitor, comprising: a first electrode comprising a first metal; a ferroelectric portion, the ferroelectric portion comprising AlxSc(1-x)N; a second electrode comprising a second metal; and a silicon carbide portion; the ferroelectric portion contacting the first electrode and the silicon carbide portion, the second electrode contacting the silicon carbide portion. A ferroelectric component, comprising: a ferroelectric portion, the ferroelectric portion comprising AlxSc(1-x)N; a first electrode comprising a first metal, the first electrode surmounting at least a portion of the ferroelectric portion; and a second electrode comprising a second metal.

The present invention relates to a ferroelectric capacitor comprising a praseodymium oxide oxygen buffer layer. The ferroelectric capacitor of the present invention comprises a lower electrode, an upper electrode, a hafnium zirconium oxide ferroelectric layer disposed between the two electrodes, and a praseodymium oxide oxygen buffer layer disposed between the ferroelectric layer and the electrode. The above praseodymium oxide oxygen buffer layer has multivalent valence characteristics in which Pr3+ and Pr4+ already coexist in a significant proportion immediately after crystallization annealing, and has fluorite (111) crystal planes that are lattice-matched with the orthogonal (111) crystal planes of hafnium zirconium oxide. Accordingly, the oxygen buffer layer functions as a crystal nucleation template that induces orthogonal (111) preferential orientation for the ferroelectric layer, and at the same time functions as a bidirectional oxygen ion reservoir that absorbs oxygen vacancies generated during repeated switching and resupplies oxygen when returning to the initial state. The ferroelectric capacitor according to the present invention exhibits a residual polarization of 40 ÌC / cm² or more under low voltage conditions of an applied voltage of 1.3 V or less, and simultaneously satisfies repeatability of 10 or more cycles, wake-up free characteristics, and data retention characteristics equivalent to 10 years in an 85 ℃ environment. In addition, it can be formed within a post-processing thermal budget of 500 ℃ or less and can be conformally applied to a 3D trench structure and a 3D stacked memory array.

Provided is a ferroelectric capacitor in which an increase in coercive electric field and degradation of rewrite resistance are suppressed with a simple structure. The ferroelectric capacitor of the present invention is a ferroelectric capacitor, including: an upper electrode; a lower electrode; and a ferroelectric layer arranged between the upper electrode and the lower electrode so as to be in close contact therewith, wherein at least one electrode selected from the group consisting of the upper electrode and the lower electrode includes a composite metal oxide electrode formed so as to contain a composite metal oxide in which a second oxide is added to a conductive first oxide containing at least one metal element selected from the group consisting of In, Ga, Zn, Sn, Ru, Ir and Sr at a molar ratio smaller than that of the first oxide, the second oxide having oxygen dissociation energy, when considered as a metal oxide of one of the metal elements, which is larger by 200 KJ / mol or more, as compared to the metal oxide having the largest oxygen dissociation energy among the first oxides.

This invention relates to the field of ferroelectric memory technology, and provides a modeling method and system for polycrystalline ferroelectric field-effect transistors (FeFETs). The method includes: structural modeling of a polycrystalline ferroelectric thin film, discretizing the polycrystalline ferroelectric thin film into multiple grains with independent crystal orientations, establishing the coordinate transformation relationship between the local crystallographic coordinate system and the global coordinate system of each grain, and using the coordinate transformation relationship to determine the influence of each grain orientation on the polarization response; based on the influence relationship, constructing a set of nonlinear partial differential equations that couple polarization and electric field based on phase-field theory; mapping the set of nonlinear partial differential equations to a ferroelectric capacitor equivalent circuit model; and combining the ferroelectric capacitor equivalent circuit model with a compact transistor model in series, achieving electrical coupling through charge continuity conditions to construct a polycrystalline ferroelectric field-effect transistor model. This method can achieve accurate modeling and thus predict the actual electrical behavior of FeFETs.

A ferroelectric memory includes at least one storage cell. Each storage cell includes a transistor, a first ferroelectric capacitor, and at least one voltage divider capacitor. The transistor includes a gate electrode, a source electrode, and a drain electrode. One electrode of the first ferroelectric capacitor is connected to the gate electrode. The other electrode of the first ferroelectric capacitor is connected to a word line. One electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the gate electrode, and the other electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the source electrode.

A memory device including a ferroelectric field-effect transistor including a gate electrode and first and second conduction electrodes; a ferroelectric capacitor including first and second charge electrodes; the transistor and the ferroelectric capacitor being connected according to a first connection configuration, wherein the first conduction electrode is connected to a reference potential and the second conduction electrode is connected to the first charge electrode, or according to a second connection configuration, wherein the first conduction electrode is connected to the first charge electrode and the second conduction electrode is connected to the second charge electrode.

This invention provides a hafnium-based ferroelectric capacitor device and its fabrication method. The fabrication method includes the following steps: providing a substrate and cleaning the substrate; sputtering a lower electrode onto the cleaned substrate; depositing a ZrO2 / HZO dielectric layer on the lower electrode using atomic layer deposition (ALD); growing an upper interface modification layer on the ZrO2 / HZO dielectric layer at low temperature using ALD; and sputtering a upper electrode onto the upper interface modification layer. The hafnium-based ferroelectric capacitor device fabricated by this invention exhibits high durability and high dielectric reliability while possessing large polarization, enabling the device to withstand high temperatures up to 10°C. 11 Under multiple cycles, it exhibits stable polarization reversal without wake-up or fatigue, and in dielectric reliability testing, it increases the 10-year lifetime operating voltage of the device by 28%, significantly improving the long-term durability of the device and expanding the application scenarios of ferroelectric memory devices.

In a memory cell including a ferroelectric capacitor, data is read without data destruction. When the reading operation is performed in the memory cell including the ferroelectric capacitor, voltage applied to the counter electrode of the ferroelectric capacitor is gradually increased so as not to cause polarization destruction in the ferroelectric capacitor. A first reading operation from the memory cell is performed by applying a first voltage that does not cause polarization inversion of the ferroelectric layer to the capacitor, a second reading operation from the memory cell is performed by applying a second voltage that does not cause polarization inversion of the ferroelectric layer to the capacitor, and the second voltage is higher than the first voltage.

A system may include a memory configured to store data of a first logic state in a ferroelectric capacitor when an electric polarization of the ferroelectric capacitor is in a first direction. A system may include a controller configured to erase the data from the memory by commanding the electric polarization of the ferroelectric capacitor in a second direction, opposite of the first direction and skipping a subsequent write operation of a null value to the memory.

The application provides a ferroelectric memory array and a preparation method thereof, a memory and an electronic device, and relates to the technical field of semiconductors, aiming to improve the uniformity and reliability of the performance of the memory. The ferroelectric memory array can be a two-dimensional structure or a three-dimensional structure, and comprises a plurality of memory cells arranged in an array, each memory cell comprising a ferroelectric capacitor and a transistor. The ferroelectric capacitor comprises a first electrode and a second electrode arranged oppositely, and a ferroelectric film arranged between the first electrode and the second electrode. The crystal phase of the ferroelectric film comprises a tetragonal phase, the ferroelectric film comprises a first layer and a second layer in contact, at least one of the first layer and the second layer comprises a ferroelectric material, and the lattice constant of the first layer is different from the lattice constant of the second layer. The ferroelectric memory array can be applied to a ferroelectric memory, a ferroelectric field effect transistor memory or a ferroelectric tunnel junction memory to realize reading and writing of data.

The semiconductor device according to an embodiment of the present disclosure is configured such that the gate electrodes of the p-type FET and the n-type FET included in the second inverter are each formed by a first shared electrode. The first electrodes of the first ferroelectric capacitor and the second ferroelectric capacitor are each formed by a second shared electrode. The first shared electrode and the second shared electrode are connected to each other. The second electrodes of the first ferroelectric capacitor and the second electrodes of the second ferroelectric capacitor are configured to be separate from each other.

A semiconductor device includes a transistor structure and a capacitor structure connected to the transistor structure. The capacitor structure includes a plate line extending in a first direction, a ferroelectric capacitor connected to the plate line, a global plate line provided at the same level as the plate line, and a plate line select transistor connected to the global plate line and the plate line. The transistor structure includes an access transistor having a gate connected to a wordline, and one end connected to the ferroelectric capacitor and another end connected to a bitline.

The application discloses an implementation method of a charge domain storage and calculation integrated computing paradigm based on a ferroelectric memory, and comprises the following steps: dividing a ferroelectric capacitor array into a plurality of computing units, each of which is composed of a plurality of ferroelectric capacitors located in the same row and sequentially adjacent to each other; selecting the ferroelectric capacitors in the ferroelectric capacitor array through a word line, applying a reading pulse to the selected ferroelectric capacitors through a bit line to trigger the ferroelectric domain inversion in the ferroelectric capacitors, and collecting the polarization inversion charge generated by the ferroelectric capacitors due to the ferroelectric domain inversion through a source line; and performing weighted summation on the polarization inversion charge generated by all the ferroelectric capacitors in the ferroelectric capacitor array to obtain the total output charge computing paradigm of the ferroelectric capacitor array, which is: The implementation method is simple and reasonable, the obtained computing paradigm is feasible, has super-high energy efficiency characteristics, and shows great potential in the field of high-energy efficiency scientific calculation.

This invention discloses a ferroelectric memory device based on a gallium oxide transistor and a hafnium oxide zirconium trench capacitor. The ferroelectric memory device includes at least 1024 independent memory cells, all disposed on the same gallium oxide substrate, with adjacent memory cells electrically isolated by an Al₂O₃ insulating layer. Each memory cell includes a gallium oxide transistor, a ferroelectric capacitor, and a Ru metal interconnect layer (i.e., a 1T1C structure) between them. The gallium oxide transistor includes an n-type doped gallium oxide epitaxial layer disposed on the gallium oxide substrate, and a discontinuous Al₂O₃ gate dielectric layer, a gate, a drain, and a source formed on the epitaxial layer. The ferroelectric capacitor is disposed within a circular trench in the gallium oxide substrate, and from near the inner wall surface of the trench, it sequentially includes a bottom electrode, a Hf electrode, and a ferroelectric capacitor. 0.5 Zr 0.5 O2 ferroelectric thin film and top electrode. This invention achieves miniaturization, high-density integration, and high reliability of memory devices, and is particularly suitable for non-volatile data storage applications in harsh environments such as high temperatures.

The application discloses a phase change device and an electronic system based on a ferroelectric capacitor state response type pulse driving, the phase change device integrates a ferroelectric capacitor and a Ge-based phase change material layer to form a composite functional unit. The core lies in that when a single voltage signal is applied to the composite unit, the phase change direction is uniquely determined by the state (crystalline state / amorphous state) of the phase change material layer before the signal is applied. This is due to the difference between the crystalline state and the amorphous state in resistance and thermal conductivity, which leads to completely different local heat accumulation and quenching effects under the same electric signal. The application realizes reliable bidirectional phase change with the simplest control logic, greatly simplifies the driving circuit, and provides an innovative hardware basis for high-performance storage, programmable switches and neuromorphic computing.

An apparatus comprising: a microelectromechanical system (MEMS) resonator; and a metal stack over the MEMS resonator, the metal stack including a first metal layer, a second metal layer, and first and second metal vias coupled between the first and second metal layers, at least one of the first or second metal layers overlapping at least part of the MEMS resonator. some of the ferroelectric capacitors.