215 results about "Ferroelectric capacitor" patented technology

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

The invention belongs to the field of microelectronics, and particularly relates to a full-transparent HfO2-based ferroelectric capacitor and a preparation method and application thereof, and the full-transparent HfO2-based ferroelectric capacitor comprises a substrate, a bottom electrode, a ferroelectric medium layer and a top electrode which are sequentially stacked from bottom to top. Insertion layers are respectively arranged between the ferroelectric medium layer and the bottom electrode and between the ferroelectric medium layer and the top electrode. And the intercalation layer is a TiOx intercalation layer. Compared with the prior art, the defects that in the prior art, the ferroelectric performance of a transparent ferroelectric device is poor, a high annealing temperature is needed, and then the thermal budget requirement of a back-end process is not met are overcome; the TiOx intercalation layers are introduced to the two sides of the ferroelectric dielectric layer, so that the grain orientation is improved, the annealing temperature can be reduced to 400 DEG C, and the method can be compatible with a back-end process.

The invention relates to the technical field of nonvolatile memories, in particular to a 2T1FC ferroelectric memory cell with a memory gate line and a preparation method of the 2T1FC ferroelectric memory cell. The 2T1FC ferroelectric storage unit with the storage gate line comprises a ferroelectric capacitor and a storage transistor which realizes read-write operation of data through polarization modulation of the ferroelectric capacitor; the control transistor is used for enabling a bit line to perform gating access; and the storage gate line is used for controlling the gate of the storage transistor and improving the holding capability of the written data. According to the invention, the special storage gate line is used, so that self-charge dissipation after writing is prevented, and the non-volatility is enhanced; separation of the storage path and the control path minimizes accidental flipping in the read / write cycle; the service life of the device is prolonged by lower write-in current stress and an isolated gate structure; low-voltage writing with high retentivity can be realized, and the method is suitable for energy-limited edge AI equipment.

The invention discloses a method for improving the performance of an HZO ferroelectric capacitor through plasma interface treatment. The method comprises the following steps: forming a TiN bottom electrode on a Si substrate material through deposition; zrO2 and HfO2 are deposited on the TiN bottom electrode through an atomic layer to form an HZO ferroelectric medium layer; performing plasma treatment on the upper surface of the HZO ferroelectric dielectric layer; after processing, a TiN top electrode is formed on the upper surface of the HZO ferroelectric dielectric layer through deposition; carrying out rapid thermal annealing treatment in an N2 atmosphere; according to the method, plasma is adopted to process the upper surface of the ferroelectric film, and the oxygen vacancy distribution uniformity of the upper surface of the HZO film can be optimized, so that the wake-up effect is inhibited, and the performance of the ferroelectric film is improved; plasma is adopted to process the upper surface of the ferroelectric film, and generation of oxygen vacancies on the upper surface of the HZO film can be inhibited, so that electric leakage is reduced, the fatigue effect and the imprinting effect are inhibited, and the performance of the ferroelectric film is improved.

The invention belongs to the field of microelectronics, and particularly relates to a ferroelectric capacitor, a preparation method thereof and a three-dimensional ferroelectric memory array, and the ferroelectric capacitor comprises a substrate, a bottom electrode, a ferroelectric dielectric layer, a deoxidizing layer and a top electrode which are sequentially arranged from bottom to top; the ferroelectric medium layer is an Hf < 1-x > Zr < x > O < 2 > layer, 0 lt; xlt; the Hf-rich composition is realized by controlling the Hf: Zr super-cycle ratio of atomic layer deposition; the thickness of the ferroelectric medium layer is 1-6 nm, and the thickness of the bottom electrode is 0.1-5 nm. Compared with the prior art, the problems of polarization characteristic degradation caused by thinning of the ferroelectric layer in the hafnium-based ferroelectric capacitor and crosstalk in the FeRAM in the prior art are solved. According to the scheme, the oxygen vacancy concentration is accurately adjusted to inhibit the formation of a non-ferroelectric phase, so that the ultra-thin ferroelectric film can still maintain relatively high remanent polarization while the size is reduced, a storage window is effectively improved, and the wake-up requirement is reduced.

A memory device includes a substrate and vertically stacked ferroelectric capacitors formed on the substrate. A first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a constant voltage is applied. First and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors. In some instances, a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. The different thicknesses allow the capacitive output for each capacitor to produce different electric field outputs. Accordingly, a combination of different output signals can be produced based on different threshold voltage levels for each capacitor contributing to the output.

The invention belongs to the field of microelectronics, and particularly relates to a ferroelectric capacitor for improving initial state polarization intensity and a preparation method and application thereof.The ferroelectric capacitor comprises a substrate, a bottom electrode, an ultrathin ferroelectric medium layer and a top electrode which are sequentially stacked from bottom to top; the ultra-thin ferroelectric dielectric layer is an Hf < 1-x > Zr < x > O < 2 > thin film, 0 lt; xlt; and in the atomic layer deposition process, the Hf-rich thin film is grown and formed by controlling the Hf: Zr super-cycle ratio. Compared with the prior art, the ferroelectric capacitor solves the problems that in the prior art, in order to improve the initial-state polarization intensity of the ferroelectric capacitor, a function matched with the HZO thin film is added, the thickness is increased due to layers, and the improvement effect is limited. According to the scheme, the doping proportion of Hf in the ultra-thin ferroelectric dielectric layer is properly increased, the formation energy of a non-ferroelectric T phase is remarkably improved, stable existence of a ferroelectric O phase is further promoted, and therefore the ferroelectric O phase with ferroelectric hysteresis close to the situation that awakening is not needed, a high initial state 2Pr value and a high content is achieved.

The embodiment of the invention provides a ferroelectric capacitor and a preparation method thereof, a storage array, a memory and electronic equipment, relates to the technical field of semiconductors, and is used for reducing M phases in a ferroelectric layer in the ferroelectric capacitor and improving the reliability of the ferroelectric capacitor. The ferroelectric capacitor includes a first electrode, a second electrode, and a ferroelectric layer between the first electrode and the second electrode. Wherein the first electrode is a polycrystal, the first electrode comprises a first columnar crystal grain, a first included angle exists between the extension direction of the first columnar crystal grain and the first reference plane, and the first included angle is larger than 0 degree or equal to 90 degrees. The ratio of the number of the first columnar crystal grains to the number of all crystal grains in the first electrode is greater than or equal to 50%. The first reference plane is parallel to a portion of the surface of the ferroelectric layer opposite the first columnar grains. A ferroelectric capacitor is applied to an electronic device to improve the performance of the electronic device.

The present invention proposes a method for realizing in-memory computing based on a small-signal ferroelectric capacitor with non-destructive readout, belonging to the field of novel computing architectures. The present invention realizes the linearly inseparable comparison operation of a content-addressable memory (CAM) unit and the local multiplication operation of a signed synaptic unit on a ferroelectric capacitor, reducing the hardware cost. Compared with the method of distance measurement based on the traditional CAM architecture, it has higher computational linearity and detection range, as well as lower search power consumption; at the same time, compared with the resistive synaptic array, it has no DC power consumption and no potential DC conduction path, avoiding the "IR drop" problem of large-scale arrays, and has lower computational power consumption, showing significant advantages in edge machine learning tasks based on feature retrieval and neural network hardware acceleration.

The invention discloses an in-memory encryption method based on a cross-point array ferroelectric capacitor array, and belongs to the field of data security and computing security. According to the invention, a cross-point array ferroelectric capacitor FeCAP array is respectively adopted as a key array and a complementary key array, and array-level XOR operation is executed between a plaintext and a key by the generated operation through a diagonal data coding mode and a coupling signal subtraction circuit, so that high-parallel XOR encryption in a memory is realized. And data decryption can be symmetrically realized by applying the ciphertext to the input and using the same key array and the complementary key array. In combination with the artificial intelligence calculation accelerator based on the cross point array ferroelectric capacitor array, high-density, high-energy-efficiency and data security enhanced in-memory calculation application can be realized.

The invention discloses a method for realizing PUF (Physical Unclonable Function) by using homomorphic write-in of an FRAM (Frequency Random Access Memory) of a 2T2C structure, which comprises the following steps of: firstly, carrying out independent write-in operation on two ferroelectric capacitors and writing same data, and carrying out homomorphic storage; then, the two ferroelectric capacitors are recovered to different residual polarization states by using the manufacturing difference of the ferroelectric capacitors; then applying a reverse level to enable the two ferroelectric capacitors to reach a saturated polarization state from a residual polarization state; and finally, comparing a difference value delta I of the polarization current responses of the two ferroelectric capacitors, and outputting a corresponding binary numerical value according to the difference value delta I and a set judgment condition, thereby generating a random PUF response. According to the invention, the PUF response with high randomness and uniqueness is generated through homomorphic storage of the 2T2C FRAM and by using the polarization characteristic of the ferroelectric material.

The invention provides an epitaxial hafnium oxide-based ferroelectric capacitor and an atomic layer deposition preparation method thereof, and the preparation method comprises the steps: providing a substrate layer, and depositing a zirconia epitaxial buffer layer on the substrate layer through employing an atomic layer deposition technology; forming a hafnium oxide-based epitaxial ferroelectric layer on the zirconium oxide epitaxial buffer layer by adopting an atomic layer deposition process; photoresist is spin-coated on the hafnium oxide-based epitaxial ferroelectric layer, exposure and development are carried out, and the shape of a top electrode is defined; preparing a top electrode on the hafnium oxide-based epitaxial ferroelectric layer; and annealing by adopting a rapid annealing process to realize the ferroelectricity of the hafnium oxide-based epitaxial ferroelectric layer. According to the application, the zirconium oxide epitaxial buffer layer is arranged between the ferroelectric layer and the substrate layer, so that the hafnium oxide-based epitaxial ferroelectric layer grown through ALD presents a highly oriented epitaxial lattice structure, the leakage current of the hafnium oxide-based ferroelectric capacitor can be reduced, and the cycle performance of the capacitor is improved.

The invention discloses a 2T2FC ferroelectric memory cell and a preparation method thereof, and the 2T2FC ferroelectric memory cell comprises a memory transistor; the source electrode of the control transistor is connected to the drain electrode of the storage transistor; one end of the first ferroelectric capacitor is connected with a first plate line, and the other end is coupled to the grid electrode of the storage transistor; one end of the second ferroelectric capacitor is connected with a second plate line, and the other end is coupled to the grid electrode of the storage transistor; a word line connected to the gate of the memory transistor; a bit line connected to the drain of the control transistor; a source line connected to the source of the memory transistor; a control line connected to the gate of the control transistor; the control transistor is configured to selectively enable or disable access to the memory transistor. By adopting one storage transistor and one control transistor, a storage path is separated from a control path, the reliability of data reading and writing is improved, meanwhile, the leakage current is reduced, and the memory is increased.

A memory device includes a substrate and vertically stacked ferroelectric capacitors formed on the substrate. A first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a constant voltage is applied. First and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors. In some cases, a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. The different thicknesses allow the capacitive output for each capacitor to produce different output electric fields. Accordingly, a combination of different output signals can be generated based on different threshold voltage levels for each capacitor contributing to the output.

Provided is a semiconductor device capable of reading data from a ferroelectric capacitor having a small amount of polarization. The semiconductor device includes first to fourth transistors, first and second capacitive elements, and first and second inverters. A first terminal of the first capacitive element is connected to a first terminal of each of the first and second transistors and to an input terminal of the first inverter. A first terminal of the second capacitive element is connected to a first terminal of each of the second and third transistors and to an input terminal of the second inverter. An output terminal of the first inverter is connected to a second terminal of each of the first and second transistors. An output terminal of the second inverter is connected to a second terminal of each of the third and fourth transistors. A gate of each of the first and third transistors is connected to first wiring. A gate of each of the second and fourth transistors is connected to second wiring.

The invention provides a ferroelectric capacitor and a preparation method thereof, the ferroelectric capacitor comprises a bottom electrode, a ferroelectric layer and a top electrode which are sequentially arranged from bottom to top, the ferroelectric layer is a lanthanum-doped hafnium zirconium oxide film prepared by an atomic layer deposition method, and the doping concentration of lanthanum in the lanthanum-doped hafnium zirconium oxide film is less than 1 at%. The ferroelectric capacitor can solve the problems that in the prior art, a ferroelectric capacitor based on an HZO cannot give consideration to a high k value and strong ferroelectricity, and is difficult to meet a low-power-consumption application scene.

The embodiment of the invention provides a memory array and a preparation method thereof, a memory and electronic equipment, relates to the technical field of semiconductors, and is used for reducing the power consumption of a ferroelectric memory. The memory array includes a substrate and a plurality of ferroelectric capacitors. The substrate comprises a first area and a plurality of second areas, and the first area is located between every two adjacent second areas. A plurality of ferroelectric capacitors are located on the plurality of second regions. The ferroelectric capacitor includes a first plate, a second plate, and a ferroelectric layer. The first pole plate extends along the thickness direction of the substrate. The second pole plate is located on the surface of the first pole plate away from the substrate. The ferroelectric layer is located between the second pole plate and the first pole plate. Wherein the second pole plates of the plurality of ferroelectric capacitors located on the same second area are connected to form plate lines, and the plate lines located on different second areas are arranged at intervals. The storage array is applied to the electronic equipment, and the performance of the electronic equipment is improved.

The present disclosure provides a ferroelectric memory and a data reading method and a data writing method thereof, and relates to the technical field of semiconductor technology, and is used to solve the technical problem of low storage density. The ferroelectric memory comprises a storage cell array, the storage cell array comprises a plurality of storage cells arranged in an array, each storage cell stores n-bit data, wherein each storage cell comprises a transistor and 2 n -1 ferroelectric capacitor coupled to the transistor, n is a positive integer greater than 1; a plurality of word lines, each word line is coupled to the storage cells arranged in a row in the storage cell array; a plurality of bit lines, each bit line is coupled to the storage cells arranged in a column in the storage cell array. The polarization direction of the 2 n -1 ferroelectric capacitor can determine 2 n a storage state, each storage state corresponds to one data, so that the 2 n -1 ferroelectric capacitor stores n-bit data, realizes the multi-state storage of the ferroelectric memory, and improves the storage density of the ferroelectric memory.

In accordance with at least one example of the description, a method comprises forming a substrate, and forming transducer elements over the substrate, each transducer element including a ferroelectric capacitor and a conductive element spaced from the ferroelectric capacitor by a dielectric material, the ferroelectric capacitor being between the conductive element and the substrate.

The present invention relates to a semiconductor memory device including a ferroelectric capacitor and a manufacturing method thereof, and more particularly, to a semiconductor memory device capable of preventing electrons from being captured in an interface layer (IL) by adding a ferroelectric capacitor to a location where an oxide filler is formed inside a channel structure and forming the ferroelectric capacitor between the channel structure and a bottom electrode, and a manufacturing method thereof.

The application discloses a PUF generating method and device based on a 2T2C structure FRAM, and belongs to the technical field of information security and storage. The method comprises the following steps: performing homomorphic writing on a first ferroelectric capacitor and a second ferroelectric capacitor in a target 2T2C FRAM memory unit, so that the two ferroelectric capacitors are in the same initial polarization state; performing two destructive reading operations on the two ferroelectric capacitors in the same initial polarization state, obtaining a first random number set corresponding to the first destructive reading and a second random number set corresponding to the second destructive reading; and performing fusion processing on the first random number set and the second random number set according to a nonlinear fusion mode, to generate a PUF response. The application can improve the complexity and stability of the PUF response.

This application provides a chip and its fabrication method, chip packaging structure, and electronic device, relating to the field of semiconductor technology. In this semiconductor structure, a ferroelectric capacitor is placed within the second dielectric layer of a first back-end trace layer. If the capacitance value of the ferroelectric capacitor meets the requirements, there is no need to add an additional sub-transfer layer. This eliminates the impact of the additional sub-transfer layer on the semiconductor structure performance (e.g., it can eliminate the impact of the additional sub-transfer layer on the signal transmission speed of logic circuits in the semiconductor structure). Even if the thickness of the first back-end trace layer cannot meet the capacitance requirement of the ferroelectric capacitor, and an additional sub-transfer layer is needed to increase the space for the ferroelectric capacitor, the additional sub-transfer layer only serves to supplement space, and its thickness is relatively thin, resulting in a relatively small impact on the semiconductor structure performance.

This application discloses a 2T2FC ferroelectric memory cell and its fabrication method. The 2T2FC ferroelectric memory cell includes: a storage transistor; a control transistor, the source of which is connected to the drain of the storage transistor; a first ferroelectric capacitor, one end of which is connected to a first plate line and the other end coupled to the gate of the storage transistor; a second ferroelectric capacitor, one end of which is connected to a second plate line and the other end coupled to the gate of the storage transistor; a word line connected to the gate of the storage transistor; a bit line connected to the drain of the control transistor; a source line connected to the source of the storage transistor; and a control line connected to the gate of the control transistor. The control transistor is configured to selectively enable or disable access to the storage transistor. This application achieves separation of the storage path and the control path by employing one storage transistor and one control transistor, improving the reliability of data read / write operations while reducing leakage current and increasing memory capacity.

A ferroelectric capacitor resisting fatigue, ferroelectric storage circuit, and ferroelectric memory thereof, the capacitor includes an upper electrode layer, a top electrode layer, a non-crystalline protective layer, a ferroelectric dielectric layer, and a bottom electrode layer in sequential order from top to bottom. The ferroelectric dielectric layer consists essentially of a fluorite-structure material selected from the group consisting of ZrO2, HfO2 and HfxZr1-xO2. The non-crystalline protective layer comprises a fluorite-structure base material and is doped with a predetermined amount of at least one element selected from the group consisting of Al, Si, La, Y, Nb, Ce, and Er, whereby the non-crystalline protective layer attains a non-crystalline state. The non-crystalline protective layer has a thickness ranging from 10% to 40% of a thickness of the ferroelectric dielectric layer. The capacitor exhibits enhanced fatigue resistance, preserved ferroelectric properties, reduced leakage current, simplified manufacturing processes, lower production costs, improved device reliability.

Methods, systems, and devices for switch and hold biasing for memory cell imprint recovery are described. A memory device may be configured to perform an imprint recovery procedure that includes applying one or more recovery pulses to memory cells, where each recovery pulse is associated with a voltage polarity and includes a first portion with a first voltage magnitude and a second portion with a second voltage magnitude that is lower than the first voltage magnitude. In some examples, the first voltage magnitude may correspond to a voltage that imposes a saturation polarization on a memory cell (e.g., on a ferroelectric capacitor, a polarization corresponding to the associated voltage polarity) and the second voltage magnitude may correspond to a voltage magnitude that is high enough to maintain the saturation polarization (e.g., to prevent a reduction of polarization) of the memory cell.

The present disclosure relates to a non-volatile content-addressable memory based on ferroelectric capacitors and an electronic device. The memory includes: a plurality of storage cells, each of which comprises: a first switch and a second switch connected to a first capacitor and a second capacitor, respectively; a first capacitor and a third capacitor, and a gate of a first transistor, all connected to a first node; a second capacitor and a fourth capacitor, and a gate of a second transistor, all connected to a second node; at least one of the first and third capacitors is a ferroelectric capacitor, and at least one of the second and fourth capacitors is a ferroelectric capacitor; and a control unit for inputting a control signal to control the storage cell to perform a target operation. The disclosed embodiments achieve non-destructive reading of data, improve the service life of the memory, and reduce operation delays and energy consumption.

This invention discloses a method and apparatus for awakening the polarization of a large-area ferroelectric capacitor at the wafer level. The wafer consists of a bottom electrode, a ferroelectric layer, and a patterned, independent top electrode array stacked sequentially from bottom to top. The bottom electrode is electrically connected to one end of a pulse voltage generator, and the conductive film on the surface of a flexible conductive roller is electrically connected to the other end of the pulse voltage generator. By controlling the horizontal movement of the wafer stage, the flexible conductive roller is driven to roll and contact the surface of the top electrode array; simultaneously, a preset pulse voltage is applied between the bottom electrode and the conductive film using the pulse voltage generator, increasing the ferroelectric remanent polarization intensity of the ferroelectric film covered by the top electrode in the contact area, thus achieving ferroelectric polarization awakening. This invention, after a high-temperature heat treatment at over 200°C, efficiently and over a large area awakens the polarization of the ferroelectric film corresponding to the top electrode array, ensuring high stability and consistency in its ferroelectric remanent polarization intensity.

The invention discloses a preparation method of an HfO2-based ferroelectric film with gradient oxygen vacancy distribution as well as the film and application of the HfO2-based ferroelectric film. The method comprises the steps that a lower electrode is prepared on a substrate, an amorphous HfO2-based prefabricated film is deposited on the lower electrode through atomic layer deposition, an upper electrode is prepared on the prefabricated film to form a sandwich stacking structure, and crystallization annealing is carried out to induce the prefabricated film to be crystallized into a ferroelectric orthorhombic phase; wherein the atomic layer deposition comprises at least one oxidant modulation period, a first deposition stage and a second deposition stage with different oxidation capacities are alternately carried out, and the oxygen content and oxygen vacancy defect distribution are regulated and controlled in the film thickness direction through the combination of sub-cycles, so that the oxygen vacancy concentration on one side close to the lower electrode and the upper electrode is lower than that in the middle area of the film. The obtained film can be applied to devices such as ferroelectric capacitors and ferroelectric field effect transistors, and is used for improving polarization output, reducing electric leakage and improving consistency and reliability of the devices.

The invention provides a ferroelectric memory, a preparation method thereof and electronic equipment. The ferroelectric memory comprises a substrate and a plurality of memory cells formed on the substrate, wherein each memory cell comprises a ferroelectric capacitor; the ferroelectric capacitor comprises a first electrode and a second electrode which are stacked, and a ferroelectric layer; the ferroelectric layer comprises at least one of hafnium oxide and zirconium oxide and doping elements; the electronegativity of the doping elements is less than that of oxygen, such as sulfur, selenium and tellurium. Therefore, anions formed by doping the elements into the ferroelectric layer are easier to displace under the action of an electric field, the electric polarization state is easier to overturn, the coercive electric field of the ferroelectric film is reduced, and meanwhile, a rectangular ferroelectric hysteresis loop can be maintained, so that the working voltage of the ferroelectric memory device can be reduced, and the anti-interference capability can be improved.

The invention discloses an oxide channel aluminum scandium nitrogen ferroelectric thin film transistor memory which comprises a drain end electrode, an oxide semiconductor channel layer, an oxide dielectric layer, a source end electrode, a floating gate metal layer, a ferroelectric dielectric layer and a control end electrode. The floating gate metal layer is located on the substrate, the oxide dielectric layer and the ferroelectric layer are located on the floating gate metal layer and are isolated from each other, and the ferroelectric layer is an aluminum scandium nitrogen ferroelectric film; the oxide semiconductor channel layer is located on the oxide dielectric layer, and the drain end electrode and the source end electrode are arranged on the oxide semiconductor channel layer; the control end electrode is arranged on the ferroelectric dielectric layer to form a ferroelectric capacitor, and the control end electrode is used for applying a pulse or a direct current signal to control the polarization direction of the ferroelectric dielectric layer and regulate and control the carrier concentration of the oxide semiconductor channel layer, so that the threshold voltage of the device is regulated and controlled, and the purpose of storing data is achieved.