159 results about "Ferroelectric capacitor" patented technology

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

The invention relates to the technical field of nonvolatile memories, in particular to a 2T1FC ferroelectric memory cell with a memory gate line and a preparation method of the 2T1FC ferroelectric memory cell. The 2T1FC ferroelectric storage unit with the storage gate line comprises a ferroelectric capacitor and a storage transistor which realizes read-write operation of data through polarization modulation of the ferroelectric capacitor; the control transistor is used for enabling a bit line to perform gating access; and the storage gate line is used for controlling the gate of the storage transistor and improving the holding capability of the written data. According to the invention, the special storage gate line is used, so that self-charge dissipation after writing is prevented, and the non-volatility is enhanced; separation of the storage path and the control path minimizes accidental flipping in the read / write cycle; the service life of the device is prolonged by lower write-in current stress and an isolated gate structure; low-voltage writing with high retentivity can be realized, and the method is suitable for energy-limited edge AI equipment.

The invention belongs to the field of microelectronics, and particularly relates to a ferroelectric capacitor, a preparation method thereof and a three-dimensional ferroelectric memory array, and the ferroelectric capacitor comprises a substrate, a bottom electrode, a ferroelectric dielectric layer, a deoxidizing layer and a top electrode which are sequentially arranged from bottom to top; the ferroelectric medium layer is an Hf < 1-x > Zr < x > O < 2 > layer, 0 lt; xlt; the Hf-rich composition is realized by controlling the Hf: Zr super-cycle ratio of atomic layer deposition; the thickness of the ferroelectric medium layer is 1-6 nm, and the thickness of the bottom electrode is 0.1-5 nm. Compared with the prior art, the problems of polarization characteristic degradation caused by thinning of the ferroelectric layer in the hafnium-based ferroelectric capacitor and crosstalk in the FeRAM in the prior art are solved. According to the scheme, the oxygen vacancy concentration is accurately adjusted to inhibit the formation of a non-ferroelectric phase, so that the ultra-thin ferroelectric film can still maintain relatively high remanent polarization while the size is reduced, a storage window is effectively improved, and the wake-up requirement is reduced.

The invention belongs to the field of microelectronics, and particularly relates to a ferroelectric capacitor for improving initial state polarization intensity and a preparation method and application thereof.The ferroelectric capacitor comprises a substrate, a bottom electrode, an ultrathin ferroelectric medium layer and a top electrode which are sequentially stacked from bottom to top; the ultra-thin ferroelectric dielectric layer is an Hf < 1-x > Zr < x > O < 2 > thin film, 0 lt; xlt; and in the atomic layer deposition process, the Hf-rich thin film is grown and formed by controlling the Hf: Zr super-cycle ratio. Compared with the prior art, the ferroelectric capacitor solves the problems that in the prior art, in order to improve the initial-state polarization intensity of the ferroelectric capacitor, a function matched with the HZO thin film is added, the thickness is increased due to layers, and the improvement effect is limited. According to the scheme, the doping proportion of Hf in the ultra-thin ferroelectric dielectric layer is properly increased, the formation energy of a non-ferroelectric T phase is remarkably improved, stable existence of a ferroelectric O phase is further promoted, and therefore the ferroelectric O phase with ferroelectric hysteresis close to the situation that awakening is not needed, a high initial state 2Pr value and a high content is achieved.

The invention discloses a method for realizing PUF (Physical Unclonable Function) by using homomorphic write-in of an FRAM (Frequency Random Access Memory) of a 2T2C structure, which comprises the following steps of: firstly, carrying out independent write-in operation on two ferroelectric capacitors and writing same data, and carrying out homomorphic storage; then, the two ferroelectric capacitors are recovered to different residual polarization states by using the manufacturing difference of the ferroelectric capacitors; then applying a reverse level to enable the two ferroelectric capacitors to reach a saturated polarization state from a residual polarization state; and finally, comparing a difference value delta I of the polarization current responses of the two ferroelectric capacitors, and outputting a corresponding binary numerical value according to the difference value delta I and a set judgment condition, thereby generating a random PUF response. According to the invention, the PUF response with high randomness and uniqueness is generated through homomorphic storage of the 2T2C FRAM and by using the polarization characteristic of the ferroelectric material.

The invention provides an epitaxial hafnium oxide-based ferroelectric capacitor and an atomic layer deposition preparation method thereof, and the preparation method comprises the steps: providing a substrate layer, and depositing a zirconia epitaxial buffer layer on the substrate layer through employing an atomic layer deposition technology; forming a hafnium oxide-based epitaxial ferroelectric layer on the zirconium oxide epitaxial buffer layer by adopting an atomic layer deposition process; photoresist is spin-coated on the hafnium oxide-based epitaxial ferroelectric layer, exposure and development are carried out, and the shape of a top electrode is defined; preparing a top electrode on the hafnium oxide-based epitaxial ferroelectric layer; and annealing by adopting a rapid annealing process to realize the ferroelectricity of the hafnium oxide-based epitaxial ferroelectric layer. According to the application, the zirconium oxide epitaxial buffer layer is arranged between the ferroelectric layer and the substrate layer, so that the hafnium oxide-based epitaxial ferroelectric layer grown through ALD presents a highly oriented epitaxial lattice structure, the leakage current of the hafnium oxide-based ferroelectric capacitor can be reduced, and the cycle performance of the capacitor is improved.

The invention discloses a 2T2FC ferroelectric memory cell and a preparation method thereof, and the 2T2FC ferroelectric memory cell comprises a memory transistor; the source electrode of the control transistor is connected to the drain electrode of the storage transistor; one end of the first ferroelectric capacitor is connected with a first plate line, and the other end is coupled to the grid electrode of the storage transistor; one end of the second ferroelectric capacitor is connected with a second plate line, and the other end is coupled to the grid electrode of the storage transistor; a word line connected to the gate of the memory transistor; a bit line connected to the drain of the control transistor; a source line connected to the source of the memory transistor; a control line connected to the gate of the control transistor; the control transistor is configured to selectively enable or disable access to the memory transistor. By adopting one storage transistor and one control transistor, a storage path is separated from a control path, the reliability of data reading and writing is improved, meanwhile, the leakage current is reduced, and the memory is increased.

Provided is a semiconductor device capable of reading data from a ferroelectric capacitor having a small amount of polarization. The semiconductor device includes first to fourth transistors, first and second capacitive elements, and first and second inverters. A first terminal of the first capacitive element is connected to a first terminal of each of the first and second transistors and to an input terminal of the first inverter. A first terminal of the second capacitive element is connected to a first terminal of each of the second and third transistors and to an input terminal of the second inverter. An output terminal of the first inverter is connected to a second terminal of each of the first and second transistors. An output terminal of the second inverter is connected to a second terminal of each of the third and fourth transistors. A gate of each of the first and third transistors is connected to first wiring. A gate of each of the second and fourth transistors is connected to second wiring.

The invention provides a ferroelectric capacitor and a preparation method thereof, the ferroelectric capacitor comprises a bottom electrode, a ferroelectric layer and a top electrode which are sequentially arranged from bottom to top, the ferroelectric layer is a lanthanum-doped hafnium zirconium oxide film prepared by an atomic layer deposition method, and the doping concentration of lanthanum in the lanthanum-doped hafnium zirconium oxide film is less than 1 at%. The ferroelectric capacitor can solve the problems that in the prior art, a ferroelectric capacitor based on an HZO cannot give consideration to a high k value and strong ferroelectricity, and is difficult to meet a low-power-consumption application scene.

The embodiment of the invention provides a memory array and a preparation method thereof, a memory and electronic equipment, relates to the technical field of semiconductors, and is used for reducing the power consumption of a ferroelectric memory. The memory array includes a substrate and a plurality of ferroelectric capacitors. The substrate comprises a first area and a plurality of second areas, and the first area is located between every two adjacent second areas. A plurality of ferroelectric capacitors are located on the plurality of second regions. The ferroelectric capacitor includes a first plate, a second plate, and a ferroelectric layer. The first pole plate extends along the thickness direction of the substrate. The second pole plate is located on the surface of the first pole plate away from the substrate. The ferroelectric layer is located between the second pole plate and the first pole plate. Wherein the second pole plates of the plurality of ferroelectric capacitors located on the same second area are connected to form plate lines, and the plate lines located on different second areas are arranged at intervals. The storage array is applied to the electronic equipment, and the performance of the electronic equipment is improved.

The present disclosure provides a ferroelectric memory and a data reading method and a data writing method thereof, and relates to the technical field of semiconductor technology, and is used to solve the technical problem of low storage density. The ferroelectric memory comprises a storage cell array, the storage cell array comprises a plurality of storage cells arranged in an array, each storage cell stores n-bit data, wherein each storage cell comprises a transistor and 2 n -1 ferroelectric capacitor coupled to the transistor, n is a positive integer greater than 1; a plurality of word lines, each word line is coupled to the storage cells arranged in a row in the storage cell array; a plurality of bit lines, each bit line is coupled to the storage cells arranged in a column in the storage cell array. The polarization direction of the 2 n -1 ferroelectric capacitor can determine 2 n a storage state, each storage state corresponds to one data, so that the 2 n -1 ferroelectric capacitor stores n-bit data, realizes the multi-state storage of the ferroelectric memory, and improves the storage density of the ferroelectric memory.

In accordance with at least one example of the description, a method comprises forming a substrate, and forming transducer elements over the substrate, each transducer element including a ferroelectric capacitor and a conductive element spaced from the ferroelectric capacitor by a dielectric material, the ferroelectric capacitor being between the conductive element and the substrate.

The application discloses a PUF generating method and device based on a 2T2C structure FRAM, and belongs to the technical field of information security and storage. The method comprises the following steps: performing homomorphic writing on a first ferroelectric capacitor and a second ferroelectric capacitor in a target 2T2C FRAM memory unit, so that the two ferroelectric capacitors are in the same initial polarization state; performing two destructive reading operations on the two ferroelectric capacitors in the same initial polarization state, obtaining a first random number set corresponding to the first destructive reading and a second random number set corresponding to the second destructive reading; and performing fusion processing on the first random number set and the second random number set according to a nonlinear fusion mode, to generate a PUF response. The application can improve the complexity and stability of the PUF response.

This application provides a chip and its fabrication method, chip packaging structure, and electronic device, relating to the field of semiconductor technology. In this semiconductor structure, a ferroelectric capacitor is placed within the second dielectric layer of a first back-end trace layer. If the capacitance value of the ferroelectric capacitor meets the requirements, there is no need to add an additional sub-transfer layer. This eliminates the impact of the additional sub-transfer layer on the semiconductor structure performance (e.g., it can eliminate the impact of the additional sub-transfer layer on the signal transmission speed of logic circuits in the semiconductor structure). Even if the thickness of the first back-end trace layer cannot meet the capacitance requirement of the ferroelectric capacitor, and an additional sub-transfer layer is needed to increase the space for the ferroelectric capacitor, the additional sub-transfer layer only serves to supplement space, and its thickness is relatively thin, resulting in a relatively small impact on the semiconductor structure performance.

This application discloses a 2T2FC ferroelectric memory cell and its fabrication method. The 2T2FC ferroelectric memory cell includes: a storage transistor; a control transistor, the source of which is connected to the drain of the storage transistor; a first ferroelectric capacitor, one end of which is connected to a first plate line and the other end coupled to the gate of the storage transistor; a second ferroelectric capacitor, one end of which is connected to a second plate line and the other end coupled to the gate of the storage transistor; a word line connected to the gate of the storage transistor; a bit line connected to the drain of the control transistor; a source line connected to the source of the storage transistor; and a control line connected to the gate of the control transistor. The control transistor is configured to selectively enable or disable access to the storage transistor. This application achieves separation of the storage path and the control path by employing one storage transistor and one control transistor, improving the reliability of data read / write operations while reducing leakage current and increasing memory capacity.

Methods, systems, and devices for switch and hold biasing for memory cell imprint recovery are described. A memory device may be configured to perform an imprint recovery procedure that includes applying one or more recovery pulses to memory cells, where each recovery pulse is associated with a voltage polarity and includes a first portion with a first voltage magnitude and a second portion with a second voltage magnitude that is lower than the first voltage magnitude. In some examples, the first voltage magnitude may correspond to a voltage that imposes a saturation polarization on a memory cell (e.g., on a ferroelectric capacitor, a polarization corresponding to the associated voltage polarity) and the second voltage magnitude may correspond to a voltage magnitude that is high enough to maintain the saturation polarization (e.g., to prevent a reduction of polarization) of the memory cell.

This invention discloses a method and apparatus for awakening the polarization of a large-area ferroelectric capacitor at the wafer level. The wafer consists of a bottom electrode, a ferroelectric layer, and a patterned, independent top electrode array stacked sequentially from bottom to top. The bottom electrode is electrically connected to one end of a pulse voltage generator, and the conductive film on the surface of a flexible conductive roller is electrically connected to the other end of the pulse voltage generator. By controlling the horizontal movement of the wafer stage, the flexible conductive roller is driven to roll and contact the surface of the top electrode array; simultaneously, a preset pulse voltage is applied between the bottom electrode and the conductive film using the pulse voltage generator, increasing the ferroelectric remanent polarization intensity of the ferroelectric film covered by the top electrode in the contact area, thus achieving ferroelectric polarization awakening. This invention, after a high-temperature heat treatment at over 200°C, efficiently and over a large area awakens the polarization of the ferroelectric film corresponding to the top electrode array, ensuring high stability and consistency in its ferroelectric remanent polarization intensity.

The invention discloses a preparation method of an HfO2-based ferroelectric film with gradient oxygen vacancy distribution as well as the film and application of the HfO2-based ferroelectric film. The method comprises the steps that a lower electrode is prepared on a substrate, an amorphous HfO2-based prefabricated film is deposited on the lower electrode through atomic layer deposition, an upper electrode is prepared on the prefabricated film to form a sandwich stacking structure, and crystallization annealing is carried out to induce the prefabricated film to be crystallized into a ferroelectric orthorhombic phase; wherein the atomic layer deposition comprises at least one oxidant modulation period, a first deposition stage and a second deposition stage with different oxidation capacities are alternately carried out, and the oxygen content and oxygen vacancy defect distribution are regulated and controlled in the film thickness direction through the combination of sub-cycles, so that the oxygen vacancy concentration on one side close to the lower electrode and the upper electrode is lower than that in the middle area of the film. The obtained film can be applied to devices such as ferroelectric capacitors and ferroelectric field effect transistors, and is used for improving polarization output, reducing electric leakage and improving consistency and reliability of the devices.

The invention discloses an oxide channel aluminum scandium nitrogen ferroelectric thin film transistor memory which comprises a drain end electrode, an oxide semiconductor channel layer, an oxide dielectric layer, a source end electrode, a floating gate metal layer, a ferroelectric dielectric layer and a control end electrode. The floating gate metal layer is located on the substrate, the oxide dielectric layer and the ferroelectric layer are located on the floating gate metal layer and are isolated from each other, and the ferroelectric layer is an aluminum scandium nitrogen ferroelectric film; the oxide semiconductor channel layer is located on the oxide dielectric layer, and the drain end electrode and the source end electrode are arranged on the oxide semiconductor channel layer; the control end electrode is arranged on the ferroelectric dielectric layer to form a ferroelectric capacitor, and the control end electrode is used for applying a pulse or a direct current signal to control the polarization direction of the ferroelectric dielectric layer and regulate and control the carrier concentration of the oxide semiconductor channel layer, so that the threshold voltage of the device is regulated and controlled, and the purpose of storing data is achieved.

The present disclosure relates to memory cells and arrays of memory cells. A memory cell includes first, second, third, and fourth transistors individually including a transistor gate. First and second ferroelectric capacitors individually have a capacitor electrode vertically interposed between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.

The invention provides a storage circuit, a memory and electronic equipment. Relates to the technical field of data storage. The memory circuit comprises a first electrode line (such as a word line WL), a second electrode line (such as a bit line BL), a plurality of third electrode lines (such as a plate line PL), and a plurality of memory cells, each storage unit comprises a transistor and a plurality of branches, and a control end (such as a gate) of the transistor is electrically connected with the first electrode wire; the first end (such as source) of the transistor is electrically connected with the second electrode wire; one end of each branch circuit is electrically connected with the third electrode wire, and the other end of each branch circuit is electrically connected with a second end (such as a drain electrode Drain) of the transistor; wherein each branch comprises a ferroelectric capacitor and a bidirectional selection device which are connected in series. According to the application, the bidirectional selection device is connected in series with the ferroelectric capacitor, so that the influence on the data stored in the unselected ferroelectric capacitor can be weakened.

The invention relates to a modeling method of a ferroelectric field effect transistor, and relates to the technical field of memories. Comprising the following steps: constructing a classical ferroelectric Preisach model to calculate an effective polarization value of a ferroelectric film; introducing a polarization relaxation time parameter tau, and establishing a differential relationship between the external voltage and the effective voltage of the ferroelectric capacitor, so as to establish a ferroelectric polarization dynamic model; and on the basis of the model, constructing electrical modeling of the ferroelectric field effect transistor. According to the method, the polarization relaxation time parameter tau is introduced into the Preisach model, the dynamic change of ferroelectric polarization is more accurately reflected, and the change rule of the storage window of the ferroelectric field effect transistor device after the grid pulse signal is written can be better predicted, so that the working voltage can be guided to be optimized, and the writing reliability of a memory is improved.

The invention provides a method for realizing a self-gating linear unit function based on a programmable field effect transistor and a ferroelectric capacitor, and belongs to the field of large model accelerators. According to the method, Swsh or GELU activation of an input voltage is realized by using a response charge-voltage relationship between a pre-programmed programmable field effect transistor and a ferroelectric capacitor, and a response charge is linearly converted into an output voltage representing an activation value by using a charge-voltage conversion module; and a mainstream self-gating linear unit activation function in the large model is realized in a simulation domain. According to the method, the analog / digital conversion overhead of a computing system in a simulation domain memory is reduced, and the realization of a high-energy-efficiency large-model accelerator is facilitated.

Memory device with series-connected ferroelectric transistor and capacitor, associated electronic circuit, programming method and reading method. The present invention relates to a memory device (14) comprising: - a ferroelectric field-effect transistor (20) having a gate electrode (21) and first (22) and second (23) conduction electrodes; - a ferroelectric capacitor (25) having first (27) and second (28) charge electrodes; the transistor (20) and the ferroelectric capacitor (25) being connected according to a first connection configuration (C1) in which the first conduction electrode (22) is connected to a reference potential (GND) and the second conduction electrode (23) is connected to the first charge electrode (27);or according to a second connection configuration in which the first conduction electrode (22) is connected to the first charging electrode (27) and the second conduction electrode (23) is connected to the second charging electrode (28). Figure for the abbreviation: Figure 2;

The invention belongs to the technical field of ferroelectric storage, and particularly relates to an ultra-thin HfO2-based ferroelectric capacitor and a preparation method and application thereof, and the ultra-thin HfO2-based ferroelectric capacitor comprises a bottom conductive electrode layer, a bottom ultra-thin metal layer, a ferroelectric dielectric layer, a top ultra-thin metal layer, a top conductive electrode layer and a mask layer, the thermal expansion coefficient of a metal material adopted by the bottom ultra-thin metal layer is smaller than that of a dielectric material adopted by the ferroelectric dielectric layer; the thermal expansion coefficient of a metal material adopted by the top ultra-thin metal layer is smaller than that of a dielectric material adopted by the ferroelectric dielectric layer. Compared with the prior art, the problem that ferroelectricity and reliability are reduced due to the fact that a depolarization field is generated by an interface oxide layer (interface layer) between the insertion layer / electrode and the ferroelectric medium layer in the prior art is solved. According to the scheme, the enhanced ferroelectricity without wakeup is realized, and meanwhile, the operation voltage is reduced.

The invention provides a non-destructive data reading method for a ferroelectric memory, and relates to the technical field of semiconductor memories, and the method comprises the steps: S1, applying a subthreshold reading voltage; s2, detecting a polarization response signal; s3, comparing and judging a logic state; the method has thorough non-destructiveness, the polarization direction of the ferroelectric capacitor cannot be overturned in the whole read operation process, and original storage data can be completely reserved. The write-back operation necessary for the traditional method is fundamentally eliminated. Delay and power consumption can be reduced, energy consumed by write-back operation is avoided, and dynamic power consumption is remarkably reduced; the read-write service life of the ferroelectric memory is greatly prolonged; and the design flexibility and robustness are improved.

The invention provides a preparation method of a wurtzite ferroelectric capacitor and the wurtzite ferroelectric capacitor, and the method comprises the steps: carrying out the photoetching of the front surface of a substrate, depositing an electrode material to form a bottom electrode layer, and forming a patterned bottom electrode through a stripping technology; depositing a wurtzite ferroelectric layer on the front surface of the laminated structure formed in the previous step; after photoetching is carried out on the front face of the wurtzite ferroelectric layer, an electrode material is deposited to form a top electrode layer, a patterned top electrode is formed through a stripping process, and the thickness of a photoresist layer formed after photoetching is larger than the thickness of the top electrode layer and the thickness of a bottom electrode layer; the problems of bottom electrode damage, interface defects, high leakage current and the like caused by excessive etching of the wurtzite ferroelectric layer can be avoided.

An operating method of a memory device including a ferroelectric memory cell is disclosed. The method comprises the following steps: receiving a read command and an address from a controller; and performing a read operation on the ferroelectric memory cell corresponding to the address based on the first read mode or the second read mode according to the read command. In a first read mode, a first read voltage is applied as a voltage across a ferroelectric capacitor included in a ferroelectric memory cell. In a second read mode, a second read voltage is applied as a voltage across a ferroelectric capacitor included in the ferroelectric memory cell. The first read voltage and the second read voltage have opposite polarities.

The invention provides a defect information extraction method for a ferroelectric capacitor dielectric layer. The method comprises the following steps: carrying out polarization state overturning for a preset number of times on a to-be-detected ferroelectric capacitor; step voltages which are gradually increased according to a preset step length are applied to the two ends of the to-be-measured ferroelectric capacitor, and the leakage current of the to-be-measured ferroelectric capacitor under each step voltage is obtained; determining a related response region of each leakage current according to the leakage current of each step voltage; and determining the defect concentration of all the related response regions, and performing assignment processing on the related response regions according to the defect concentration to obtain defect information of the to-be-detected ferroelectric capacitor. According to the invention, the leakage current of the ferroelectric capacitor under the gradually increased step voltage is detected, the change of the related response region where the defect is located in the complete voltage application process of the ferroelectric capacitor is analyzed, and the related response region is subjected to assignment processing in combination with the defect concentration; and the contribution degree of the defect of each related response region to the leakage current is obtained, and the purpose of more completely analyzing the failure behavior of the device is achieved.

The embodiment of the invention discloses a memory array and a preparation method thereof, a memory and electronic equipment, and relates to the technical field of semiconductors. The memory array includes a ferroelectric capacitor. A ferroelectric capacitor includes a first electrode layer, a second electrode layer, a first ferroelectric layer, a first electric dipole intercalation, and an electron injection intercalation. The second electrode layer and the first electrode layer are arranged oppositely. The first ferroelectric layer is located between the first electrode layer and the second electrode layer. The first electric dipole intercalation layer is located between the first ferroelectric layer and the second electrode layer. The electron injection intercalation is located between the first ferroelectric layer and the first electric dipole intercalation. The resistivity of the material of the electron injection intercalation is less than the resistivity of the material of the first electric dipole intercalation. On the basis of increasing a storage window and reducing operation voltage and power consumption by utilizing the first electric dipole intercalation layer, a large number of free electrons can be introduced by utilizing the electron injection intercalation layer, so that the imprint impression of the storage array and the memory applying the storage array is improved, and the characteristics and durability are maintained.