422 results about "Cell block" patented technology

A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.

A method and apparatus for embedding cells that utilizes a flow-through embedding technique maximizes the efficiency of extractions and decreases time for embedding the cell fragments, minimizes cell loss, and automatically positions cell samples at the position in which a microtome blade will section them. The apparatus includes a cell flow pathway defined by an inflow tube for delivering cell fragments from a cell sample to a sample port. The sample port is in fluid communication with a tissue cassette having attached thereto a filter. The cell flow pathway is in communication with a reagent flow pathway for delivering the reagents through the sample port to the cassette. The apparatus is configured such that the application of pressure directs the cell fragments from the cell sample through the cell flow pathway, and effects delivery of the reagents through the reagent flow pathway. The apparatus produces an embedded cell block having concentrated cells near the plane of the block to be sectioned in a quick and efficient manner.

Provided is directed to a NAND flash memory device and a method of programming the same, which can improve integration of the device by removing a common source line connecting with a source line coupled to a plurality of cell blocks, control a voltage applied to a source line by each cell block, and rise a precharge level in a channel area by applying a pumping voltage to the source line relatively having low capacitance instead of a bitline having a large capacitance, and as a result of those, the NAND flash memory device can reduce disturbance, use a lower voltage than a power supply voltage on the bitline, which leads to reduce a current consumption.

A memory includes a first cell block comprising a plurality of first word lines and one or more first redundancy word lines for replacing at least one of the plurality of first word lines; a second cell block comprising a plurality of second word lines and one or more second redundancy word lines for replacing at least one of the plurality of second word lines; and a control unit suitable for sequentially receiving one or more input addresses, during a target refresh section, selecting one of the first cell block and the second cell block and a word line included in the selected cell block in response to a first input address, and activating one or more adjacent word lines adjacent to the selected word line, which is selected based on the first input address, when the selected word line is adjacent to the redundancy word line, wherein the adjacent word lines comprise the redundancy word line.

A method of performing a write operation in a nonvolatile memory device comprises storing write data in a log block used to update a data block, determining whether a write pattern stored in the log block is a sequential write pattern or a random write pattern, and selecting a new data block for storing merged data in the data block and the log block. The new data block is determined to be a single-level cell block or a multi-level cell block according to the determined write pattern.

The present invention relates to a light emitting device. The light emitting device according to the present invention comprises a light emitting cell block having a plurality of light emitting cells; and a bridge rectifying circuit connected to input and output terminals of the light emitting cell block, wherein the bridge rectifying circuit includes a plurality of diodes between nodes. In manufacturing an AC light emitting device with a bridge rectifying circuit built therein, the present invention can provide a light emitting device capable of enhancing the reliability and luminance of the light emitting device by setting the size of diodes of the bridge rectifying circuit to be a certain size and controlling the number thereof.

An assembled battery system includes an assembled battery including a plurality of electric cell blocks connected in series, the electric cell blocks each including at least one nonaqueous electrolyte secondary battery provided with a negative electrode current collector formed of aluminum or an aluminum alloy, a voltage measuring unit configured to measure a plurality of voltages of the electric cell blocks, a controller which controls charge/discharge of the assembled battery in accordance with the measured voltages, and bypass circuits connected in parallel to the electric cell blocks, the bypass circuits each bypassing a current that flows from a negative electrode of one of the electric cell blocks to a positive electrode of the one of electric cell blocks when the measured voltage of the one of electric cell blocks is a negative value not greater than a threshold value.

In an electrical instrument to which a plurality of battery blocks and/or a plurality of batteries are detachably connectable, to prevent a phenomenon that only specific battery and battery block are deteriorated. A hybrid battery connectable to a body of an electrical instrument consuming electrical power includes: a cell block which includes one or more battery cells, and supplies electrical power to the body of the electrical instrument by discharging after being charged; and a cell block which includes one or more battery cells, supplies electrical power to the body of the electrical instrument by discharging after being charged, and becomes active selectively with the former cell block. In the hybrid battery, a CPU selects a cell block becoming active based on the number of charge/discharge cycles of the former cell block and the number of charge/discharge cycles of the latter cell block.

According to an aspect of the invention, there is provided a nonvolatile ferroelectric memory, including a ferroelectric capacitor composed of a ferroelectric film sandwiched by capacitor electrodes made of a conductive material, a cell capacitor block stacked a plurality of the capacitor electrodes and the ferroelectric film of the ferroelectric capacitor perpendicular to a main surface of a silicon substrate in layer, a cell transistor having a drain electrode and a source electrode, the drain electrode and the source electrode are electrically connected to the ferroelectric capacitor in parallel, a memory cell composed of the ferroelectric capacitor and the cell transistor, a cell block having the plurality of memory cells electrically connected in series, the drain electrode and the source electrode being as a terminals, a word line, a bit line connected to one end of the cell block, the bit line being arranged along orthogonal direction to the word line and a plate line connected to the other end of the cell block, the plate line arranged along the word line.

Providing a charge condition adjusting apparatus, which can shorten a time for equalization of each charge in unit cells, a low-voltage CPU selects each smallest unit cell in the each cell block, which has each smallest voltage between the both electrodes, from among plural unit cells structuring the cell blocks. The low-voltage CPU controls ON/OFF of a block-discharging switch to connect the both electrodes of each cell block and each block-discharging resistor for discharging the each cell block until the each voltage between the both electrodes of the selected smallest unit cell reaches the target voltage. Successively, the low-voltage CPU controls ON/OFF of a selecting switches and a cell-discharging switch to connect the both electrodes of each unit cell and each cell-discharging resistor to discharge the each unit cell until the each voltage between the both electrodes of the unit cells reaches the target voltage.

A semiconductor memory device including an array with a first memory cell block having redundancy blocks and a second memory cell block having normal blocks. A redundancy block in the first memory cell block is substituted for a defective normal block in the second memory cell block. The substitution is performed by a block selection circuit. When substitution is required, the block selection circuit selects from among the first memory cell blocks in inverse order, beginning with the first memory cell block having the highest address. First memory cell blocks that are not substituted for defective cell blocks are used as normal memory cell blocks by the block selection circuit.

A method of forming fine patterns of a semiconductor device, in which a plurality of conductive lines formed in a cell array region are integrally formed with contact pads for connecting the conductive lines to a peripheral circuit. In this method, a plurality of mold mask patterns, each including a first portion extending in a first direction and a second portion which is integrally formed with the first portion and extends in a second direction, are formed within a cell block on a substrate comprising a film which is to be etched. A first mask layer covering sidewalls and an upper surface of each of the plurality of mold mask patterns is formed on the substrate. First mask patterns are formed by partially removing the first mask layer so that a first area of the first mask layer remains and a second area of the first mask layer is removed. The first area of the first mask layer covers sidewalls of adjacent mold mask patterns from among the plurality of mold mask patterns by being located between the adjacent mold mask patterns, and the second area of the first mask layer covers portions of the sidewalls of the plurality of mold mask patterns, the portions corresponding to an outermost sidewall of a mold mask pattern block.

The present invention provides a light emitting device comprising a first semiconductor substrate including a light emitting cell block having a plurality of light emitting cells connected in series on one surface thereof; a second semiconductor substrate having one surface formed with a rectifying bridge and the other surface bonded to the other surface of the first semiconductor substrate; and a submount substrate to which the second semiconductor substrate is flip-chip bonded to be in contact with the one surface of the second semiconductor substrate, wherein rectified power is applied to the light emitting cell block through the rectifying bridge. The present invention further provides a method of manufacturing the light emitting device. The light emitting device and the method of manufacturing the same according to the present invention have advantages in that a flicker effect generated from an AC power source can be minimized and constant brightness can be maintained even in changes in the voltage of the AC power source by integrating a rectifying circuit into a light emitting device with a flip-chip structure, and in that there is no cumbersomeness of mounting an additional auxiliary device, resulting in increase of the degree of utilization of space and improved light output.

The invention belongs to the field of image recognition processing. The invention relates to a self-adaptive intelligent document recognition and input device and a use method thereof. A data acquisition module acquires a paper text of a client into a picture file through scanning or shooting, the preprocessing module carries out block processing on the text in an image by utilizing a morphological processing algorithm, lattices in each line or table are made into unequal cell blocks, and the character recognition module carries out binary processing on each cell block; Then, the correlation analysis module performs correlation analysis according to a pre-configured keyword and a pre-configured rule; According to the technical scheme, the relation between text blocks is analyzed, a data extraction module is guided to extract needed field content, a deviation rectification module can perform verification and automatic correction on the extracted content according to previous identification and deviation rectification historical data, and finally a result is stored and returned to a calling party. The system is ingenious in design concept, safe and convenient to use, high in intelligent degree, high in recognition accuracy, friendly to application environment and wide in market prospect.

There is provided a synchronous memory device having a simplified data input unit for receiving and transferring data to an internal memory cell block, which is adapted to high frequency and can reduce a power consumption. The synchronous memory device includes: a data alignment unit for aligning in parallel a plurality of data sequentially inputted through one data input pin as many as the number of prefetched data to generate a plurality of aligned data; a global I/O line driving unit for receiving the plurality of aligned data and outputting the even data or the odd data to a memory core area in response to a data input strobe signal; a data input strobe signal generating unit for buffering the clock signal to output the data input strobe signal; and a data input strobe signal control unit for generating a data input strobe control signal used to allow the data input strobe signal generating unit to output the data input strobe signal only at a period when an operation corresponding to the write command is carried out.

Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.