A
system for concurrently verifying
programming of logical data in a multi-level-
cell (MLC)
flash memory device having a plurality of memory cells each configured to store N bits of logical data where N>=2. The MLC
flash memory device has a plurality of memory cells capable of being storing N-bits of data in one of 2N distinct data storage levels, each data storage level corresponding to a discrete N-bit combination of logical data. The data storage levels include a default level, called the erased level, and 2N-1 program levels, including a lowest program level, 2N-2 intermediate program levels and a highest program level. For each
memory cell to be verified as programmed, an N-bit combination of data to be verified is loaded into a program-verify circuit and a stepped
voltage pulse having 2N-1 steps is applied to each
memory cell. The stepped
voltage pulse includes an initial step, at least one intermediate step and a final step with the initial step substantially equal to a program-verify
voltage for the highest program level of the MLC
flash memory within a the highest program level, each successive intermediate step is substantially equal to a program-verify voltage corresponding to an intermediate program level and the final step of the
voltage pulse is substantially equal to a program-verify voltage for the lowest program level. Concurrently with the application of the stepped
voltage pulse to each
memory cell, the data storage level is verified as substantially within a program level corresponding to the N-bit combination for the memory
cell. Subsequent to verifying the data storage level for a memory
cell, the verified memory cell is inhibited form further application of a program pulse.