35 results about "Multi-level cell" patented technology

Systems, methods, and data storage devices for dynamic mode selection for hybrid MLC / SLC data storage devices are described. Storage operations at a plurality of storage devices from a host device may be processed, wherein each storage device of the plurality of storage devices comprises a plurality of partitions including multi-level cell blocks and single-level cell blocks and multi-level cell blocks may be selectively written in a single-level write operation. A usage value is determined for each partition of the plurality of partitions at each storage device of the plurality of storage devices. A storage device of the plurality of storage devices may be dynamically selected based on the usage value for single-level cell blocks of the selected storage device having available single level cell blocks. New data may then be stored at the dynamically selected storage device of the plurality of storage devices.

In accordance with some embodiments of the present disclosure, a method is performed by processing circuitry of a storage device for writing data to memory of a storage device. The method is related to executing a program to write data written in a plurality of single-layer cells (SLCs) in a first portion of the memory to a plurality of multi-level cells (MLCs) in a second portion of the memory using a single program command. The single program command includes an address of each SLC in the first portion of the memory and optionally, additional information regarding SLC read-level shifts. Executing the single program command includes reading from each SLC of the plurality of SLCs, storing at least some of the respective SLC data in the plurality of latches, and writing the SLC data that was stored in the plurality of latches to the plurality of MLCs.

A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

The invention belongs to the technical field of semiconductor photoelectric device manufacturing, and particularly relates to an epitaxial growth method of a P-type Bragg reflection layer, a vertical cavity surface emitting laser and an epitaxial growth method of the vertical cavity surface emitting laser. The P-type Bragg reflection layer provided by the invention is grown by adopting a metal organic compound chemical vapor deposition-in-situ reflection monitoring method, and comprises multiple layers of unit structures which are arranged in a laminated manner, each layer of unit structure sequentially comprises a carbon-doped GaAs layer, a first carbon-doped AlGaAs layer, a delta-doped layer and a second carbon-doped AlGaAs layer from bottom to top, the delta-doped layer is located at an optical standing wave node, and the second carbon-doped AlGaAs layer is located at an optical standing wave node. And the delta-doped layer is a third carbon-doped AlGaAs layer. According to the P-type Bragg reflection layer provided by the invention, the resistance of a P-DBR device can be remarkably reduced while high reflectivity is maintained, and the optimal balance of photoelectric properties is achieved through accurate control of a doping position.

The invention provides a memory device. A memory device includes a memory block, an operation processor, and an address allocator. The memory block includes a plurality of string groups connected to a plurality of word lines. The operation processor is configured to set a program operation mode of the memory block to one of a single-layer cell (SLC) mode and a multi-layer cell (MLC) mode in response to a command received from outside the memory device. The address allocator is configured to allocate row addresses of the memory blocks differently according to a program operation mode.

A multilayer ceramic capacitor includes a cuboid element body having a multilayer unit alternately laminating ceramic layers and internal electrodes composed primarily of metal, a pair of covering portions arranged at both ends of the multilayer unit in the laminating direction and covering surfaces of the multilayer unit, and margin portions covering at least some of the end portions of the ceramic layers and the internal electrodes in the multilayer unit, and connecting the pair of covering portions to each other; and a plurality of terminal electrodes electrically connected to the internal electrodes, and arranged in a spaced-apart manner on a mounting surface, which is one of the surfaces forming the surfaces of the element body, facing the circuit board during circuit board mounting, wherein the plurality of terminal electrodes are arranged in m units in a first direction on the mounting surface and n units in a second direction perpendicular to the first direction (where m is a natural number equal to or greater than 2 and n is a natural number), a region in which the terminal electrodes are not arranged on the mounting surface has a mounting surface side intersection portion in which a first straight line and a second straight line intersect, and a mounting surface side non-intersection portion in which the first straight line and the second straight line do not intersect, when the first straight line is drawn to extend in the first direction without touching any of the terminal electrodes and the second straight line is drawn to extend in the second direction without touching any of the terminal electrodes, and the element body satisfies T1<T2, where T1 is a dimension in the laminating direction of the element body, as measured with reference to a mounting surface side intersection portion, and T2 is a dimension in the laminating direction of the element body, as measured with reference to a mounting surface side non-intersection portion.

Methods, systems, and devices for write booster pinning are described. In some examples, a memory device may receive one or more commands (e.g., write commands) while operating in a first mode (e.g., a write booster mode). Some write commands may include an indication to pin the data to one or more SLCs. For example, a first write command may be associated with first data and a first indicator and a second write command may be associated with second data. Both the first data and the second data may be written to one or more SLCs. When maintenance operations are performed on the SLCs, the second data may be moved (e.g., written) to one or more MLCs. Additionally or alternatively, the memory system may receive one or more commands to unpin data (e.g., the first data) such that it may be moved to one or more MLCs during subsequent maintenance operations.

Methods, systems, and devices for data storage and decompression in a memory system are described. The described techniques provide for a memory system to store compressed data during a manufacturing stage according to a first write configuration and store decompressed data according to a second write configuration. The first write configuration may be associated with writing to a set of single-level cells (SLCs) as part of a pre-programming operation and the second write configuration may be associated with writing to a set of multiple-level cells when the memory system enters an operational mode. In some cases, the compressed data may include a bitmap indicating a relationship between one or more symbols each representing a sequence of bits and a respective set of one or more locations within the data.

In accordance with some embodiments of the present disclosure, a method is performed by processing circuitry of a storage device for writing data to memory of a storage device. The method is related to executing a program to write data written in a plurality of single-layer cells (SLCs) in a first portion of the memory to a plurality of multi-level cells (MLCs) in a second portion of the memory using a single program command. The single program command includes an address of each SLC in the first portion of the memory and optionally, additional information regarding SLC read-level shifts. Executing the single program command includes reading from each SLC of the plurality of SLCs, storing at least some of the respective SLC data in the plurality of latches, and writing the SLC data that was stored in the plurality of latches to the plurality of MLCs.

In accordance with some embodiments of the present disclosure, a method is performed by processing circuitry of a storage device for writing data to memory of a storage device. The method is related to executing a program to write data written in a plurality of single-layer cells (SLCs) in a first portion of the memory to a plurality of multi-level cells (MLCs) in a second portion of the memory using a single program command. The single program command includes an address of each SLC in the first portion of the memory and optionally, additional information regarding SLC read-level shifts. Executing the single program command includes reading from each SLC of the plurality of SLCs, storing at least some of the respective SLC data in the plurality of latches, and writing the SLC data that was stored in the plurality of latches to the plurality of MLCs.

A multilayer ceramic capacitor includes: a cuboid element body having a multilayer unit alternately laminating ceramic layers and internal electrodes composed primarily of metal, a pair of covering portions arranged at both ends of the multilayer unit in the laminating direction and covering surfaces of the multilayer unit, and margin portions covering at least some of the end portions of the ceramic layers in the multilayer unit and the end portions of the internal electrodes, and connecting the pair of covering portions to each other; and a plurality of terminal electrodes electrically connected to the internal electrodes, and arranged on at least a mounting face, which is one of the faces forming the surfaces of the element body, that faces the circuit board when the multilayer ceramic capacitor mounted on the circuit board, wherein at least one of the main faces, which are the faces with the largest area among the faces forming the surfaces of the element body, has particles of a metal oxide adhered to an exposed portion that is not covered by any terminal electrodes, and the metal oxide is different from the material forming the exposed portion.

A data storage device and method for accident-mode storage of vehicle information are disclosed. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The memory comprises single-level cell (SLC) memory and multi-level cell (MLC) memory. The one or more processors, individually or in combination, are configured to: receive a command from a vehicle to enter accident mode; and in response to receiving the command from the vehicle to enter accident mode, relocate vehicle information stored in the MLC memory to the SLC memory. Other embodiments are disclosed.

Methods, systems, and devices for write booster buffer and hibernate are described. The memory system may initiate a first operation to enter a first power mode having a lower power consumption than a second power mode. In some cases, the memory system may determine whether a quantity of data stored in a buffer of single-level cells associated with write booster information satisfies a threshold based on initiating the first operation. The memory system may determine whether to perform a second operation to transfer the quantity of data stored in the buffer of single-level cells to a portion of memory comprising multiple level cells based on determining whether the quantity of data satisfies the threshold. The memory system may enter the first power mode based on determining to perform the second operation to transfer the quantity of data from the buffer to the portion of memory.

Methods, systems, and devices for adaptive performance tuning for memory systems are described. A memory system may apply a programming mode ratio. For example, the memory system may write data to single-level cell (SLC) word lines and multiple level cell word lines according to a ratio. The memory system may determine the ratio according to operating parameters, such as a command queue depth, size of commands in the command queue, host delays, an amount of free space, or the like. The memory system may determine the ratio based on whether the operating parameters satisfy thresholds. That is, the memory system may compare each operating parameter to one or more operating parameter thresholds.

Embodiments of the present invention provide a honeycomb core formed of a plurality of polygonal cells arranged in an array, where each polygonal cell has a side cell wall, the side cell walls of each polygonal cell forming a polygonal loop, the side cell walls comprising a sheet, the sheet is a symmetric three or five layer thermoplastic co-extruded sheet having an inner central layer or core layer and an outer layer. The symmetric three or five layer thermoplastic co-extruded sheet provides better mechanical properties compared to a simple sheet.

Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.

More efficient memory device usage is possible by altering the memory device management. For example, when the full storage capacity of the memory device will not be used, certain portions of the memory device can be shut off and then turned on when the storage capacity is needed. When less capacity is needed, data can be consolidated and certain portions of the memory device can be shut off. Additionally, rather than operating in multilevel cell (MLC) memory, the memory device can start in single level cell (SLC) memory and transition to MLC memory over time. If there is a determination that less memory is needed, the memory device can transition from MLC memory to SLC memory. In so doing, the storage capacity of the memory device is more appropriately utilized.

An aspect of the present invention is a multilayer ceramic capacitor comprising: a multilayer unit obtained by alternately laminating ceramic layers and internal electrodes composed primarily of metal; a cuboid element body having a pair of covering portions arranged at both ends of the stack in the laminating direction and covering surfaces of the multilayer unit, and margin portions covering at least some of the end portions of the ceramic layers, and the end portions of the internal electrodes in the multilayer unit, and connecting the pair of covering portions to each other; and a plurality of terminal electrodes electrically connected to the internal electrodes, and arranged apart from each other on at least a mounting surface out of the surfaces forming the surfaces of the element body, wherein the mounting surface is a surface facing the circuit board on which the capacitor is to be mounted, and relational expression (1) below is satisfied, where Po is the porosity of a surface layer portion and Pi is a porosity of an inner portion located closer to the multilayer unit than the surface layer portion in at least some of the regions in the covering portion or the margin portionPi<Po.(1)

A 3D DRAM architecture may have one or more layers of cells where the access transistors of the memory cell array are fabricated among the metal layers rather than in the semiconductor (e.g., silicon) substrate. Counter and counter control circuits for each row in the memory cell array are fabricated under the array. These counters track the number of row hammers each row experiences. When a counter indicates a row has experienced a threshold number of row hammers, that row is refreshed. The row may be refreshed immediately after the current row is closed. The row may be scheduled to be refreshed as part of a regular refresh sequence. A signal may be sent to the memory controlling indicating that the bank with the row being refreshed immediately should not be accessed until the refresh is complete.

Methods, systems, and devices for data layout configurations for access operations are described. The memory system may write data to a first set of memory cells using a first write operation having a first type of layout for mapping the data to physical addresses of the memory system in response to receiving a write command. The first set of memory cells may be written to as single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs). The memory system may transfer the data to a second set of memory cells of the memory system using a second write operation having the first type of layout. The second set of memory cells may be written to as quad-level cells (QLCs). The memory system may read the data from the second set of memory cells using a read operation having a second type of layout different than the first type of layout.

A data storage device and method for accident mode storage of vehicle information are disclosed. In one embodiment, a data storage device is provided that includes a memory and one or more processors. The memory includes a single-layer cell (SLC) memory and a multi-layer cell (MLC) memory. The one or more processors, individually or in combination, are configured to: receive a command from a vehicle to enter an accident mode; and in response to receiving a command from the vehicle to enter the accident mode, relocating the vehicle information stored in the MLC memory to the SLC memory. Other embodiments are disclosed.

The application belongs to the technical field of semiconductor photoelectric device manufacturing, and particularly relates to an epitaxial growth method of a P-type Bragg reflection layer, a vertical cavity surface emitting laser and an epitaxial growth method thereof. The P-type Bragg reflection layer provided by the application is grown by a metal organic chemical vapor deposition-in-situ reflection monitoring method, comprises a plurality of layer unit structures arranged in layers, and each layer unit structure comprises, from bottom to top, a carbon-doped GaAs layer, a first carbon-doped AlGaAs layer, a delta-doped layer and a second carbon-doped AlGaAs layer. The delta-doped layer is located at an optical standing wave node, and the delta-doped layer is a third carbon-doped AlGaAs layer. The P-type Bragg reflection layer provided by the application can significantly reduce the resistance of a P-DBR device while maintaining high reflectivity, and the optimal balance of photoelectric performance can be achieved through accurate control of the doping position.

A data storage device and method for hybrid space balancing based on host read affinity and heuristics are provided. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The one or more processors, individually or in combination, are configured to: receive information from a host regarding an incoming write workload of a burst operation; and dynamically adjust an amount of the memory configured as single-level cell (SLC) memory versus multi-level cell (MLC) memory based on the information to accommodate the burst operation. Other embodiments are disclosed.

By changing memory device management, more efficient memory device usage can be achieved. For example, when all storage capacity of the memory device will not be used, some portions of the memory device can be turned off and then turned on when the storage capacity is needed. When less capacity is required, data can be integrated and some portions of the memory device can be turned off. In addition, the memory device is capable of starting in a single-layer cell (SLC) memory and transitioning to an MLC memory over time, rather than operating in a multi-layer cell (MLC) memory. If it is determined that less memory is required, the memory device can transition from MLC memory to SLC memory. In this way, the storage capacity of the memory device is utilized more appropriately.

The invention relates to a memory device and an operating method thereof. The memory device may include a first memory block, a second memory block, a peripheral circuit, and a control circuit. The control circuit controls the peripheral circuit to program first data to a first memory block according to a single layer cell (SLC) scheme, to generate second data by converting data read from the first memory block in chunk units, and to program the second data to a second memory block according to a multi-layer cell (MLC) scheme.

A programming method of a memory device comprising a multi-level cell is introduced. The programming method includes applying a sequence of program pulses comprising at least one set pulse and at least one reset pulse to the multi-level cell; determining whether the resistance of the multi-level cell is in a target range after each program pulse of the sequence of program pulses is applied to the multi-level cell; keeping applying the sequence of program pulses to the multi-level cell in response to determining that the resistance of the multi-level cell is not in the target range; and stopping applying the sequence of program pulses to the multi-level cell in response to determining that the resistance of the multi-level cell is in the target range.

A storage device is provided. The storage device of the present invention includes a memory device comprising a first single-level cell area, a second single-level cell area, and a multi-level cell area, and a storage controller that reads data from the memory device and controls the movement of data between the first single-level cell area, the second single-level cell area, and the multi-level cell area, wherein the data reading speed of the first single-level cell area may be faster than the data reading speed of the second single-level cell area.

A memory device may include a first memory block, a second memory block, a peripheral circuit, and a control circuit. The control circuit controls the peripheral circuit to program first data to the first memory block according to a single-level cell (SLC) scheme, generate second data by converting data read from the first memory block on a chunk basis, and program the second data to the second memory block according to a multi-level cell (MLC) scheme.

A storage device may maintain data reliability between sub-blocks by executing wear leveling operations such that a program-erase count (PEC) difference between sister sub-blocks is reduced. The storage device may include a memory device including blocks, and at least one of the blocks may be divided into sister sub-blocks. The storage device may also include a controller to calculate a sister sub-block threshold and process a wear leveling operation. When executing the wear leveling operation, the controller may select a destination block. The controller may also prioritize a first sister block for a multi-layer cell (MLC) flow when the PEC value of a second sister sub-block is greater than the sister sub-block threshold.

To provide a laminate in which a p-type semiconductor and an n-type semiconductor are laminated, each of which is made of a silicon alloy of silver, barium, and silicon, and at least one of a thermoelectric conversion material and a thermoelectric conversion module including the laminate.SOLUTION: A silicon alloy laminate made of silver, barium, and silicon, has a structure in which a p-type semiconductor layer, a mixed semiconductor layer containing a p-type semiconductor and an n-type semiconductor, and an n-type semiconductor layer are laminated in this order, and the mixed semiconductor layer has a structure in which two or more unit layers are laminated.SELECTED DRAWING: None