17 results about "Multi-level cell" patented technology

In accordance with some embodiments of the present disclosure, a method is performed by processing circuitry of a storage device for writing data to memory of a storage device. The method is related to executing a program to write data written in a plurality of single-layer cells (SLCs) in a first portion of the memory to a plurality of multi-level cells (MLCs) in a second portion of the memory using a single program command. The single program command includes an address of each SLC in the first portion of the memory and optionally, additional information regarding SLC read-level shifts. Executing the single program command includes reading from each SLC of the plurality of SLCs, storing at least some of the respective SLC data in the plurality of latches, and writing the SLC data that was stored in the plurality of latches to the plurality of MLCs.

The invention belongs to the technical field of semiconductor photoelectric device manufacturing, and particularly relates to an epitaxial growth method of a P-type Bragg reflection layer, a vertical cavity surface emitting laser and an epitaxial growth method of the vertical cavity surface emitting laser. The P-type Bragg reflection layer provided by the invention is grown by adopting a metal organic compound chemical vapor deposition-in-situ reflection monitoring method, and comprises multiple layers of unit structures which are arranged in a laminated manner, each layer of unit structure sequentially comprises a carbon-doped GaAs layer, a first carbon-doped AlGaAs layer, a delta-doped layer and a second carbon-doped AlGaAs layer from bottom to top, the delta-doped layer is located at an optical standing wave node, and the second carbon-doped AlGaAs layer is located at an optical standing wave node. And the delta-doped layer is a third carbon-doped AlGaAs layer. According to the P-type Bragg reflection layer provided by the invention, the resistance of a P-DBR device can be remarkably reduced while high reflectivity is maintained, and the optimal balance of photoelectric properties is achieved through accurate control of a doping position.

A multilayer ceramic capacitor includes a cuboid element body having a multilayer unit alternately laminating ceramic layers and internal electrodes composed primarily of metal, a pair of covering portions arranged at both ends of the multilayer unit in the laminating direction and covering surfaces of the multilayer unit, and margin portions covering at least some of the end portions of the ceramic layers and the internal electrodes in the multilayer unit, and connecting the pair of covering portions to each other; and a plurality of terminal electrodes electrically connected to the internal electrodes, and arranged in a spaced-apart manner on a mounting surface, which is one of the surfaces forming the surfaces of the element body, facing the circuit board during circuit board mounting, wherein the plurality of terminal electrodes are arranged in m units in a first direction on the mounting surface and n units in a second direction perpendicular to the first direction (where m is a natural number equal to or greater than 2 and n is a natural number), a region in which the terminal electrodes are not arranged on the mounting surface has a mounting surface side intersection portion in which a first straight line and a second straight line intersect, and a mounting surface side non-intersection portion in which the first straight line and the second straight line do not intersect, when the first straight line is drawn to extend in the first direction without touching any of the terminal electrodes and the second straight line is drawn to extend in the second direction without touching any of the terminal electrodes, and the element body satisfies T1<T2, where T1 is a dimension in the laminating direction of the element body, as measured with reference to a mounting surface side intersection portion, and T2 is a dimension in the laminating direction of the element body, as measured with reference to a mounting surface side non-intersection portion.

Methods, systems, and devices for data storage and decompression in a memory system are described. The described techniques provide for a memory system to store compressed data during a manufacturing stage according to a first write configuration and store decompressed data according to a second write configuration. The first write configuration may be associated with writing to a set of single-level cells (SLCs) as part of a pre-programming operation and the second write configuration may be associated with writing to a set of multiple-level cells when the memory system enters an operational mode. In some cases, the compressed data may include a bitmap indicating a relationship between one or more symbols each representing a sequence of bits and a respective set of one or more locations within the data.

In accordance with some embodiments of the present disclosure, a method is performed by processing circuitry of a storage device for writing data to memory of a storage device. The method is related to executing a program to write data written in a plurality of single-layer cells (SLCs) in a first portion of the memory to a plurality of multi-level cells (MLCs) in a second portion of the memory using a single program command. The single program command includes an address of each SLC in the first portion of the memory and optionally, additional information regarding SLC read-level shifts. Executing the single program command includes reading from each SLC of the plurality of SLCs, storing at least some of the respective SLC data in the plurality of latches, and writing the SLC data that was stored in the plurality of latches to the plurality of MLCs.

In accordance with some embodiments of the present disclosure, a method is performed by processing circuitry of a storage device for writing data to memory of a storage device. The method is related to executing a program to write data written in a plurality of single-layer cells (SLCs) in a first portion of the memory to a plurality of multi-level cells (MLCs) in a second portion of the memory using a single program command. The single program command includes an address of each SLC in the first portion of the memory and optionally, additional information regarding SLC read-level shifts. Executing the single program command includes reading from each SLC of the plurality of SLCs, storing at least some of the respective SLC data in the plurality of latches, and writing the SLC data that was stored in the plurality of latches to the plurality of MLCs.

A multilayer ceramic capacitor includes: a cuboid element body having a multilayer unit alternately laminating ceramic layers and internal electrodes composed primarily of metal, a pair of covering portions arranged at both ends of the multilayer unit in the laminating direction and covering surfaces of the multilayer unit, and margin portions covering at least some of the end portions of the ceramic layers in the multilayer unit and the end portions of the internal electrodes, and connecting the pair of covering portions to each other; and a plurality of terminal electrodes electrically connected to the internal electrodes, and arranged on at least a mounting face, which is one of the faces forming the surfaces of the element body, that faces the circuit board when the multilayer ceramic capacitor mounted on the circuit board, wherein at least one of the main faces, which are the faces with the largest area among the faces forming the surfaces of the element body, has particles of a metal oxide adhered to an exposed portion that is not covered by any terminal electrodes, and the metal oxide is different from the material forming the exposed portion.

Methods, systems, and devices for adaptive performance tuning for memory systems are described. A memory system may apply a programming mode ratio. For example, the memory system may write data to single-level cell (SLC) word lines and multiple level cell word lines according to a ratio. The memory system may determine the ratio according to operating parameters, such as a command queue depth, size of commands in the command queue, host delays, an amount of free space, or the like. The memory system may determine the ratio based on whether the operating parameters satisfy thresholds. That is, the memory system may compare each operating parameter to one or more operating parameter thresholds.

An aspect of the present invention is a multilayer ceramic capacitor comprising: a multilayer unit obtained by alternately laminating ceramic layers and internal electrodes composed primarily of metal; a cuboid element body having a pair of covering portions arranged at both ends of the stack in the laminating direction and covering surfaces of the multilayer unit, and margin portions covering at least some of the end portions of the ceramic layers, and the end portions of the internal electrodes in the multilayer unit, and connecting the pair of covering portions to each other; and a plurality of terminal electrodes electrically connected to the internal electrodes, and arranged apart from each other on at least a mounting surface out of the surfaces forming the surfaces of the element body, wherein the mounting surface is a surface facing the circuit board on which the capacitor is to be mounted, and relational expression (1) below is satisfied, where Po is the porosity of a surface layer portion and Pi is a porosity of an inner portion located closer to the multilayer unit than the surface layer portion in at least some of the regions in the covering portion or the margin portionPi<Po.(1)

A data storage device and method for accident mode storage of vehicle information are disclosed. In one embodiment, a data storage device is provided that includes a memory and one or more processors. The memory includes a single-layer cell (SLC) memory and a multi-layer cell (MLC) memory. The one or more processors, individually or in combination, are configured to: receive a command from a vehicle to enter an accident mode; and in response to receiving a command from the vehicle to enter the accident mode, relocating the vehicle information stored in the MLC memory to the SLC memory. Other embodiments are disclosed.

The application belongs to the technical field of semiconductor photoelectric device manufacturing, and particularly relates to an epitaxial growth method of a P-type Bragg reflection layer, a vertical cavity surface emitting laser and an epitaxial growth method thereof. The P-type Bragg reflection layer provided by the application is grown by a metal organic chemical vapor deposition-in-situ reflection monitoring method, comprises a plurality of layer unit structures arranged in layers, and each layer unit structure comprises, from bottom to top, a carbon-doped GaAs layer, a first carbon-doped AlGaAs layer, a delta-doped layer and a second carbon-doped AlGaAs layer. The delta-doped layer is located at an optical standing wave node, and the delta-doped layer is a third carbon-doped AlGaAs layer. The P-type Bragg reflection layer provided by the application can significantly reduce the resistance of a P-DBR device while maintaining high reflectivity, and the optimal balance of photoelectric performance can be achieved through accurate control of the doping position.

The invention relates to a memory device and an operating method thereof. The memory device may include a first memory block, a second memory block, a peripheral circuit, and a control circuit. The control circuit controls the peripheral circuit to program first data to a first memory block according to a single layer cell (SLC) scheme, to generate second data by converting data read from the first memory block in chunk units, and to program the second data to a second memory block according to a multi-layer cell (MLC) scheme.

A storage device is provided. The storage device of the present invention includes a memory device comprising a first single-level cell area, a second single-level cell area, and a multi-level cell area, and a storage controller that reads data from the memory device and controls the movement of data between the first single-level cell area, the second single-level cell area, and the multi-level cell area, wherein the data reading speed of the first single-level cell area may be faster than the data reading speed of the second single-level cell area.

A memory device may include a first memory block, a second memory block, a peripheral circuit, and a control circuit. The control circuit controls the peripheral circuit to program first data to the first memory block according to a single-level cell (SLC) scheme, generate second data by converting data read from the first memory block on a chunk basis, and program the second data to the second memory block according to a multi-level cell (MLC) scheme.

In accordance with some embodiments of the present disclosure, a method is performed by processing circuitry of a storage device for writing data to memory of a storage device. The method is related to executing a program to write data written in a plurality of single-layer cells (SLCs) in a first portion of the memory to a plurality of multi-level cells (MLCs) in a second portion of the memory using a single program command. The single program command includes an address of each SLC in the first portion of the memory and optionally, additional information regarding SLC read-level shifts. Executing the single program command includes reading from each SLC of the plurality of SLCs, storing at least some of the respective SLC data in the plurality of latches, and writing the SLC data that was stored in the plurality of latches to the plurality of MLCs.

The invention provides a capacity configuration method of a multi-layer unit memory chip, a controller and a vehicle, which are used for prolonging the service life of the memory chip. Wherein in the production process of the controller mainboard, the multi-layer unit storage chip is embedded into the controller mainboard in a standard packaging state, and establishes communication with a control chip on the controller mainboard; the capacity configuration method of the multi-layer unit storage chip comprises the steps that the multi-layer unit storage chip receives a capacity partition configuration instruction sent by a control chip; according to the capacity partition configuration instruction, NAND flash memory partition operation is executed, so that the capacity of the multi-layer unit storage chip is permanently divided into a pseudo single-layer unit partition and a multi-layer unit partition; wherein one unit in the pseudo single-layer unit partition stores information of one bit, and one unit in the multi-layer unit partition stores information of a plurality of bits.

The utility model discloses a PCB circuit board of a new energy vehicle-mounted OBC power supply, the circuit board comprises multiple layers of unit boards, and the multiple layers of unit boards are fixed together through rivets in riveting holes. Each layer of unit plate comprises a hole opening position of at least one riveting hole, at least one direction indication mark and at least two marking target spots are arranged on the surface of the unit plate, the marking target spots comprise a first target spot and a second target spot, and the first target spot and the second target spot are different in structure; the first target spot comprises a first rectangular frame, a first circular area arranged in the first rectangular frame and a first pattern area located in the first circular area; the second target spot comprises a second rectangular area and a second circular area arranged in the second rectangular area. The PCB of the new energy vehicle-mounted OBC power supply provided by the utility model solves the technical problem in the prior art that the direction of a circuit board is reversely punched into a wrong hole position during OPE punching.