21 results about "Physical mapping" patented technology

A request is received that specifies a logical address associated with a host initiated operation for a first portion of a memory device. A logical to physical (L2P) table is accessed. The L2P table includes mappings between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and it is determined that the entry points to an entry in a read cache table. A block address of a block from among a plurality of blocks of a read cache is calculated based on an entry number of the entry in the read cache table. A physical address corresponding to the logical address specified by the request is identified by accessing the block of the read cache. A host initiated operation is performed at a physical location in the first portion of the memory device that corresponds to the physical address.

The application discloses a cross-grain RAID strip local dynamic reconstruction method and device based on a logical-physical mapping bitmap index, comprising the following steps: first, a logical-physical mapping bitmap index for marking the validity of each sector data in a RAID strip is maintained in a flash translation layer (FTL) of a solid state disk; when a target grain failure is detected, the bitmap index is called by the system for analysis; then, according to the marking of the bitmap index, the effective data area on other healthy grains in the corresponding strip is accurately scheduled to perform local reading and XOR calculation, and all invalid data areas are actively skipped to reconstruct the effective data in the failed grain; finally, the recovered discrete effective data is dynamically aggregated into a new complete strip and then written into a standby physical space. Through the application, internal read amplification and write amplification in the reconstruction process can be significantly reduced, the failure recovery time is shortened, and the performance stability of the SSD in the degradation mode is ensured.

The application discloses a kind of address management methods of partitioned namespace solid state disk and related equipment.Its method includes: in power-on initialization stage, the memory space corresponding to the address space of single partition is applied with the size of logical-to-physical mapping table, and logical-to-physical mapping table is initialized as the physical mapping address value set of all address units in reference superblock;Binding relationship between partition and superblock and the binding relationship table of the amount of valid data written in each partition are maintained;In response to read command, the physical mapping address of target data is obtained according to binding relationship table and logical-to-physical mapping table;When power-off, the binding relationship table is persisted, and the saved binding relationship table is loaded when re-powered.The application can greatly reduce memory requirements and simplify operation management logic while ensuring the performance of direct table lookup of read command, shorten the power-on and power-off time of partitioned namespace solid state disk, and improve its overall performance and efficiency.

Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.

Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.

A method for allocating resources for a scheduling request indicator (SRI) is disclosed. An SRI cycle period for use by user equipment (UE) within a cell is transmitted from a NodeB in a cell to UE within the cell. The NodeB transmits a specific SRI subframe offset and an index value to the particular UE within the cell. The specific SRI subframe offset and the index value enable the UE to determine a unique combination of cyclic shift, RS orthogonal cover, data orthogonal cover, and resource block number for the UE to use as a unique physical resource for an SRI in the physical uplink control channel (PUCCH).

A request that specifies a logical address associated with a host-initiated operation directed at a first portion of a memory device is received. A logical to physical (L2P) table is accessed. The L2P table comprises a mapping between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and is determined to point to an entry in a read cache table. Based on an entry number of the entry in the read cache table, a chunk address of a chunk from among multiple chunks of a read cache is calculated. A physical address that corresponds to the logical address specified by the request is identified by accessing the chunk of read cache. The host-initiated operation is performed at a physical location within the first portion of the memory device corresponding the physical address.

The invention provides a fault transmission analysis method based on a functional physical mapping model, and belongs to the technical field of complex system safety analysis, and the method comprises the following steps: S1, carrying out the preparation before modeling; s2, creating a functional physical mapping model of the system; and S3, carrying out security analysis on the functional physical mapping model. By adopting the fault transmission analysis method based on the functional physical mapping model, the problem of repeated modeling work caused by separation of functional modeling and physical modeling is solved, a method for associating a system function with a physical architecture is provided, the efficiency of safety analysis work based on the model is improved, and the method is suitable for popularization and application. And the integrity and accuracy of hardware fault identification are ensured.

A processing device receives a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device. The processing device accesses a second L2P table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device. A physical location within the second portion of the memory device is identified based on the second L2P table. The physical location corresponds to a portion of a first L2P table that specifies a physical address within the first portion of the memory device that corresponds to the logical address. The physical address is identified based on the portion of the first L2P table and the host-initiated operation is performed at the physical address.

Methods, systems, and devices for logical-to-physical (L2P) mapping for enhanced granularity data storage are described. A memory system may support write operations according to multiple different write granularities and corresponding data transfer sizes. Entries that map logical addresses to physical addresses within the memory system may include first entries associated with a first data transfer size and second entries associated with a second data transfer size that is greater than the first data transfer size. If the memory system receives a write command that indicates a size of data that is less than or equal to the first data transfer size, the system may update the first entries to indicate a mapping. Data indicated via write commands associated with larger data sizes may be mapped by the second entries. The varying entry structure may support improved write operations and throughput for storage of data at varying granularities.

The invention discloses an operation method and device for logic-to-physical mapping and a storage medium. The method comprises the steps that write operation for the storage medium is received; the L2P of the write data corresponding to the write operation is stored in the processing cache, and under the condition that the storage amount of the L2P in the processing cache reaches a storage threshold value, duplicate removal operation is conducted on the L2P in the processing cache; wherein the processing cache is a preset cache used for temporarily storing the L2P; and writing the L2P subjected to the duplicate removal operation into an L2P table, and after one or more L2P table entries in an L2P management table corresponding to the L2P table reach an update threshold, writing the L2P corresponding to the L2P table entry reaching the update threshold in the L2P management table into a storage medium. Therefore, invalid updating of the L2P table is reduced, and invalid bandwidth occupation and write amplification caused by invalid L2P updating are reduced.

Methods, systems, and devices for logical-to-physical (L2P) mapping for zoned namespace (ZNS) memory systems are described. A memory system may include a cache, such as a single‑level cell (SLC) cache in front of a quad-level cell (QLC) non-volatile memory device. The cache may include a multiple layer L2P table to map logical block addresses (LBAs) of data to physical addresses of the cache. In some examples, the L2P table may be sparsely populated to hold a quantity of LBAs corresponding to a quantity of open zones, and may be organized into groups of L2P entries to address a full logical space of the memory device. L2 Region boundaries may be aligned on zone boundaries by utilizing an integer quantity of L2 regions for each zone, an integer quantity of L2P entries per L2 region, or both, to reduce complexity and write amplification while improving performance.

A method of operating a memory system is provided. A logical-to-physical (L2P) address mapping table is obtained in response to a data request instruction. Corresponding data is read from a memory device based on the L2P address mapping table. The L2P address mapping table includes a base physical address of continuous first physical addresses corresponding to first logic addresses and a base physical address offset corresponding to the continuous first physical addresses.

Methods, systems, and devices for logical-to-physical (L2P) mapping for zoned namespace (ZNS) memory systems are described. A memory system may include a cache, such as a single-level cell (SLC) cache in front of a quad-level cell (QLC) non-volatile memory device. The cache may include a multiple layer L2P table to map logical block addresses (LBAs) of data to physical addresses of the cache. In some examples, the L2P table may be sparsely populated to hold a quantity of LBAs corresponding to a quantity of open zones, and may be organized into groups of L2P entries to address a full logical space of the memory device. L2 Region boundaries may be aligned on zone boundaries by utilizing an integer quantity of L2 regions for each zone, an integer quantity of L2P entries per L2 region, or both, to reduce complexity and write amplification while improving performance.

Methods, systems, and devices for logical-to-physical (L2P) mapping for enhanced granularity data storage are described. A memory system may support write operations according to multiple different write granularities and corresponding data transfer sizes. Entries that map logical addresses to physical addresses within the memory system may include first entries associated with a first data transfer size and second entries associated with a second data transfer size that is greater than the first data transfer size. If the memory system receives a write command that indicates a size of data that is less than or equal to the first data transfer size, the system may update the first entries to indicate a mapping. Data indicated via write commands associated with larger data sizes may be mapped by the second entries. The varying entry structure may support improved write operations and throughput for storage of data at varying granularities.

The present disclosure provides a method and system for logical to physical mapping of a data storage device. The method includes maintaining first type information representing at least a portion of a logical to physical address translation mapping. Further, the method includes maintaining second type information related to the logical to physical translation mapping as a portion of a physical page. Further, the method includes completing the logical to physical mapping based on the first type information and the second type information to determine a physical location of data stored in each logical page within one or more of the physical pages.

During operation, an electronic device may generate, using an image sensor, a 2D or a 3D map of a physical layout of an environment. Then, based at least in part on the 2D or 3D map of the physical layout of the environment, the electronic device may determine a path of the electronic device in the environment. Moreover, the electronic device may perform a wireless scan, where the wireless scan is performed concurrently with motion of the electronic device along the path. Next, based at least in part on the wireless scan, the electronic device may generate a wireless-performance map of wireless performance along the path. Furthermore, based at least in part on the 2D or 3D map of the physical layout of the environment, the electronic device may interpolate the wireless-performance map to determine the wireless performance in a 2D plane in the environment.

This invention discloses a program code refactoring self-testing method, device, and computer-readable storage medium. The method includes: constraining and guiding a large model to generate refactoring code for the current device through a preset physical directory; before sending the refactoring code to the device for testing, injecting a dataset of real physical mappings corresponding to the device into the refactoring code through a preset virtual sandbox, and collecting expected physical responses; verifying the expected physical responses based on the real physical responses in the dataset, and after successful verification, sending the refactoring code to the device for testing. This achieves a more reliable program code refactoring self-testing scheme, avoiding the risk of collisions with real-world devices when generating code from a large model, and ensuring the determinism and maintainability of industrial software architecture.

Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.