53 results about "Physical mapping" patented technology

Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.

A processing device receives a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device. The processing device accesses a second L2P table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device. A physical location within the second portion of the memory device is identified based on the second L2P table. The physical location corresponds to a portion of a first L2P table that specifies a physical address within the first portion of the memory device that corresponds to the logical address. The physical address is identified based on the portion of the first L2P table and the host-initiated operation is performed at the physical address.

The invention relates to a compressed logic-to-physical mapping for sequentially stored data. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block addresses generated by a host device to physical addresses of the memory device. The memory device may determine whether all entries of a terminal logical-to-physical mapping table are contiguous physical addresses. In response to determining that all entries contain contiguous physical addresses, a memory device may store a starting physical address of the contiguous physical addresses as an entry in a higher level table along with a flag indicating that the entry directly points to data in the memory device rather than a terminal logic-to-physical mapping table. For a subsequent read of data stored in one or more of the contiguous physical addresses, the memory device may read the data across a terminal table.

A request that specifies a logical address associated with a host-initiated operation directed at a first portion of a memory device is received. A logical to physical (L2P) table is accessed. The L2P table comprises a mapping between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and is determined to point to an entry in a read cache table. Based on an entry number of the entry in the read cache table, a chunk address of a chunk from among multiple chunks of a read cache is calculated. A physical address that corresponds to the logical address specified by the request is identified by accessing the chunk of read cache. The host-initiated operation is performed at a physical location within the first portion of the memory device corresponding the physical address.

In certain aspects, a memory controller includes a logical-to-physical (L2P) search engine. The L2P search engine is configured to maintain an L2P mapping table that maps logical addresses to physical addresses, respectively. The L2P search engine is further configured to organize the physical addresses mapped by the L2P mapping table into address categories based on the at least one address boundary.

Methods, systems, and devices for data relocation scheme selection for a memory system are described. A system may select, based on a fragmentation characteristic of data associated with a block of addresses, whether to perform a relocation associated with relocating invalid data, or to perform a relocation associated with refraining from relocating invalid data. A relocation associated with relocating invalid data may be selected for relatively more-fragmented data, which may avoid a relatively higher latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a more-granular level. A relocation associated with refraining from relocating invalid data may be selected for relatively less-fragmented data, which may support increasing available space by relocating data to a physical block with available portions that may be written to, taking advantage of a relatively lower latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a less-granular level.

A storage device is disclosed. The storage device may include a host interface to receive a write request from a host, the write request may include a data and a logical address of the data. The storage device may further include a first storage for the data. The storage device may further include a retention period determiner to determine a retention period for the data. The storage device may further include a translation layer to select a physical address in the first storage to store the data based at least in part on the retention period. The storage device may further include a second storage for a logical-to-physical mapping table to map the logical address to the physical address and the retention period. Finally, the storage device may include a controller to program the data into the physical address in the first storage.

The application discloses a mapping table snapshot generation method and an electronic device, relates to the technical field of data management, and performs block processing on a logical-to-physical mapping table of a full allocation volume and counts an empty block rate, adaptively selects a snapshot generation strategy according to an actual empty block distribution working condition of the mapping table, and obtains a complete mapping table snapshot that can be directly loaded. Compared with a recovery mode of full-disk traversal reconstruction of the mapping table, the recovery mode does not need to scan all data blocks in a fault recovery stage, does not need to reconstruct a mapping index in real time, can directly load a pre-generated snapshot to quickly restore a complete logical-to-physical mapping table, eliminates high time consumption overhead of traversal reconstruction of a large-capacity volume, shortens a fault recovery time length, reduces a business interruption time, and thus improves stability of business execution.

A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.

A request is received that specifies a logical address associated with a host initiated operation for a first portion of a memory device. A logical to physical (L2P) table is accessed. The L2P table includes mappings between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and it is determined that the entry points to an entry in a read cache table. A block address of a block from among a plurality of blocks of a read cache is calculated based on an entry number of the entry in the read cache table. A physical address corresponding to the logical address specified by the request is identified by accessing the block of the read cache. A host initiated operation is performed at a physical location in the first portion of the memory device that corresponds to the physical address.

A data storage device having a flash translation layer configured to handle file-system defragmentation in a manner that substantially avoids physical data movement in a flash memory. In an example embodiment, a memory controller operates to update a logical-to-physical table thereof to change association of physical addresses of sections of user data from being associated with source logical addresses to being associated with destination logical addresses of the host defragmentation requests without moving the user data in the flash memory. Such updates can reduce the number of instances in which the host addresses a non-contiguous logical-address range, which results in a beneficial reduction of the number of input / output commands sent to the data storage device and of the associated processing overhead.

The invention relates to separating logical-to-physical mappings. A memory system may separate an L2P map based on one or more characteristics of data associated with the L2P map. The memory system may determine whether a logical address included in a write command is associated with a first characteristic, a second characteristic, or some other characteristic. The memory system may write the L2P map to a first memory cell block, a second memory cell block, or some other memory cell block based on a determined characteristic of the L2P map. The blocks of memory cells to which the L2P mapping is written may include other mappings having data with the same (or similar) characteristics.

This application discloses a method and system of using HMB as a cache of physical address mapping table. The method comprises: arranging physical addresses in order of logical addresses, physical mapping entries corresponding to a plurality of consecutive physical addresses form one table unit, and a logical address corresponding to a first entry of each table unit is used as an index of the table unit; determining HMB size, dividing all table units into a plurality of sections according to the HMB size, each section comprises a plurality of table units, each section is divided into a plurality of ways; calculating a metadata according to logical address corresponding to the first entry of the table unit to be stored and the HMB size, the metadata comprises a section number and a way number; writing the metadata and the table unit to be stored into the HMB. This application uses HMB as L2P address mapping table cache of SSD controller, saving or avoiding use cost of DRAM on SSD, and reducing SSD size.

A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.

Methods, systems, and devices for logical-to-physical (L2P) mapping for enhanced granularity data storage are described. A memory system may support write operations according to multiple different write granularities and corresponding data transfer sizes. Entries that map logical addresses to physical addresses within the memory system may include first entries associated with a first data transfer size and second entries associated with a second data transfer size that is greater than the first data transfer size. If the memory system receives a write command that indicates a size of data that is less than or equal to the first data transfer size, the system may update the first entries to indicate a mapping. Data indicated via write commands associated with larger data sizes may be mapped by the second entries. The varying entry structure may support improved write operations and throughput for storage of data at varying granularities.

In certain aspects, a memory controller includes a logical-to-physical (L2P) search engine. The L2P search engine is configured to maintain an L2P mapping table that maps logical addresses to physical addresses, respectively. The L2P search engine is also configured to organize the physical addresses mapped by the L2P mapping table into address categories based on at least one address boundary.

The application discloses a cross-grain RAID strip local dynamic reconstruction method and device based on a logical-physical mapping bitmap index, comprising the following steps: first, a logical-physical mapping bitmap index for marking the validity of each sector data in a RAID strip is maintained in a flash translation layer (FTL) of a solid state disk; when a target grain failure is detected, the bitmap index is called by the system for analysis; then, according to the marking of the bitmap index, the effective data area on other healthy grains in the corresponding strip is accurately scheduled to perform local reading and XOR calculation, and all invalid data areas are actively skipped to reconstruct the effective data in the failed grain; finally, the recovered discrete effective data is dynamically aggregated into a new complete strip and then written into a standby physical space. Through the application, internal read amplification and write amplification in the reconstruction process can be significantly reduced, the failure recovery time is shortened, and the performance stability of the SSD in the degradation mode is ensured.

In certain aspects, a memory controller includes a logical-to-physical (L2P) search engine. The L2P search engine is configured to maintain an L2P mapping table that maps logical addresses to physical addresses, respectively. The L2P search engine is also configured to organize the physical addresses mapped by the L2P mapping table into address categories based on at least one address boundary.

The application discloses a kind of address management methods of partitioned namespace solid state disk and related equipment.Its method includes: in power-on initialization stage, the memory space corresponding to the address space of single partition is applied with the size of logical-to-physical mapping table, and logical-to-physical mapping table is initialized as the physical mapping address value set of all address units in reference superblock;Binding relationship between partition and superblock and the binding relationship table of the amount of valid data written in each partition are maintained;In response to read command, the physical mapping address of target data is obtained according to binding relationship table and logical-to-physical mapping table;When power-off, the binding relationship table is persisted, and the saved binding relationship table is loaded when re-powered.The application can greatly reduce memory requirements and simplify operation management logic while ensuring the performance of direct table lookup of read command, shorten the power-on and power-off time of partitioned namespace solid state disk, and improve its overall performance and efficiency.

The utility model relates to the technical field of teaching tools, and discloses a physical drawing device which comprises a substrate plate. The measuring part is configured at the middle part of the substrate plate and is used for sketching an arc line and / or a straight line and measuring the angle of the arc line and / or the length of the straight line; and a circuit drawing part which is arranged on the periphery of the measuring part and is used for drawing an optical path diagram and / or a circuit diagram. In addition, graphs of various subjects can be drawn rapidly, accurately and beautifully, and the learning efficiency and the drawing efficiency of students are greatly improved. Teachers and any other people can use the teaching aid conveniently.

Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.

Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.

Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.

A method for allocating resources for a scheduling request indicator (SRI) is disclosed. An SRI cycle period for use by user equipment (UE) within a cell is transmitted from a NodeB in a cell to UE within the cell. The NodeB transmits a specific SRI subframe offset and an index value to the particular UE within the cell. The specific SRI subframe offset and the index value enable the UE to determine a unique combination of cyclic shift, RS orthogonal cover, data orthogonal cover, and resource block number for the UE to use as a unique physical resource for an SRI in the physical uplink control channel (PUCCH).

Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.

A data storage device having a flash translation layer configured to process file system defragmentation in a manner that substantially avoids physical data movement in the flash. In an example embodiment, a memory controller operates to update its logical-to-physical table to change an association of a physical address of a user data segment from being associated with a source logical address to being associated with a destination logical address of a host defragmentation request without moving user data in a flash memory. This update may reduce the number of instances in which the host addresses the non-contiguous logical address range, which results in a beneficial reduction in the number of input / output commands sent to the data storage device and the associated processing overhead.

The invention discloses a batch demapping method and device and heterogeneous equipment. The method comprises the following steps: after a heterogeneous device allocates a de-mapping request of a heterogeneous component to a de-mapping queue, when the number of de-mapping requests of a first de-mapping queue reaches a set length threshold value, extracting the de-mapping requests with the number corresponding to the set length threshold value to another de-mapping queue; and batch processing is carried out on all the demapping requests of the other demapping queue, so that asynchronous processing of the plurality of demapping requests is realized. And when at least two virtual addresses in virtual addresses in all de-mapping requests de-physical mapping of the other de-mapping queue are continuous virtual addresses, the heterogeneous equipment sends a TLB failure instruction capable of directly losing efficacy of entries of a plurality of TLBs to the TLB, so that the number of sent TLB failure instructions is reduced, and the time delay of batch de-mapping is reduced.

A request that specifies a logical address associated with a host-initiated operation directed at a first portion of a memory device is received. A logical to physical (L2P) table is accessed. The L2P table comprises a mapping between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and is determined to point to an entry in a read cache table. Based on an entry number of the entry in the read cache table, a chunk address of a chunk from among multiple chunks of a read cache is calculated. A physical address that corresponds to the logical address specified by the request is identified by accessing the chunk of read cache. The host-initiated operation is performed at a physical location within the first portion of the memory device corresponding the physical address.

The invention provides a fault transmission analysis method based on a functional physical mapping model, and belongs to the technical field of complex system safety analysis, and the method comprises the following steps: S1, carrying out the preparation before modeling; s2, creating a functional physical mapping model of the system; and S3, carrying out security analysis on the functional physical mapping model. By adopting the fault transmission analysis method based on the functional physical mapping model, the problem of repeated modeling work caused by separation of functional modeling and physical modeling is solved, a method for associating a system function with a physical architecture is provided, the efficiency of safety analysis work based on the model is improved, and the method is suitable for popularization and application. And the integrity and accuracy of hardware fault identification are ensured.

A processing device receives a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device. The processing device accesses a second L2P table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device. A physical location within the second portion of the memory device is identified based on the second L2P table. The physical location corresponds to a portion of a first L2P table that specifies a physical address within the first portion of the memory device that corresponds to the logical address. The physical address is identified based on the portion of the first L2P table and the host-initiated operation is performed at the physical address.