2146 results about "Design data" patented technology

Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for determining a position of inspection data in design data space includes aligning data acquired by an inspection system for alignment sites on a wafer with data for predetermined alignment sites. The method also includes determining positions of the alignment sites on the wafer in design data space based on positions of the predetermined alignment sites in the design data space. In addition, the method includes determining a position of inspection data acquired for the wafer by the inspection system in the design data space based on the positions of the alignment sites on the wafer in the design data space. In one embodiment, the position of the inspection data is determined with sub-pixel accuracy.

Conventional file-based engineering design data for an engineering model are represented by a plurality of components. Each component has a unique identifier, a set of fields, each field having a data type and a data value, and a program which interprets and modifies the fields. The plurality of components are stored in a repository of a server. The repository also stores a history of any changes made to the components. A plurality of client computers are bidirectionally connected to the server. Each client computer may obtain the current version of the components and may send locally edited versions of the components back to the server to replace the current versions in the repository. At the client computer, the user interacts with the components using conventional file-based software. Before locally edited versions of the components are committed to the server to replace the current versions, a synchronization and merging process occurs whereby the latest version of the components are downloaded to the client computer and are compared to the locally edited version of the components to detect resolvable (compatible) and unresolvable (incompatible) conflicts therebetween. The commit process is performed only if no unresolvable conflicts exist between the two versions of the components. To facilitate translation between file-based data and components, a schema is written to "wrap" each of the engineering file formats. Each schema is a set of classes that capture all of the information in the file-based data.

A semiconductor production system has a semiconductor manufacturing apparatus having an exposure unit, a control unit for controlling the exposure unit and a storage device; a semiconductor inspection apparatus having an observation unit, a control unit for controlling the observation unit and a storage device; and a storage device commonly used by the semiconductor manufacturing apparatus and the semiconductor inspection apparatus. The manufacturing apparatus, the inspection apparatus and the commonly used storage device are interconnected via a storage area network. With the semiconductor manufacturing apparatus and the storage device linked together via the storage area network, a large volume of image data or design data can be communicated at high speed, thus improving the system throughput.

Various methods and systems for determining a position of inspection data in design data space are provided. One computer-implemented method includes determining a centroid of an alignment target formed on a wafer using an image of the alignment target acquired by imaging the wafer. The method also includes aligning the centroid to a centroid of a geometrical shape describing the alignment target. In addition, the method includes assigning a design data space position of the centroid of the alignment target as a position of the centroid of the geometrical shape in the design data space. The method further includes determining a position of inspection data acquired for the wafer in the design data space based on the design data space position of the centroid of the alignment target.

A selected scenario of a design ICD document for an integrated enterprise is validated by examining each IDL call of each sequence diagram forming part of the selected scenario. A list of data attributes contained in one or more of the IDL calls are generated and each IDL call associated therewith is generated. A physical location to which each such IDL call is mapped is then associated with the IDL call. By analyzing the IDL calls and associated physical locations on a data attribute-by-data attribute basis, inconsistencies in the physical mapping of the data attributes to the databases forming an IIS for the integrated enterprise may be identified and subsequently corrected.

An improved solution for cooling a data center is provided. In an embodiment of the invention, a data center design that combines physical segregation of hot and cold air streams together with a data hall variable air volume system is provided. The invention is a data center design that resolves air management issues of re-circulation, bypass and load balance. Bypass is airflow supplied by the cooling units that directly returns without cooling servers. Recirculation airflow is server discharge warm air that returns directly without being cooled. Load balance is supplying the required server airflow. An embodiment includes physical segregation of cold and hot air streams and by providing variable air volume to match server load. Air segregation is done by enclosing the hot aisle end and above the cabinets. The air conditioning system provides variable air volume to the data hall (cold side) to meet server demands. The cooling plant consists of variable-air-volume air-cooling system, which cools air by air free cooling (economizer) and is supplemented with mechanical cooling in the warmer seasons.

Design driven inspection/metrology methods and apparatus are provided. A recipe is a set of instructions including wafer processing parameters, inspection parameters, or control parameters for telling an inspection/metrology system how to inspect/measure a wafer. Design data is imported into a recipe extraction system that recognizes instances of target structures and configures recipe parameters accordingly, thereby reducing manual instrument setup time, improving inspection/measurement accuracy, and improving fabrication efficiency.

Methods and systems for generating simulated output for a specimen are provided. One method includes acquiring information for a specimen with one or more computer systems. The information includes at least one of an actual optical image of the specimen, an actual electron beam image of the specimen, and design data for the specimen. The method also includes inputting the information for the specimen into a learning based model. The learning based model is included in one or more components executed by the one or more computer systems. The learning based model is configured for mapping a triangular relationship between optical images, electron beam images, and design data, and the learning based model applies the triangular relationship to the input to thereby generate simulated images for the specimen.

A pattern inspection apparatus is used for inspecting a pattern, such as semiconductor integrated circuit (LSI), liquid crystal panel, and a photomask by using an image of the pattern to-be-inspected and design data for fabricating the pattern to-be-inspected. The pattern inspection apparatus includes a reference pattern generation device for generating a reference pattern represented by one or more lines from design data, an image generation device for generating the image of the pattern to-be-inspected, a detecting device for detecting an edge of the image of the pattern to-be-inspected, and an inspection device for inspecting the pattern to-be-inspected by comparing the edge of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.

Computer-implemented methods, processors, and systems for creating a wafer fabrication process are provided. One computer-implemented method includes determining individual error budgets for different parameters of the wafer fabrication process based on an overall error budget for the wafer fabrication process and simulated images that illustrate how reticle design data will be printed on a wafer at different values of the different parameters. The method also includes creating the wafer fabrication process based on the overall error budget and the individual error budgets.

PCB Logical design data is stored in a database according to a connectivity-based data model. Circuit functional blocks, inputs and outputs of functional blocks, and signals are stored as separate data structures. Those structures may be edited by users at separate clients during concurrent editing sessions. Profile data for each of multiple users specifies logical design data elements accessible by, and PCB design software to be provided to, that user. The PCB design software may be plug-ins executable within a web browser at a client, and the client computers may communicate with the database via the Internet. Layout data may also be stored in the database, with elements of the layout data mapped to elements of the logical design data. Constraint data may also be stored in the database, with elements of the constraint data being mapped to elements of the layout data.

Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method of determining a critical area for a semiconductor design layout is disclosed. The critical area is utilizable to predict yield of a semiconductor device fabricated from such layout. A semiconductor design layout having a plurality of features is first provided. The features have a plurality of polygon shapes which include nonrectangular polygon shapes. Each feature shape has at least one attribute or artifact, such as a vertex or edge. A probability of fail function is calculated based on at least a distance between two feature shape attributes or artifacts. By way of example implementations, a distance between two neighboring feature edges (or vertices) or a distance between two feature edges (or vertices) of the same feature is first determined and then used to calculate the probability of fail function. In a specific aspect, the distances are first used to determine midlines between neighboring features or midlines within a same feature shape, and the midlines are then used to determine the probability of fail function. A critical area of the design layout is then determined based on the determined probability of fail function. In specific implementations, the defect type is a short type defect or an open type defect. In a preferred implementation, the features may have any suitable polygonal shape, as is typical in a design layout.

A Virtual Design Module (VDM) used in a networked design environment generates manufactured product designs that are near optimal in terms of cost and production cycle time by using design data files containing alternative parts and manufacturers information. Numerous product design alternatives are considered and evaluated in terms of design-manufacturing-parts-supplier feasibility and real-time information on cost and production cycle time for realization. The VDM generates a population of new designs with appropriate board design information to allow for design-manufacturer-supplier decision making and determines the feasibility of each member of the current generation of designs and rejects designs that are not feasible. The VDM triggers Mobile Software Agents (MSA) that obtain data for parts availability, cost, lead time and manufacturer data for manufacturing availability, cost and lead time for each feasible member of the current generation of designs and return the data. In one application for printed circuit board design, the VDM evaluates each member of the current generation of designs by calculating cost, lead-time and value using a J function. The VDM then improves board designs through selection and use of board design modifiers. The process continues until optimized designs are obtained. Optimized board designs are output as results to an operator.