91 results about "Logic circuit design" patented technology

A programmable pattern matching engine efficiently parses the contents of network messages for regular expressions and executes pre-defined actions or treatments on those messages that match the regular expressions. The pattern matching engine is preferably a logic circuit designed to perform its pattern matching and execution functions at high speed, e.g., at multi-gigabit per second rates. It includes, among other things, a message buffer for storing the message being evaluated, a decoder circuit for decoding and executing corresponding actions or treatments, and one or more content-addressable memories (CAMs) that are programmed to store the regular expressions used to search the message. The CAM may be associated with a second memory device, such as a random access memory (RAM), as necessary, that is programmed to contain the respective actions or treatments to be applied to messages matching the corresponding CAM entries. The RAM provides its output to the decoder circuit, which, in response, decodes and executes the specified action or treatment.

A method for particle beam lithography, such as electron beam (EB) lithography, includes predefining a stencil design having a plurality of cell patterns with information from a cell library, fabricating the stencil design, synthesizing a functional description into a logic circuit design after predefining the stencil design so that one or more characteristics of the stencil design are considered during synthesizing of the functional description into the logic circuit design, optimizing the logic circuit design, generating a layout design from the optimized logic circuit design, and forming the logic circuit on a substrate according to the stencil design and the layout design.

An automated logic circuit design system uses a common database to store design data at different states of the design process, including data-flow graphs, netlists and layout descriptions. In this way, the need to translate circuit descriptions between tools is eliminated, thus leading to increased speed, flexibility and integration. The common database includes entities, models, cells, pins, busses and nets. The data-flow graphs are stored as graphs, the nodes in a graph as cells, and the edges as busses. Physical design data is available by storing the cells in a model in a KD tree. This allows queries on cells in the netlist located in the layout within arbitrary areas.

An apparatus for and method of generating test cases for testing simulated logic circuit designs. The test cases are basically generated automatically in a random fashion, manually, or using some combination of automatic and manual techniques. Each test case has a corresponding success indication. These test cases are provided to the simulated logic design for execution. Following execution, each test case is rated pass or fail by comparison of the result with the corresponding success indication and a reason for failure is recorded for each failure. A significantly smaller list of test cases is prepared by eliminating test cases which do not have a unique reason for failure. The smaller list of test cases is then presented for a simulation run which requires substantially less simulator time and substantially less manual analysis of the results.

The invention provides a method for verifying a logic circuit design. The method comprises the following steps: generating configuration data and stimulation data through a verifying platform; storing the configuration data and the stimulation data into a target memory; transmitting the configuration data and the stimulation data to an object to be verified through the verifying platform; controlling a reference object to read the configuration data and the stimulation data from the target memory through the verifying platform so that the reference object begins to carry out simulation calculation, wherein the object to be verified is a logic circuit code which implements an algorithm by using a first language, and the reference object is a code for implementing the same algorithm by using a second language; controlling the reference object to finish simulation calculation through the verifying platform; acquiring output data of the reference object by the verifying platform; acquiring output data of the object to be verified through the verifying platform; and determining a verified result of the object to be verified according to the output data of the reference object and the object to be verified. The invention further provides a device for verifying the logic circuit design. The purpose of accurately verifying the object to be verified is achieved.

A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The method comprises choosing at least one master seed to determine initial values as initialization for said logic circuit and/or stimuli data for at least one interface of said logic circuit, choosing at least two different dynamic clock gating configurations for every chosen master seed, executing a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and/or stimuli data based on a corresponding master seed, comparing simulation results of functional simulations against each other executed with said logic circuit for at least two different chosen dynamic clock gating configurations, and reporting an error if said at least two simulation results are not identical.

A layout-data generation equipment includes a logic circuit designing section which designs a logic circuit based on information of the specifications of a semiconductor integrated circuit, a layout-data generation section which creates layout-data based on the logic circuit, a resistance information extraction section which extracts resistance information of a wire from the layout-data, a circuit simulation execution section which executes a circuit simulation, an identification section of current direction which identifies a direction of a current in the wire based on the resistance information of a wire and an execution result of the circuit simulation, a verification section which verifies whether layout-data of the wire breaks a design rule, the design rule being extracted from the information of the specifications of a semiconductor integrated circuit and the verification section generates this verification result, and a data output section which outputs the layout-data.

A buffer circuit for providing dynamic threshold control. The buffer circuit includes a pair of input inverters designed with different skewed threshold potential characteristics. The outputs of the skewed inverters are directed to a logic circuit designed to select either the faster or the slower signal received from the two inverters for transmission to passgate devices coupled to the respective inverters. Only one of the passgate devices is enabled to ensure that only one of the output signals from the two inverters is propagated through the buffer. A latch is preferably connected between the logic circuit and the two passgate devices to maintain the states of the inverters and the logic circuit. The circuit can be designed to define the threshold potential at which switching will occur so as to reduce propagation delay or increase it as desired. It is therefore possible using the circuit to increase transmission rates with minimal affect on signal noise.

The invention provides a low-power-consumption magnetic multi-resistance-state memory cell. The low-power-consumption magnetic multi-resistance-state memory cell successively comprises an anti-ferromagnetic strip film, a first ferromagnetic metal, a first oxide, a second ferromagnetic metal, a first synthetic anti-ferromagnetic layer and a first electrode from bottom to top. The thickness of the anti-ferromagnetic strip film is 0-20 nm. The thickness of the first ferromagnetic metal is 0-3 nm. The thickness of the first oxide is 0-2 nm. The thickness of the second ferromagnetic metal is 0-3 nm. The thickness of the first synthetic anti-ferromagnetic layer is 0-20 nm. The thickness of the first electrode is 10-200 nm. The two ends of the anti-ferromagnetic strip film are respectively plated with a second electrode and a third electrode. Five layers of materials arranged above the anti-ferromagnetic strip film form material magnetic tunnel junctions. According to the technical scheme of the invention, the multi-resistance-state storage can be realized. The low-power-consumption magnetic multi-resistance-state memory cell can be applied not only to the fields of single-bit memory and logic operation, but also the fields of brain-like calculation and the like. Data are written by adopting a unidirectional current, so that the design of memories and logic circuits is simplified. The integration level of circuits is improved and the power consumption of the memory cell is reduced. The process complexity and the manufacturing cost are reduced. Moreover, data are written by using different branches, so that the write operations of different data are independently optimized and designed.

The invention discloses a low-power-consumption magnetic storage unit which consists of six layers from bottom to top, that is, a heavy metal stripy film of 0-20nm thick, a first ferromagnetic metal layer of 0-3nm thick, a first oxide layer of 0-2nm thick, a second ferromagnetic metal layer of 0-3nm thick, a first synthesized antiferromagnetic layer of 0-20nm thick and a first electrode of 10-20nm thick, wherein two ends of the heavy metal stripy film are respectively plated with a second electrode and a third electrode; the five layers of substances above the heavy metal stripy film form magnetic tunnel junctions. According to the low-power-consumption magnetic storage unit, data can be written through one-way current, so that design of a memory and a logic circuit can be simplified, the circuit integration degree is increased, the power consumption of the storage unit is reduced, and the complexity and the manufacturing cost of processes can be reduced; as data are written through different branches, writing operation of different data can be independently optimized and designed conveniently.

Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

A circuit structure analysis unit performs structure analysis for logic circuit information, obtained from an HDL description, and acquires analysis results for function parts, such as a register, an operation unit and a multiplexer. A synthesis instruction generation unit compares the analysis results with a synthesis instruction correlation rule, and automatically generates a synthesis instruction to control a logic synthesis method. Finally, an HDL description output unit outputs a synthesis instruction added HDL description, wherein a synthesis instruction is inserted into the original HDL description. When the synthesis instruction added HDL description is employed in the logic synthesis, starting at the top hierarchical level, a synthesis instruction for the logic circuit is not required in a synthesis execution script.