13 results about "Logic circuit design" patented technology

The invention discloses a high-speed successive approximation analog-to-digital converter based on shared biphase dynamic pre-amplification. The analog-to-digital converter comprises a sampling switch, a capacitive digital-to-analog converter, a shared biphase dynamic pre-amplifier, a latch comparator array and a DAC switch control logic. According to the invention, the pre-amplification function is executed by sharing the dual-phase dynamic pre-amplifier; different amplified sampling signals can be effectively compared and latched by combining a latch comparator array; compared with a traditional SAR ADC with the same single quantization time, the overall quantization time is halved; in addition, the mode of sharing the pre-amplification stage is adopted, so that the chip area is saved, and the influence caused by mismatch between latch comparator arrays can be reduced; meanwhile, the latch comparator array can directly store each quantization result, so that the design difficulty and power consumption of the SAR logic circuit are reduced; according to the invention, the speed and power consumption bottlenecks of the SAR ADC are broken through, and the application scene of the high-speed and low-power consumption SAR ADC is widened.

The present invention provides a discharge device (1) for discharging a high-voltage circuit, the discharge device comprising: an inverter output stage (2) having at least one half-bridge (3a, 3b, 3c), the half-bridge including series-connected semiconductor switches (4a, 5a, 4b, 5b, 4c, 5c) with associated drive circuits (6a, 7a, 6b, 7b, 6c, 7c); and a processor (12) connected via an interface to the drive circuits (6a, 7a, 6b, 7b, 6c, 7c) of the inverter output stage (2), wherein each semiconductor switch (4a, 5a, 4b, 5b, 4c, 5c) has a control input terminal (8a, 9a, 8b, 9b, 8c, 9c) designed for receiving signals from the inverter output stage. (2) The associated drive circuits (6a, 7a, 6b, 7b, 6c, 7c) receive drive signals. The drive circuits (6a, 7a, 6b, 7b, 6c, 7c) of the inverter output stage (2) respectively include safety logic circuits (10a, 11a, 10b, 11b, 10c, 11c). The safety logic circuits are designed to receive configuration signals from the processor (12) of the discharge device (1) through an interface. The configuration signals configure the drive signals to discharge the high-voltage circuit. The drive signals are to be output through the drive circuits (6a, 7a, 6b, 7b, 6c, 7c) to the associated control input terminals (8a, 9a, 8b, 9b, 8c, 9c) of the semiconductor switches (4a, 5a, 4b, 5b, 4c, 5c).

An automated signal electromigration violation resolution process is provided for a logic circuit design of an integrated circuit. The automated resolution process includes simulating, by at least one processor set, signal electromigration (SEM) for a logic circuit design of an integrated circuit, where the simulating generates signal electromigration metrics for the logic circuit design. Further, the process includes automatedly resolving, based on evaluating the signal electromigration metrics for violations, a signal electromigration metric violation of the logic circuit design. The automatedly resolving includes generating a signal electromigration limit-to-metric ratio for the metric violation, and auto-adjusting, using the generated limit-to-metric ratio, a switching factor of the logic circuit design to facilitate resolving the signal electromigration violation. Further, the process includes reevaluating the signal electromigration metrics of the logic circuit design using the auto-adjusted switching factor to confirm automated resolution of the signal electromigration metric violation.

A semiconductor structure and a method of forming the same, wherein the structure includes: a substrate including a base, an active region on the base, a shield region surrounding the active region, and a first insulating region surrounding the shield region, and the first insulating region is in contact with the shield region, and a second insulating region is between part of the active region and the shield region, the active region includes a first region and a second region separated from each other, and a third region surrounding the first region and the second region; a source in the first region; a drain in the second region; a shield structure in the shield region, the shield structure having shield ions therein; a gate on the third region, and part of the gate also extends onto the second insulating region, reducing the leakage between adjacent transistors while meeting the requirements of logic circuit design.

This application discloses a multipolar input switch control circuit, device, and system, relating to the field of electronic circuit technology. The circuit includes a switch module connected between an input power supply and a load, used to control the on / off state of power supply from the input power supply to the load; a first input terminal for receiving a first control signal; a second input terminal for receiving a second control signal; and a logic control module connected to the first input terminal, the second input terminal, and the control terminal of the switch module. When the first input terminal receives a valid low-level signal and / or the second input terminal receives a valid high-level signal, the logic control module controls the switch module to turn on; when neither the first nor the second input terminal receives a valid level signal, the logic control module controls the switch module to turn off. This application, through a pure hardware logic circuit design, can simultaneously accommodate input signals of two different polarities, namely, active low-level and active high-level, offering wide applicability and high reliability.

The invention discloses a logic unit based on a gallium oxide NMOS (N-channel Metal Oxide Semiconductor) field effect transistor. The logic unit comprises a pull-up structure and a pull-down network, the pull-up structure is composed of a gate-drain short circuit or gate-source short circuit gallium oxide NMOS transistor, and the pull-up structure is used for providing a potential pull-up function at an output end and pulling up an output signal to a high level; the pull-down network is formed by connecting at least one gallium oxide NMOS transistor according to a target logic function and a CMOS logic circuit design standard, and the pull-down network is used for providing a potential pull-down function at an output end and pulling down an output signal to a low level GND. The method does not need heterogeneous integration, and has the characteristics of low process difficulty, low cost, strong anti-interference capability and capability of supporting complete logic function realization.

An example detection circuit includes: a bypass circuit designed to selectively bypass an array of LEDs from an LED driver, a first voltage detection circuit designed to compare a voltage at a first terminal of the array of LEDs with a first reference voltage and output a first indication of the comparison, and a logic circuit designed to output a circuit type based on the first indication.

The invention discloses a logic synthesis method and device for logic circuit design and a storage medium, and relates to the field of chip development and chip test.The method comprises the steps that according to an abstract syntax tree of the logic circuit design, the number of operators of all function modules is obtained; traversing the abstract syntax tree on the basis of an operator threshold value in a bottom-to-top exploring mode so as to obtain a plurality of sub-logic circuit designs; transmitting constants searched in the sub-logic circuit designs to adjacent sub-logic circuit designs so as to carry out logic optimization and signal optimization on the sub-logic circuit designs; and performing parallel synthesis on each sub logic circuit design to obtain a comprehensive netlist of the logic circuit design. According to the technical scheme provided by the embodiment of the invention, through the concurrent integration of the sub-logic circuit design obtained by splitting, the integration efficiency of the logic circuit design is improved, the existence of redundant logic in the integration netlist is avoided, and the integration resource area of the logic circuit design is reduced.

The invention relates to the technical field of nuclear reactor shutdown, and discloses a reactor backup safety shutdown method and system.The method comprises the steps that when a system optimization module cannot give an instruction, a first hardware switch is closed, and a first closing instruction is sent out; in response to the first closing instruction, the second hardware switch is closed, a second closing instruction is sent out, and a first safety control instruction is generated through AND logic; and the first safety control instruction directly ignores the optimal module through OR logic and is transmitted to the corresponding safety equipment, and shutdown operation is carried out. A pure hardware switch and a logic circuit are adopted and are completely independent of a network system, the risk that CIM and other modules fail due to network attacks is thoroughly avoided, signals are generated through physical actions, AND logic and OR logic are combined, and the reliability of instruction generation and transmission is ensured. And a hardware switch and a logic circuit are simple in design, easy to integrate into an existing nuclear power plant control system, suitable for various reactor types, low in implementation cost and convenient to maintain.

The application discloses a three-value single-variable up-spin logic and down-spin logic circuit based on a memristor. M 1, a second memristor M 2, a first NMOS tube T 1 and a second NMOS tube T 2 are composed of; the three-value single-variable down-spin logic circuit based on the memristor is composed of a third memristor M 3, a fourth memristor M 4, a fifth memristor M 5, a third NMOS tube T 3, a fourth NMOS tube T 4 and a fifth NMOS tube T 5 are composed of. The three-value single-variable up-spin and down-spin logic circuit based on the memristor in the application has clear and simple circuit model structure and is easy to realize, and has important significance for application research in many fields such as multi-value digital logic circuit design.

A method of verifying a logic circuit design by a hardware emulation system, includes, in part, receiving a netlist of the logic circuit design configured to operate in response to positive edges of a first clock signal, and transforming each of a first multitude of flip-flops disposed in the logic circuit design to a dual-enable flip-flop configured to operate in response to positive edges of a second clock signal thereby to generate a transformed logic circuit design. The state of the logic circuit design after 2k cycles of the first clock is the same as a state of the transformed logic circuit design after k cycles of the second clock.

The application discloses a system and method of image diffuse wave spectrum technology based on FPGA, which can realize the logic circuit design of the image diffuse wave spectrum algorithm with high parallelism, real-time and stability by using FPGA, simplify the experimental operation and greatly improve the acquisition speed of the experimental results. Compared with the prior art, the application realizes the operation of the diffuse wave spectrum algorithm in high speed and real time by using the design of the parallelism of the CMOS camera, the FPGA chip and the peripheral storage circuit, reduces the cost of the system, and makes sufficient preparation for the miniaturization of the system.

The invention discloses a three-valued circulation logic circuit based on a threshold type memristor and application of the three-valued circulation logic circuit, and belongs to the technical field of image encryption. Comprising two direct-current power supplies, an STI circuit, an operational amplifier and a voltage division circuit, the voltage division circuit comprises a VTEAM memristor; wherein one direct-current power supply supplies power to the main circuit, the other direct-current power supply supplies working voltage to the operational amplifier, input voltage is converted by the STI circuit and then input to the operational amplifier for voltage stabilization, output voltage of the operational amplifier is compared with threshold voltage of the VTEAM memristor, corresponding resistance is generated for voltage division, and therefore three kinds of voltage are output. And three-valued logic can be mapped. The memristor has remarkable feasibility in the design of a three-valued logic circuit, has the advantages of high performance, low power consumption, high integration level and the like, and provides a valuable implementation path for storage and calculation integration and security encryption application in the future.