Reversible-logic-based 16-bit carry look-ahead adder

A technology of advanced carry and adder, which is applied in the field of microelectronics, can solve the problem of high power consumption of devices and achieve the effect of reducing energy loss

Inactive Publication Date: 2013-08-07
CHONGQING UNIV OF POSTS & TELECOMM
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to design a 16-bit carry-ahead adder using reversible logic gates for the high power consumption defect of the device in the prior art digital circuit, which can greatly reduce the power consumption of the device and reduce the time delay

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  • Reversible-logic-based 16-bit carry look-ahead adder

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Embodiment Construction

[0013] Such as figure 1 Shown is a 16-bit reversible carry-look-ahead adder. It consists of four 4-bit reversible carry-look-ahead adders cascaded, and its quantum cost is 552. The adder has 169 input terminals, of which A0-A15, B0-B15, and C0 are effective input terminals, and the remaining 136 input terminals are redundant inputs, namely the '1' input port and the '0' input port in the figure. The adder also has 169 output terminals, among which S0-S15 and C16 are effective output terminals, and the remaining 152 output terminals are garbage outputs, that is, the 'g' output ports in the figure. Such as figure 1 As shown, the 4-bit results S0-S3, S4-S7, S8-S11 and S12-S15 of the adder are calculated by the 4-bit reversible carry-look-ahead adder of each stage, and the corresponding carry output C4 of the stage , C8, C12 and C16, input three of C4, C8 and C12 (the first, second and third carry outputs) in the carry output of the current stage to the corresponding carry inpu...

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Abstract

The invention discloses a 16-bit carry look-ahead adder based on reversible logic and relates to the microelectronic technical field. The adder is formed by cascading of four stages of 4-bit reversible carry look-ahead adders. The 4-bit reversible carry look-ahead adder at each stage calculates 4-bit in-place calculation results of the stage and corresponding carry outputs respectively; a first carry output, a second carry output and a third carry output are respectively input into a corresponding carry input end of the 4-bit reversible carry look-ahead adder of the next stage to serve as a carry input, and a fourth carry output serves as a carry output of a 16-bit reversible carry look-ahead adder. According to the 16-bit carry look-ahead adder, a reversible logic design method is used for achieving the 16-bit carry look-ahead adder, the circuit delay can be reduced greatly, and simultaneously, by following the reversible logic circuit design, energy losses can be reduced, and circuit losses can even be completely eradicated.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to the design of a digital circuit look-ahead carry adder. Background technique [0002] With the development of today's integrated circuit design and technology, electronic engineers put more and more high-frequency logic components into smaller and smaller integrated circuits. At the same time, the power consumption and heating problems of logic components have attracted more and more people's attention, because these problems not only lead to waste of resources, but also cause damage to logic components due to overheating. According to Landauer's principle (Landauer's principle): any logically irreversible operation of information, every time one bit of information is erased, ln2x kT of heat will inevitably be generated, k represents the Boltzmann constant, and T represents the temperature. All the unnecessary heat generated in the logic components will cause energy los...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/506G06F7/507
Inventor 庞宇王骏超林金朝李章勇李国权周前能王绍全闫亚锋钱骏洲蔡骁
Owner CHONGQING UNIV OF POSTS & TELECOMM
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