879 results about "16-bit" patented technology

A Point to Multipoint (PMP) multi-hop relay network includes a base station, one or more relay stations and one or more subscriber stations. Active service flows in a PMP multi-hop relay network have a 16-bit connection identifier (CID). A CID defines the connection that a packet is servicing. Before traffic can be transmitted, the path through the network, and the association of CIDs with respective hops needs to be established. The CID mapping relationship from the ingress air link to the egress air link at each relay station is first set up, which is then followed by a traffic phase where the CID mapping relationship is used to route traffic from a base station to a subscriber station.

A packet encapsulation scheme for multiplexing application sessions—Lightweight IP Encapsulation (LIPE)—is described. An LIPE packet comprises at least one multiplexing header (NH) and associated multimedia data packet (MDP). The LIPE packet uses UDP/IP as transport. An MH field further comprises a 16-bit a user identifier (UID) field, an 11 bit length indicator (LNG) field, a 1 bit “more” (M) field and an optional payload type/class of service (PT/CoS) field comprising 8 bits.

The present invention is to provide a digital video-audio signal recording and reproducing apparatus that allows the number of channels of audio data and the data width per sample to be changed corresponding to user's settings. 24-bit/sample audio data that is input as serial data to Ch 1 of the digital video-audio signal recording and reproducing apparatus is separated into high order 16 bits and low order eight bits. The high order 16 bits are recorded in a region of Ch 1 of a record medium. The low order eight bits are stored to a region of low order eight bits of Ch 3 paired with Ch 1 of the record medium. Mode information that represents that 24-bit data is separated into paired channels is added to record data each edit unit of video data. When dat is reproduced, data of paired channels is combined corresponding to the mode information so as to restore 24-bit data. Since the 24-bit data is treated as 16-bit data, the record format of 16-bit data can be used for the 24-bit data.

The present invention allows for processing classification and/or security filtering rules by using bitmaps as representations. In one instance, the packet header involved in the packet classification is divided into sections (fields) such as 16 bit portions. Once, this is performed, a data lookup table is built for each of the packet header fields. In particular, a bitmap is created representing which filter rules match a certain packet header field value. The created data lookup tables, typically one for each packet header field, are merged to form intermediate level data lookup tables. The intermediate level data lookup tables are continuously merged until one final data lookup table is formed. The result of the final data lookup table represents all the possible packets to be classified. Thus, each final data entry has a bitmap representing the filtering rules that matches this entry. The bitmap can be used to selectively provide a desired result of the classification. For instance, a first matching rule is represented by the first bit set in the bitmap; the best matching rule is determined by processing the bitmap and selecting the most appropriate rule; and a complete set of rules that match is represented by the full bits set in the bitmap.

The invention discloses a fixed-point method for a floating-point operation. The method comprises the steps that according to a preset numerical range and the calculation precision requirement, the exponents and significant bits of adjustable-precision floating-point data are adjusted, and the parameter data in a single-precision floating-point format are converted into adjustable-precision floating-point data; when calculating is carried out, the adjustable-precision floating-point data are converted into fixed-point data and used for calculation, and an intermediate result generated by calculation is converted into adjustable-precision floating-point data; a final result is generated after all calculation; and the final result is converted to data in the single-precision floating-point format. According to the invention, standard floating-point data can be represented with a 16-bit bit width or a smaller bit width to realize fixed-point conversion of the floating-point operation; the storage space is saved; the operation performance is improved; and the calculation precision is not influenced.

A multi-level semiconductor memory device for storing multi-level data having three or more values is implemented by utilizing a nonvolatile memory device for storing 2-valued data. Identification of successive 16-bit data externally applied is performed with external address bit AA [2], and a storage block is selected with external address bit AA [23]. Upper word data LW and lower word data UW are compressed into byte data of 8 bits; respectively, and stored in a memory cell array.

The invention discloses a singlechip-based induction motor variable frequency speed regulation control system. The system comprises a main circuit, an auxiliary power circuit, an inverter circuit, a control part, an over-current protection circuit, a rotation speed detection circuit and other peripheral circuits. A 16-bit high-performance signal controller dsPIC30F4011 which is produced by the Microchip Company is used as a control core by the system to perform speed regulation based on vector control motor excitation. A digital signal controller dsPIC30F4011 of the America Microchip Technology Company is used as a chip special for motor control, a digital signal processor (DSP) inner core is embedded, and the chip has quick data processing capacity and is provided with abundant input and output equipment and interface circuits; an intelligent power module (IPM) IRAMSIOUP 60A of the IR Company is an inverter switching device, so that the variable frequency speed regulation control system of an asynchronous motor is constructed; and the system has the characteristics that the system is simple to drive and easy to realize.

The invention provides apparatus for controlling a search lamp using a wireless transmitter and receiver. The transmitter responds to user inputs by providing a wireless digitally encoded modulation signal containing information indicating at least one operation in a set of operations the search lamp is able to perform. The receiver responds to the wireless digitally encoded modulation signal by providing a control signal for controlling the functionality of the search lamp. The functionality may include, for example, moving the search lamp left/right and/or up/down, a sweep on/off @ ±45 degrees; X/Y/Z movement (Z when motors run simultaneously); Diagonal sweep (motors run simultaneously); Fast/Slow sweep (50%/100%). The transmitter and receiver are programmable to communicate on a unique 16 bit digital code setting that provides about 65K different code settings, which may also include a random code setting.

A combination CD-ROM and MP3 recorder/player playing a CD-ROM decodes 16-bit ISO standard code words into an audio wave form converts this wave form to sound while encoding and digitizing the wave form into 24-bit MP3 format digital data. To conserve power the MP3 data is buffered in a solid state memory, preferably of the FLASH or DRAM type, before being written to a hard disk. Both reading of the CD/ROM and encoding the read contents as MP3 data, and interchange of MP3 data with other recorder/players, can be accomplished at greater than real-time play rates, permitting that, most typically, some 1200+ musical works can transferred expediently.

A semiconductor synchronous dynamic random access memory (SDRAM) device capable of correcting bits having a low error rate in a Pause Refresh Tail distribution and of reducing a data holding current by lengthening a refresh period so that the refresh period exceeds a period for a Pause Refresh real power. The semiconductor memory device is made up of a 16-bit SDRAM having a Hamming Code and including an ECC (Error Correcting Code) circuit made up of an encoding circuit controlled by a first test signal to output a parity bit corresponding to an information bit, a decoding circuit controlled by second test signal to output an error location detecting signal indicating an error bit in codeword, and an error correcting circuit controlled by a third test signal to input an error location detecting signal and to output an error bit in a reverse manner.

The invention relates to a video camera system of discovering and tracking automatically abnormal targets. Camera lens, video camera, image collecting unit, image processing unit, turntable control unit, turntable consist of a closed loop control system. The image collecting unit converts standard television signals output by the camera into 16-bit digital video signals. The image processing unit outputs the center position of the biggest abnormal target after detecting abnormal targets, and outputs the zooming control of lens of the camera according to the size of targets and the position in the visual field. The turntable control unit gives an alarm to the monitoring center, controls rotation of the turntable to make the light axis of the camera installed in the turntable point to the abnormal targets detected, and adjusts automatically the zooming multiple to make the monitoring center obtain clear and intact video image about the abnormal targets. The invention realizes the quick detection and track about invading targets.

For a processor having instruction codes of two instruction lengths (16 bits and 32 bits), methods of locating the instruction codes are limited to two types: (1) two 16-bit instruction codes are stored within 32-bit word boundaries, and (2) a single 32-bit instruction code is stored intactly within the 32-bit word boundaries. A branch destination address is specified only on the 32-bit word boundary. The MSB of each instruction code serves as a 1-bit instruction length identifier for controlling the execution sequence of the instruction codes. This provides two transfer paths from an instruction fetch portion to an instruction decode portion within the processor, achieving reduction in code side and in the amount of hardware and, accordingly, the increase in operating speed.

The CRC for the CPS Header of an ATM AAL2 cell is generated by a CRC generator which uses the 8 bits of the CID field to generate partial 5 bits CRCs which are loaded in a first table. The 6 bits LI field and 5 bits UUI field are added to the partial 5 bits CRC to form 16 bits. The CRC generator uses the 2<16 >bits to generate a second CRC table. The CRC for a particular CPS header is generated by correlating bits in the CID field, Li field and UUI field with the two tables.

Channel coupling for an AC-3 encoder, using mixed precision computations and 16-bit coupling coefficient calculations for channels with 32-bit frequency coefficients.

Systems and methods compress and decompress 16 bit data. The 16 bit data may be signed or unsigned and represented in a fixed point or floating point format. A fixed block size of data is compressed into a fixed length format. Data compressed using a medium quality compression scheme may be efficiently decompressed in hardware. Data may be efficiently compressed and decompressed in hardware using a high quality compression scheme. The high quality compression scheme has a lower compression ratio compared with the medium quality compression scheme, but is near lossless in terms of quality.

An IP routing lookup scheme and system for a multi-gigabit switching router which can reach 3 memory accesses in the worst case using memory size less than 512 KB is disclosed. The invention can compress a routing table with 40,000 routing entries into a forwarding table of 450–470 Kbytes. According to the present invention, a segmentation table storage device stores a next hop or a pointer for looking up a next hop for an incoming packet having prefix length less than or equal to 16 bits. The Next Hop Array storage device is for storing the next hops for a packet having prefix length larger than 16 bits and offset length less than or equal to 3 bits. A Compressed Next Hop Array storage device is encoded and decoded according to a Code Word Array storage device. The Compressed Next Hop Array storage device stores next hops for the incoming packet having prefix length larger than 16 bits and offset length larger than 3 bits. Thus, in the worst case, an output port for a route prefix can be found in 3 memory accesses.

A processor generates a mode indication based on two or more other indications. The mode indication is indicative of whether or not a particular mode is active in the processor. Each indication is stored in a storage location which is addressable via a different instruction. In one embodiment, a long mode in which a 64 bit operating mode is selectable in addition to 32 bit and 16 bit modes may be activated via a long mode active indication. The long mode active indication may be generated by the processor, and may indicate that long mode is active if paging is enabled and a long mode enable indication indicates that long mode is enabled. In this manner, long mode may be activated after paging is enabled (with a set of long mode page tables indicated by the page table base address).

The invention provides a super-capacitor energy storage and transfer-based active equalization system and method for a lithium battery pack. The active equalization system comprises an equalization main controller, a switch array, a two-way DC/DC, a super-capacitor, a current detection and power calculation device, a 16-bit decoder and a drive circuit, wherein the equalization main controller obtains a single battery voltage inspection value as an equalization state basis and any to-be-equalized battery is gated by the switch array to be connected to an equalization bus; the preceding stage of the full-bridge two-way DC/DC with an adjustable ratio is connected with the equalization bus and the backward stage is connected with the super-capacitor; the power of the equalization loss is calculated through the current detection and power calculation device; the equalization main controller achieves charging for the super-capacitor by a high-power battery through the two-way DC/DC; and the super-capacitor stores the power and then discharges a low-power battery through the two-way DC/DC until the equalization state. The power is stored and transferred through the super-capacitor; active equalization for the lithium battery pack is achieved; and the super-capacitor energy storage and transfer-based active equalization system has an important significance for prolonging of the lifetime of the lithium battery pack.