42 results about "16-bit" patented technology

The invention provides a large language model quantification method, related equipment and a computer program product, and the method comprises the steps: carrying out the reasoning of a to-be-quantized large language model through calibration data, obtaining the activation of the large language model, and carrying out the statistics of the activation distribution of a target layer according to channels; calculating a smoothing factor of each channel according to the activation distribution; compensating the weight of the target layer channel by channel according to the smoothing factor to obtain a compensated weight; performing 4-bit quantization on the compensated weight; in the model reasoning process, activation of a target layer is smoothed, and 16-bit quantization is carried out on the smoothed activation. According to the method, a W4A16 quantification scheme is adopted, compared with W8A8, the weight storage amount is compressed by half, meanwhile, the precision loss is controlled to be smaller than 3%, and deployment of a large language model on edge equipment is facilitated.

The invention discloses a hybrid precision storage and calculation control circuit based on a Sense-Switch type pFLASH. The hybrid precision storage and calculation control circuit comprises an NOR FLASH type SSpF storage and calculation array, a hybrid precision array controller, a hybrid precision shift adder and an AD module. The NOR FLASH type SSpF storage and calculation array is used for realizing convolution operation; the mixed precision array controller divides the NOR FLASH type SSpF memory calculation array according to the configured calculation precision, and completes input control and output sampling of 4, 8 or 16-bit convolution operation, and 4-bit weight programming and reading; the mixing precision shift adder performs shift addition on the output of the mixing precision array controller according to the sequence and the channel according to the configured calculation precision to obtain a 4, 8 or 16-bit convolution calculation result; the AD module is used for converting current output of the NOR FLASH type SSpF storage array into voltage output and converting an analog signal into a 4-bit digital signal. According to the method, 4, 8 or 16-bit convolution calculation can be realized in parallel, and the calculation precision can be configured.

The invention provides a block storage method and device for a sparse matrix, and is applied to the field of data storage.The method comprises the steps that block storage is conducted on the sparse matrix through a target sparse storage format, the target sparse storage format comprises a first-layer storage structure, a second-layer storage structure and a third-layer storage structure, comprising the following steps: in a first-layer storage structure, dividing a sparse matrix into blocks with the row and column number of 16 * 16; in the second-layer storage structure, the blocks are divided into sub-blocks with the row and column number being 4 * 4, the positions of non-zero sub-blocks in the sub-blocks are marked based on a 16-bit first-level bitmap, and the non-zero sub-blocks are stored; in the third-layer storage structure, marking the positions of the non-zero elements in the non-zero sub-blocks based on a 16-bit secondary bitmap, and positioning the non-zero element values of the non-zero elements through a secondary value pointer; according to the invention, the storage compatibility among different sparse cores can be realized.

Procedures, methods, architectures, apparatuses, systems, devices, and computer program products directed to improved linear model estimation for template-based video coding are provided. Included therein is a method comprising determining minimum and maximum (“min / max”) values of luma and chroma samples neighboring a coding block, wherein the min / max chroma values correspond to the min / max luma values; determining a first linear model parameter of a template-based video coding technique (i) based on a single look-up table and the min / max chroma values and (ii) at a precision no greater than 16 bits; determining a second linear model parameter of the template-based video coding technique (i) based on the first linear model parameter and the minimum chroma and luma values and (ii) at a precision no greater than 16 bits; and predicting chroma samples of the coding block based on reconstructed luma samples of the coding block and the first and second linear model parameters.

The embodiment of the invention provides a frequency coding method and device, a storage medium and an electronic device. The method comprises the following steps: acquiring a central wavelength frequency value to be coded; and coding the central wavelength frequency value through a target BIT representation method, the number of bits adopted by the target BIT representation method being greater than 16 BITs, and the target BIT representation method adopting at least 7 consecutive BITs to extend the low frequency part of the L wave band. By adopting the technical scheme, the problem that the existing 16GBIT coding method cannot cover all wave bands of the C + L wave band in the related technology is solved.

The invention provides a four-bit fixed-point BANKROUND implementation method based on simd. The four-bit fixed-point BANKROUND implementation method based on simd comprises the steps that S1, floating point conversion shaping and four-bit fixed-point operation are carried out; s2, performing right shift by 4 bits, i.e., after multiplying by 16, dividing by 16 for reduction, retaining an integer part of the data, and reducing the fixed-point data into original data; s3, retaining a decimal part of the data, wherein the decimal part is expressed as result3 = result1amp; 0 * 00001111, 0 * 00001111; s4, judging whether a decimal part is 0.5 or not: judging whether the decimal part is equal to 0.5 or not in banker rounding; s5, according to the BANKROUND standard, the condition of entering 1 needs to be met at the same time: case 1) decimal part gt; the condition is completed in the process of S1, and all the parts larger than or equal to 0.5 directly enter 1; 2) the decimal part is equal to 0.5, and the unit of the integer part needs to be ensured to be an odd number; s6, setting each 16-bit number meeting the condition in each result5 as 1, and setting each 16-bit number not meeting the condition as 0; and S7, subtracting the calculation result in the step S6 from the result after shifting calculated in the step S2.

A method for performing segment routing in a data communications network is disclosed. A routing node (106) along path between sender node (102) and receiver node (104) receives data packet with destination address (302). The destination address includes a first group of bits (306) with fixed amount of most significant bits, a second group of bits (308) specifying first segment, and a third group of bits (310) specifying second segment. The second and third groups have equal fixed amounts of bits and the distance in the destination header between the second group of bits and the third group of bits is a multiple of 16 bits. The routing node (106) determines if the first and second groups match its address. If matched, the routing node (106) generates a modified destination address (304) by swapping the second and third groups of bits.

The invention provides a simd-based double magnification bilinear interpolation implementation method, which aims at a double magnification ratio, so that the zoom coefficients in x and y directions are 0.5, and comprises the following steps: S1, amplifying the original resolution by 2 * 2; s2, boundary point special calculation: carrying out special processing on a first row / a last row / a first column / a last column; s3, core calculation of four fixed points: S3.1, parallel calculation of two rows and two columns, and simultaneous calculation of dst (0, 0), dst (1, 0), dst (0, 1) and dst (1, 1) which respectively correspond to coordinates x and y: dst (x, y), dst (x + 1, y), dst (x, y + 1), dst (x + 1, y + 1); s3.2, calculating and multiplying the input pixel points by the corresponding weights respectively; s3.3, multiplying the input data by the weight in the w direction, and expanding the data to 16 bits to prevent overflow; and S4, according to a final result, the data is quantized to 8 bits by using bankround. According to the method, the scaling is twice scaling, 4-bit fixed-point calculation is used in the process, the calculation efficiency and accuracy are improved, floating points are converted into bit fixed-point calculation, and the calculation amount is reduced. The input data are reused, and the data repeated carrying time is shortened.

The application discloses a kind of self-adapting polar code decoder and decoding method, belong to wireless communication technical field, the present application will channel log likelihood ratio LLR be stored into memory, controller receives node distribution pattern after on-line identification R0, R1, REP, SPC four kinds of special nodes, pruning and generating 16 bit decoding instruction;Computing unit array PEA reads LLR from memory and executes operation, result is written back;When encountering special node, node processing unit NPU reads LLR from memory and calculates path metric PM, generates decision result and path screening result through 2L to L filter;Decision result sends part and computing unit PSU to carry out single-cycle cross-level part and calculation, and then the result is fed back to PEA;Path screening result sends path management module to adjust memory pointer;The present application supports arbitrary confidence order decoding, significantly reduces delay and system overhead, and is suitable for sensory auxiliary, AI auxiliary and physical layer security scene.

This invention provides an optimized method for grayscale image mean preprocessing. For grayscale images, 128 image data points are loaded each time. One register loads 16 8-bit data points, using eight variable registers: vrd0, vrd2, vrd4, vrd6, vrd8, vrd10, vrd12, and vrd14. The loaded register data is then converted to 16 bits, meaning 16 registers are used to store the data. These variable registers are reused, and eight more variable registers are added to generate vrd0, vrd1, ..., vrd12. 5. Use a register `sum_h0` to accumulate 16-bit data. When `sum_h0` accumulates 256 times, shift the data right by 8 bits (equivalent to dividing by 256). Then, use a new register `sum_h1` to accumulate the shifted `sum_h0`, while `sum_h0` is initialized to 0. Then, re-accumulate the newly loaded data. Use `sum_h1` to accumulate the shifted `sum_h0`. When `sum_h1` accumulates 256 times, save the result of `sum_h1` to an array. Finally, accumulate the data in the array again and calculate the average. This optimization improves speed by 40 times.

The invention relates to a compression method and device for user portrait label data, and belongs to the technical field of data compress.The method comprises the steps that at least one to-be-queried field is obtained from a database according to a user portrait label, a plurality of corresponding user ids are obtained according to the to-be-queried field to serve as to-be-stored user ids, the user ids are of an int type, and the to-be-stored user ids are stored according to the to-be-queried field; each user id is represented by 32 bits, each user id in the to-be-stored user id is divided into high 8 bits, middle-high 8 bits and low 16 bits, and the to-be-stored user id is compressed and stored according to the high 8 bits, the middle-high 8 bits and the low 16 bits; and the plurality of user ids corresponding to the user portrait label are compressed and stored based on high 8 bits, middle-high 8 bits and low 16 bits, so that the storage space for storing the user ids can be effectively reduced, and the storage cost is saved.

This invention provides a lookup table method for half-precision floating-point number FP16, including: S1, 1) NNA quantization input; 2) Int16 input: 16 bits output to Lbit, S=0 indicates a positive number, V=0 indicates no overflow; Int16 input, FP16 input: converted to FPi; lookup table value FPi; obtain offset(FPPi), scale_n(FPPi), scale_p(FPPi); add offset, according to the result: positive multiply by scale_p, negative multiply by scale_n; obtain: absolute value converted to integer, take the lower 16 bits and output to Lbit, overflow 16 bits V=1, otherwise V=0, output overflow to V, output sign bit to S; S2, obtain SVLbit 16-bit positive integer; S3, according to LU_Table, SAT_T0, IDX0_T, get: V=1: take the value SAT_T0 (S=1) or SAT_T1 (S=0), V=0: take the high 5 bits of Lbit as idx, S=1: if idx≥IDX0_T1 take the value SAT_T0, S=0: idx+=IDX0_T1, if idx>31 take the value SAT_T1, take the low 11 bits of Lbit as dx, use idx and dx to look up the table and calculate y; S4, lookup result y (FPin); true value output: convert to FP16; quantization output: get ofbit, convert to integer and saturate to ofbit unsigned number; S5, NNA quantization output or XOR RAM port.

The invention relates to the field of computer equipment based on a specific calculation model, can be used for designing neuromorphic processor equipment, and can also be used for the fields of central and graphics processor equipment and the like. The pipelined multiplier may be part of an arithmetic coprocessor of a neuromorphic VLSI (very large scale integrated circuit) processor core, intended to perform a multiplication operation on two binary operands, or a combined multiplication-addition operation (MAC operation) on three operands. The two primary operands are integers in the range from-32768 to 32767, 16 bits long, represented in additional codes. The third additional operand of the MAC operation and the operand of the operation result are 32-bit integers presented in additional codes. The pipelined multiplier includes the use of the claimed invention, capable of quickly performing a large number of multiplications or combined multiply-add operations in a pipelined operation mode, i.e., in each operation cycle, receiving a new set of operand values at the input and generating a new result at the output based on the old set of operand values.

A method for transmitting data over a serial bus includes transmitting two bits of data over a first wire of a serial bus in each cycle of a plurality of cycles of a transmitter clock signal, transmitting a synchronization pattern over a second wire of the serial bus in a first cycle in the plurality of cycles of the transmitter clock signal, and transmitting two bits of data over the second wire of the serial bus in each cycle of the plurality of cycles of the transmitter clock signal except for the first cycle in the plurality of cycles of the transmitter clock signal. In one example, 16 bits of data and 2 parity bits are transmitted in five cycles of the plurality of cycles of the transmitter clock signal.

The embodiment of the invention discloses a data processing method and a related device, which are applied to the technical field of mobile communication and are used for reducing the overhead of a communication device during communication. The method is applied to a first communication device, and comprises the following steps: acquiring first information to be sent; sending the first information and a first cyclic redundancy check (CRC) code corresponding to the first information to a second communication device, wherein the length of the first CRC code is less than or equal to 16 bits; wherein when the first information does not include the first control information and the length of the first information is less than a first threshold value, the length of the first CRC code is 0 bit, and the first control information is used for scheduling the second communication device.

Message faulting is an expensive problem for 5G and especially for 6G due to increased pathloss and network faulting. Current message correction procedures rely on bulky FEC codes or automatic retransmission requests, further burdening the network. Disclosed are methods for a receiver to recognize a faulted message, identify the faulted message elements, and determine the corrected value for each fault, thereby recovering the correct message without a retransmission. Autonomous error correction within a receiver can be performed without network assistance or standards because the receiver has enough data, in the form of the received waveforms and the included error-detection code (usually just 16 bits) to find the corrected version internally. Reduced dependence on retransmissions and multiple code transmissions will alleviate network crowding while preserving the desired reliability and latency goals of the recipient.

The application discloses a 64-bit fixed-point trigonometric function operation method of an ARM processor, which comprises the following steps: firstly, defining a 64-bit fixed-point number and a data type conversion mechanism; defining a sin trigonometric function table based on a 32-bit fixed-point number and storing the table in the form of integer data; secondly, converting a floating-point number to be operated into a 64-bit fixed-point number, performing a modulus operation on the 64-bit fixed-point number and a 64-bit fixed-point number form of π / 2, obtaining a trigonometric function variable, representing the variable in the form of integer data, and then incrementally searching a table to obtain a sin value of the converted 32-bit fixed-point number in the sin trigonometric function table; using the 64-bit fixed-point number to represent and using linear interpolation to compensate the value of the lower 16 bits of the decimal point, so as to obtain a sin value corresponding to the 64-bit fixed-point number; and finally, according to the sin value, using a trigonometric function transformation formula to calculate the values of trigonometric functions cos and tan. The operation method can realize high-precision decimal trigonometric function operation with high operation speed in the ARM processor.

To satisfactorily transmit uncompressed RAW data between devices. A transmission unit transmits uncompressed RAW data to an external device via an HDMI transmission path. For example, the uncompressed RAW data is uncompressed RAW data in a Bayer layout. Furthermore, for example, the bit depth of each pixel of the uncompressed RAW data is 16 bits, and the transmission unit transmits the uncompressed RAW data using the YC 12 bit transfer mode. For example, the transmission unit transmits metadata related to the uncompressed RAW data together with the uncompressed RAW data.

The invention discloses an intelligent communication system based on network management and control. An operation method of the system comprises the following steps: carrying out coding optimization management on the network intelligent communication system; performing physical layer and link control on the network intelligent communication system; operation analysis control management of the network intelligent communication system is carried out; subscription storage processing of the network intelligent communication system is carried out; the coding optimization management of the network intelligent communication system comprises the following steps of: performing network access configuration processing of terminal equipment through a method of coding together with a multicast address and a data frame length, identifying a field to which distribution network data belongs by high 7 bits of a coded 23-bit low-order bit, representing coded data by low 16 bits, and representing a field to which distribution network data belongs by high 7 bits of the coded 23-bit low-order bit; and representing the serial number of each frame of data by the data frame length. The step of controlling the physical layer and the link of the network intelligent communication system comprises the step of carrying out information communication transmission by adopting a Wi-Fi wireless signal in the physical layer of the network intelligent communication system. The system has the characteristics of high management control efficiency and high stability.

The invention relates to the technical field of data storage, and discloses a method for automatically identifying the Die capacity of a memory chip, which comprises the following steps of: reading a register MR8 through a mode of the memory chip and acquiring the capacity of a single Die; the number of Ranks and the number of Channel are identified through pins; the IO bit width of a single channel is judged, when the bit width is 16 bits, the number S = 1 is allocated according to the bit width, and the first theoretical Die total capacity is calculated according to the Rank number, the Channel number and the number S = 1; comparing the first theoretical Die total capacity with the standard capacity, if the first theoretical Die total capacity is consistent with the standard capacity, passing verification, and if not, triggering an error reporting mechanism. According to the method, two mainstream IO bit width specifications of the LPDDR5 memory are covered, and the problem that no standard verification process exists in an 8-bit Die parallel working scene is solved.

Disclosed in embodiments of the present application are a data processing method and a related apparatus, which are applied to the technical field of mobile communications, and are used for reducing the overhead of communication apparatuses during communication. The method is applied to a first communication apparatus. The method comprises: acquiring first information to be sent; and sending to a second communication apparatus the first information and a first cyclic redundancy check (CRC) code corresponding to the first information, the length of the first CRC code being less than or equal to 16 bits, wherein when the first information does not comprise first control information and the length of the first information is less than a first threshold, the length of the first CRC code is 0 bit, and the first control information is used for scheduling the second communication apparatus.

The invention provides a matmul transpose weight splitting method based on simd, in the method, weight splitting is formed by combining a series of 2bit transpose logics, an input column is transposed to an output row, the method is suitable for matmul calculation in any shape, and the method comprises the following steps: S1, reading data in a first row, namely data before transpose, from an input address by using an mx512lad (vr0, 0, input tradr, 0) instruction; s2, aggregating the 4 bit data together by using an mx512gt4bi instruction; s3, all the 2bits are aggregated together by using an mx512gt2bi instruction; s4, all the 16 bits are aggregated together by using an mx512th instruction; and S5, transposing the generated rows of data by using an mx512ilve instruction and an mx512ilvo instruction to obtain a weight splitting target output format. According to the method, additional input and output space development is reduced; a large number of la and sa instructions are reduced; and a large number of redundant instructions are removed.

Provided are processes, methods, architectures, apparatus, systems, devices, and computer program products for improved linear model estimation for template-based video decoding. A method is included, the method comprising: determining minimum and maximum ("min / max") values ​​of luma and chroma samples adjacent to a coding block, wherein the minimum / maximum chroma values ​​correspond to minimum / maximum luma values; (i) determining first linear model parameters for a template-based video decoding technique based on a single lookup table and the minimum / maximum chroma values ​​and (ii) with no more than 16 bits of precision; (i) determining second linear model parameters for the template-based video decoding technique based on the first linear model parameters and the minimum chroma and luma values ​​and (ii) with no more than 16 bits of precision; and predicting chroma samples of the coding block based on reconstructed luma samples of the coding block and the first and second linear model parameters.

The invention provides an optimization method for image interpolation scaling. The optimization method comprises the following steps: S1, extracting data from S by using a lu1q instruction; s2, using a shufv instruction to extract data from registers in0, in1, in2 and in3 through a register cvtbyte0 selected by coordinates; s3, designing data coordinates required by data cross multiplication and addition; s4, a shufv instruction is used for obtaining data from the inb1 and the inb0 through the cvtcross1 and the cvtcross2; the generated result is stored in the cin0 and the cin1; s5, the 8-bit continuous data stored in the cin0 and the cin1 are converted into 16-bit data through a shufv instruction according to the data in the register; s6, the first 24 pieces of data in the cin0 and the cin1 are converted into 16 bits through the cvtshot1 and the cvtshot2 by using a shufv instruction, and the first 24 pieces of data in the cin0 and the cin1 are converted into 16 bits through the cvtshot2 and the cvtshot1; the generated result is stored in a cin1 register, a cin0 register and a cin2 register, and the stored data is 16 bits; s7, a dotpuw instruction is used for calculating multiplication and addition; the calculated result is stored in a cin0 register, a cin1 register and a cin2 register, and four pieces of 32-bit data are stored in each register; and S8, storing the data in the results cin0, cin1 and cin2 in a specified address. The calculation speed is improved.

The application provides an optimization method of a low-bit arbitrary-size independent convolution simd, comprising the following steps: S1, processing of convolution kernel data, the data storage mode adopts a convolution calculation mode, which can greatly reduce the loading time, and the data needs to be converted; converting the data; S2, design of convolution calculation and accumulation: since the accumulation sum cannot exceed 16 bits after multiplication and adjacent addition, the data must be processed; first, using the 16-bit accumulation sum to calculate, calculating 14 times each time, since the instruction is multiplied first and then adjacent addition in the calculation, the actual instruction accumulation number is 7 times; then, converting the data in the register into 32 bits and accumulating into a 32-bit register. The application can realize a speed increase of several times, and can increase by about 35 times relative to a C program. The 16-bit accumulation can be used, and the speed can be improved.

A method for transmitting data over a serial bus includes transmitting two bits of data over a first wire of a serial bus in each cycle of a plurality of cycles of a transmitter clock signal, transmitting a synchronization pattern over a second wire of the serial bus in a first cycle in the plurality of cycles of the transmitter clock signal, and transmitting two bits of data over the second wire of the serial bus in each cycle of the plurality of cycles of the transmitter clock signal except for the first cycle in the plurality of cycles of the transmitter clock signal. In one example, 16 bits of data and 2 parity bits are transmitted in five cycles of the plurality of cycles of the transmitter clock signal.

The present invention belongs to the field of wireless communication technology, and specifically is a TB‑Net hardware acceleration implementation method for DoA estimation. The method of the present invention comprises the following steps: designing the architecture design of the TB‑Net accelerator for DoA estimation; designing the data flow, and writing a script that can reorder the weights and biases of TB‑Net; designing a custom simple instruction set, and writing TB‑Net into an instruction program; quantizing the weights and bias data of TB‑Net into 16-bits signed integer data; performing circuit function verification, and comparing software and hardware results. The circuit structure includes: an instruction decoding module, an instruction storage module, a global data cache module, a data transmission network, a PE array, and a global control module. The present invention uses fixed weights and pulse arrays to increase the number of data reuses, significantly reduce the amount of data transmission, and can adapt to one-dimensional convolutions of various sizes, so as to realize a low-power and high-speed hardware accelerator for DoA using TB‑Net.

Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit to process as many elements of the second source vector as fit into an SIMD lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the SIMD lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.

The utility model relates to the technical field of data acquisition, in particular to a universal data acquisition preprocessing simulation control daughter card. Comprising a master control module, a power conversion unit, a clock unit and an interface unit. The system is used for controlling various ADC acquisition chips, the ZYNQ chip is adopted to realize the connection of the SPI, the LVTTL discrete line, the 16-bit parallel port, the LVDS interface and the JESD204B interface with the ADC chip of an external acquisition system, a main data acquisition system is assisted to carry out signal preprocessing and execute preliminary data processing or analysis, the function of the main acquisition system is enhanced, and the data acquisition efficiency is improved. And more accurate signal conditioning and faster data processing capability are provided.