21 results about "16-bit" patented technology

The invention provides a large language model quantification method, related equipment and a computer program product, and the method comprises the steps: carrying out the reasoning of a to-be-quantized large language model through calibration data, obtaining the activation of the large language model, and carrying out the statistics of the activation distribution of a target layer according to channels; calculating a smoothing factor of each channel according to the activation distribution; compensating the weight of the target layer channel by channel according to the smoothing factor to obtain a compensated weight; performing 4-bit quantization on the compensated weight; in the model reasoning process, activation of a target layer is smoothed, and 16-bit quantization is carried out on the smoothed activation. According to the method, a W4A16 quantification scheme is adopted, compared with W8A8, the weight storage amount is compressed by half, meanwhile, the precision loss is controlled to be smaller than 3%, and deployment of a large language model on edge equipment is facilitated.

The invention provides a block storage method and device for a sparse matrix, and is applied to the field of data storage.The method comprises the steps that block storage is conducted on the sparse matrix through a target sparse storage format, the target sparse storage format comprises a first-layer storage structure, a second-layer storage structure and a third-layer storage structure, comprising the following steps: in a first-layer storage structure, dividing a sparse matrix into blocks with the row and column number of 16 * 16; in the second-layer storage structure, the blocks are divided into sub-blocks with the row and column number being 4 * 4, the positions of non-zero sub-blocks in the sub-blocks are marked based on a 16-bit first-level bitmap, and the non-zero sub-blocks are stored; in the third-layer storage structure, marking the positions of the non-zero elements in the non-zero sub-blocks based on a 16-bit secondary bitmap, and positioning the non-zero element values of the non-zero elements through a secondary value pointer; according to the invention, the storage compatibility among different sparse cores can be realized.

A method for performing segment routing in a data communications network is disclosed. A routing node (106) along path between sender node (102) and receiver node (104) receives data packet with destination address (302). The destination address includes a first group of bits (306) with fixed amount of most significant bits, a second group of bits (308) specifying first segment, and a third group of bits (310) specifying second segment. The second and third groups have equal fixed amounts of bits and the distance in the destination header between the second group of bits and the third group of bits is a multiple of 16 bits. The routing node (106) determines if the first and second groups match its address. If matched, the routing node (106) generates a modified destination address (304) by swapping the second and third groups of bits.

This invention provides an optimized method for grayscale image mean preprocessing. For grayscale images, 128 image data points are loaded each time. One register loads 16 8-bit data points, using eight variable registers: vrd0, vrd2, vrd4, vrd6, vrd8, vrd10, vrd12, and vrd14. The loaded register data is then converted to 16 bits, meaning 16 registers are used to store the data. These variable registers are reused, and eight more variable registers are added to generate vrd0, vrd1, ..., vrd12. 5. Use a register `sum_h0` to accumulate 16-bit data. When `sum_h0` accumulates 256 times, shift the data right by 8 bits (equivalent to dividing by 256). Then, use a new register `sum_h1` to accumulate the shifted `sum_h0`, while `sum_h0` is initialized to 0. Then, re-accumulate the newly loaded data. Use `sum_h1` to accumulate the shifted `sum_h0`. When `sum_h1` accumulates 256 times, save the result of `sum_h1` to an array. Finally, accumulate the data in the array again and calculate the average. This optimization improves speed by 40 times.

This invention provides a lookup table method for half-precision floating-point number FP16, including: S1, 1) NNA quantization input; 2) Int16 input: 16 bits output to Lbit, S=0 indicates a positive number, V=0 indicates no overflow; Int16 input, FP16 input: converted to FPi; lookup table value FPi; obtain offset(FPPi), scale_n(FPPi), scale_p(FPPi); add offset, according to the result: positive multiply by scale_p, negative multiply by scale_n; obtain: absolute value converted to integer, take the lower 16 bits and output to Lbit, overflow 16 bits V=1, otherwise V=0, output overflow to V, output sign bit to S; S2, obtain SVLbit 16-bit positive integer; S3, according to LU_Table, SAT_T0, IDX0_T, get: V=1: take the value SAT_T0 (S=1) or SAT_T1 (S=0), V=0: take the high 5 bits of Lbit as idx, S=1: if idx≥IDX0_T1 take the value SAT_T0, S=0: idx+=IDX0_T1, if idx>31 take the value SAT_T1, take the low 11 bits of Lbit as dx, use idx and dx to look up the table and calculate y; S4, lookup result y (FPin); true value output: convert to FP16; quantization output: get ofbit, convert to integer and saturate to ofbit unsigned number; S5, NNA quantization output or XOR RAM port.

The embodiment of the invention discloses a data processing method and a related device, which are applied to the technical field of mobile communication and are used for reducing the overhead of a communication device during communication. The method is applied to a first communication device, and comprises the following steps: acquiring first information to be sent; sending the first information and a first cyclic redundancy check (CRC) code corresponding to the first information to a second communication device, wherein the length of the first CRC code is less than or equal to 16 bits; wherein when the first information does not include the first control information and the length of the first information is less than a first threshold value, the length of the first CRC code is 0 bit, and the first control information is used for scheduling the second communication device.

The application discloses a 64-bit fixed-point trigonometric function operation method of an ARM processor, which comprises the following steps: firstly, defining a 64-bit fixed-point number and a data type conversion mechanism; defining a sin trigonometric function table based on a 32-bit fixed-point number and storing the table in the form of integer data; secondly, converting a floating-point number to be operated into a 64-bit fixed-point number, performing a modulus operation on the 64-bit fixed-point number and a 64-bit fixed-point number form of π / 2, obtaining a trigonometric function variable, representing the variable in the form of integer data, and then incrementally searching a table to obtain a sin value of the converted 32-bit fixed-point number in the sin trigonometric function table; using the 64-bit fixed-point number to represent and using linear interpolation to compensate the value of the lower 16 bits of the decimal point, so as to obtain a sin value corresponding to the 64-bit fixed-point number; and finally, according to the sin value, using a trigonometric function transformation formula to calculate the values of trigonometric functions cos and tan. The operation method can realize high-precision decimal trigonometric function operation with high operation speed in the ARM processor.

The invention relates to the technical field of data storage, and discloses a method for automatically identifying the Die capacity of a memory chip, which comprises the following steps of: reading a register MR8 through a mode of the memory chip and acquiring the capacity of a single Die; the number of Ranks and the number of Channel are identified through pins; the IO bit width of a single channel is judged, when the bit width is 16 bits, the number S = 1 is allocated according to the bit width, and the first theoretical Die total capacity is calculated according to the Rank number, the Channel number and the number S = 1; comparing the first theoretical Die total capacity with the standard capacity, if the first theoretical Die total capacity is consistent with the standard capacity, passing verification, and if not, triggering an error reporting mechanism. According to the method, two mainstream IO bit width specifications of the LPDDR5 memory are covered, and the problem that no standard verification process exists in an 8-bit Die parallel working scene is solved.

Disclosed in embodiments of the present application are a data processing method and a related apparatus, which are applied to the technical field of mobile communications, and are used for reducing the overhead of communication apparatuses during communication. The method is applied to a first communication apparatus. The method comprises: acquiring first information to be sent; and sending to a second communication apparatus the first information and a first cyclic redundancy check (CRC) code corresponding to the first information, the length of the first CRC code being less than or equal to 16 bits, wherein when the first information does not comprise first control information and the length of the first information is less than a first threshold, the length of the first CRC code is 0 bit, and the first control information is used for scheduling the second communication apparatus.

The invention provides a matmul transpose weight splitting method based on simd, in the method, weight splitting is formed by combining a series of 2bit transpose logics, an input column is transposed to an output row, the method is suitable for matmul calculation in any shape, and the method comprises the following steps: S1, reading data in a first row, namely data before transpose, from an input address by using an mx512lad (vr0, 0, input tradr, 0) instruction; s2, aggregating the 4 bit data together by using an mx512gt4bi instruction; s3, all the 2bits are aggregated together by using an mx512gt2bi instruction; s4, all the 16 bits are aggregated together by using an mx512th instruction; and S5, transposing the generated rows of data by using an mx512ilve instruction and an mx512ilvo instruction to obtain a weight splitting target output format. According to the method, additional input and output space development is reduced; a large number of la and sa instructions are reduced; and a large number of redundant instructions are removed.

The invention provides an optimization method for image interpolation scaling. The optimization method comprises the following steps: S1, extracting data from S by using a lu1q instruction; s2, using a shufv instruction to extract data from registers in0, in1, in2 and in3 through a register cvtbyte0 selected by coordinates; s3, designing data coordinates required by data cross multiplication and addition; s4, a shufv instruction is used for obtaining data from the inb1 and the inb0 through the cvtcross1 and the cvtcross2; the generated result is stored in the cin0 and the cin1; s5, the 8-bit continuous data stored in the cin0 and the cin1 are converted into 16-bit data through a shufv instruction according to the data in the register; s6, the first 24 pieces of data in the cin0 and the cin1 are converted into 16 bits through the cvtshot1 and the cvtshot2 by using a shufv instruction, and the first 24 pieces of data in the cin0 and the cin1 are converted into 16 bits through the cvtshot2 and the cvtshot1; the generated result is stored in a cin1 register, a cin0 register and a cin2 register, and the stored data is 16 bits; s7, a dotpuw instruction is used for calculating multiplication and addition; the calculated result is stored in a cin0 register, a cin1 register and a cin2 register, and four pieces of 32-bit data are stored in each register; and S8, storing the data in the results cin0, cin1 and cin2 in a specified address. The calculation speed is improved.

The application provides an optimization method of a low-bit arbitrary-size independent convolution simd, comprising the following steps: S1, processing of convolution kernel data, the data storage mode adopts a convolution calculation mode, which can greatly reduce the loading time, and the data needs to be converted; converting the data; S2, design of convolution calculation and accumulation: since the accumulation sum cannot exceed 16 bits after multiplication and adjacent addition, the data must be processed; first, using the 16-bit accumulation sum to calculate, calculating 14 times each time, since the instruction is multiplied first and then adjacent addition in the calculation, the actual instruction accumulation number is 7 times; then, converting the data in the register into 32 bits and accumulating into a 32-bit register. The application can realize a speed increase of several times, and can increase by about 35 times relative to a C program. The 16-bit accumulation can be used, and the speed can be improved.

A method for transmitting data over a serial bus includes transmitting two bits of data over a first wire of a serial bus in each cycle of a plurality of cycles of a transmitter clock signal, transmitting a synchronization pattern over a second wire of the serial bus in a first cycle in the plurality of cycles of the transmitter clock signal, and transmitting two bits of data over the second wire of the serial bus in each cycle of the plurality of cycles of the transmitter clock signal except for the first cycle in the plurality of cycles of the transmitter clock signal. In one example, 16 bits of data and 2 parity bits are transmitted in five cycles of the plurality of cycles of the transmitter clock signal.

The utility model relates to the technical field of data acquisition, in particular to a universal data acquisition preprocessing simulation control daughter card. Comprising a master control module, a power conversion unit, a clock unit and an interface unit. The system is used for controlling various ADC acquisition chips, the ZYNQ chip is adopted to realize the connection of the SPI, the LVTTL discrete line, the 16-bit parallel port, the LVDS interface and the JESD204B interface with the ADC chip of an external acquisition system, a main data acquisition system is assisted to carry out signal preprocessing and execute preliminary data processing or analysis, the function of the main acquisition system is enhanced, and the data acquisition efficiency is improved. And more accurate signal conditioning and faster data processing capability are provided.

The invention discloses a voice coding and decoding method, which comprises a receiving end and a transmitting end, and is characterized in that the transmitting end acquires voice data which is in a pulse code modulation (PCM) format, has a single channel, 16 bits and a sampling rate of 8kHz, and acquires 320 bytes per 20ms; compressing each 320 bytes of voice data into 5 bytes of compressed data; multiple groups of compressed data are assembled into data frames, every 18 groups of compressed data form one data frame, and protocol fields are added to the heads of the data frames; performing encryption and scrambling processing on the data frame; the processed data frame is sent to a satellite communication channel through a digital signal processor (DSP); a receiving end receives data frames from a satellite communication channel, and one frame is received every 60ms; splicing the plurality of data frames into a complete voice data frame; performing descrambling and decryption processing on the voice data frame; decompressing the decrypted data into 320-byte voice data by taking every 5 bytes as a group; playing the decompressed voice data; according to the invention, the voice quality is greatly improved.

Embodiments of the application disclose a data transmission method and device, electronic equipment and medium. The method comprises: determining target communication data to be transmitted to a communication host; sending the target communication data to the communication host through at least two data transmission processes; the byte length of the target communication data transmitted for the first time is an odd number smaller than the byte length of the transmission data corresponding to the transmission period of the communication host, and the bit number of the shift register used for transmitting data in the communication slave is greater than or equal to 16 bits. The above scheme solves the problem that the byte delay is lost when transmitting data at a time, and the communication slave has no preparation time to transfer data to the shift register. Through at least two transmissions and the byte length of the target communication data transmitted for the first time being an odd number smaller than the byte length of the transmission data corresponding to the transmission period of the communication host, efficient transmission of large data is realized without the need for cyclic transmission of a large number of times or the need for reducing the clock rate.

The invention discloses a constant-temperature drying device for a glass slide, and belongs to the technical field of laboratory equipment. The device comprises a shell, a drying tray, a heat insulation plate, a heating film, an integrated controller and a double-temperature sensor. The drying tray is made of 6061 aluminum alloy and comprises five drying positions arranged in an array mode, and the center-to-center distance is 15 mm. The five polyimide flexible heating films are matched with the drying positions in a one-to-one mode, the power of each polyimide flexible heating film is 25 W, and 0-25 W stepless adjustment is achieved through PWM signals. The integrated controller is provided with an STM32H743 microcontroller and provided with a 16-bit ADC, and the sampling frequency is 20 Hz. The double PT1000 temperature sensors monitor in a distributed mode, the second sensor is embedded into the bottom of the center drying position to monitor the core temperature, and the first sensor is located on the edge to monitor the temperature difference. And by adopting an incremental PID algorithm, high-precision temperature control at + / -0.3 DEG C is realized, and the response time is less than or equal to 0.5 second. Compared with the prior art, the temperature control precision is improved by 85%, the energy consumption is reduced by 40%, five glass slides can be treated at the same time, and the pathological section manufacturing quality and efficiency are remarkably improved.

The present application relates to the technical field of data storage, and discloses a Die capacity automatic identification method of a memory chip, which comprises the following steps: reading a mode register MR8 of the memory chip and obtaining the capacity of a single Die; identifying the number of ranks and the number of channels through pin feet; judging the single-channel IO bit width, when the bit width is 16 bits, allocating the number of Dies S=1 according to the bit width, and calculating the first theoretical total capacity of Dies according to the number of ranks, the number of channels and the number of Dies S=1; comparing the first theoretical total capacity of Dies with the standard capacity, and if they are consistent, the verification is passed, otherwise, an error reporting mechanism is triggered. The present application covers two mainstream IO bit width specifications of LPDDR5 memory, and solves the problem of "no standard verification process" in the 8-bit Die parallel working scene.

The invention provides a nearest neighbor double image reduction optimization method based on simd, which is suitable for an nv12 image, the nv12 image is divided into a Y part and a UV part, S1, an mx512lao instruction is used to read 256bit data from row data of the Y part of an input image and store the 256bit data in a Y0 register, and 256bit data is read from row data of the UV part of the input image and store the 256bit data in a UV register; s2, taking one piece of data from every two points in the Y0 by using an mx512gtb instruction, storing the data together and storing the data into a Y1 register, taking two points from every four points in the UV0 by using mx512th, storing the two points together and storing the two points into a UV1 register; s3, 8 bits or 16 bits are moved to obtain a register Y1 and a register UV1, every four 8 bits represent a new element, and a new display register Y2 and a new display register UV2 are obtained; in every 64 bits, the first 32 bits are required data, and the last 32 bits are not required data; then, the mx512sao2w instruction is used for moving needed data to the front half section of the register, namely y0, y2, y4 and y6 are moved to the 0 bit, the 1 bit, the 2 bit and the 3 bit of the register and stored in an output address.

The application belongs to the field of channel coding, and particularly relates to a fast decoding algorithm of a polar code, namely MN (Major Node)-FSC algorithm; the method comprises the following steps: identifying special nodes of MN type which can be subjected to fast decoding at an encoding end, including but not limited to MN I, MN II, MN III and MN IV type nodes; after the identification is completed, corresponding fast decoding algorithms are used for decoding, and CRC checking is performed; if the CRC checking is passed, the decoding is considered to be successful, and if the CRC checking is failed, the decoding is considered to be unsuccessful. The minimum decoding unit of the traditional fast SC decoding is improved from 8 bits to 16 bits, that is, 16 bits can be decoded at least once, and the decoding tree can be greatly simplified. When 16 bits are taken as the minimum decoding unit, the four special nodes proposed in the application can decode more than 90% of the decoding nodes, and the remaining part can be decoded by using a traditional mode, so that the fast decoding scheme can effectively improve the decoding speed while ensuring the original block error rate.