119results about "Charge amplifiers" patented technology

The invention provides a front-end readout electronics circuit for a silicon PIN detector. The front-end readout electronics circuit solves the technical problems that an existing front-end readout circuit cannot meet the requirements for quick response, dynamic adjustment of the dynamic range and small nonlinearity error. The charge sensitive amplifier comprises a charge sensitive amplifier and a forming module connected with the charge sensitive amplifier, and the charge sensitive amplifier receives an analog charge signal of the silicon PIN detector and converts the analog charge signal into an analog voltage signal according to a certain gain; the gain is controlled by a feedback capacitor which is dynamically controlled by a register; the reset module is connected in parallel to two ends of the charge sensitive amplifier and is used for releasing the accumulated charge quantity of the charge sensitive amplifier; the forming module performs filtering forming on the analog voltage signal to obtain a Gaussian-like waveform; the forming module comprises a fast forming unit and a slow forming unit, and the fast forming unit is sequentially connected with a comparator and a digital-to-analog converter; the slow forming unit is sequentially connected with the sampling hold circuit, the digital control center module and the analog-to-digital converter. The method can be widely applied to the technical field of particle detection.

Low power event driven pixels and reset control circuits for the same are disclosed herein. In one embodiment, an event driven pixel comprises a photosensor; a photocurrent-to-voltage converter coupled to the photosensor; and a difference circuit coupled to the photocurrent-to-voltage converter. The difference circuit includes a source follower transistor and is configured to generate a signal at a gate of the source follower transistor that is based on a voltage output from the photocurrent-to-voltage converter. The difference circuit is further configured to output a difference signal in response to assertion of a row select signal. The event driven pixel can further include a reset control circuit coupled to the difference circuit and configured to initialize the difference circuit, and to reset the difference circuit when the difference signal output from the event driven pixel indicates a change in the voltage greater than a threshold amount.

The invention relates to the technical field of charge amplification, and discloses a charge amplification device and electronic equipment, and the charge amplification device comprises an input connection end which is used for connecting a signal source; an output connection; the input end of the integral amplification circuit is connected with the input connecting end, the output end of the integral amplification circuit is connected with the output connecting end, and the integral amplification circuit is used for carrying out integral processing on a current signal input by the signal source and outputting a voltage signal. A capacitance feedback loop of the integral amplification circuit is connected with a feedback capacitance network composed of a plurality of capacitors. The capacitance feedback loop of the integral amplification circuit in the charge amplification device adopts a feedback capacitance network as an equivalent feedback capacitor, the amplification gain of the charge amplification device is improved by more than two orders of magnitude, and the measurement sensitivity is greatly improved.

A readout circuit (110) is proposed. The readout circuit (110) is configured to convert an analog sensor charge (112) into a digital output count (114). The readout circuit (110) comprises at least one integrate and fire (IAF) circuit (116). The IAF circuit (116) is configured to convert the analog sensor charge (112) into a first digital output count (118). An analog voltage residue (120) after the last IAF cycle is further processed. The readout circuit (110) includes at least one analog-to-digital converter (ADC) (122). The ADC (122) is configured to convert the analog voltage residue (120) into a second digital output (124). Furthermore, the input charge to the readout circuit is a photodetector (182), and a method of readout of the analog sensor charge (112) is proposed.

The invention relates to an amplifier circuit (1) for broadband and low-noise amplification of a capacitive current source, preferably a thermoelectric sensor, comprising: a signal input (3) which can be connected to the capacitive current source in a node K1; the invention relates to an amplifier (1) for amplifying an input voltage, comprising an input stage (A1), which is connected to a node K1 at an input (7) of the input stage (A1) and has a node K2 at an output (9) of the input stage (A1), the input stage (A1) being designed to amplify the input voltage by at least three times, the input stage (A1) being designed to provide a high-ohm input resistance at the input of the input stage (A1), the input stage (A1) is designed to provide a stable and load-independent voltage at the output of the input stage (A1); the invention relates to a power amplifier comprising a first amplifier (A1) and a second amplifier (A3), an amplifier cascade (11) having at least a first amplifier and a second amplifier (A2, A3), each having an input (13, 17) and an output (15, 19), the output (15) of the first amplifier (A2) being connected in a node K3 to the input (17) of the second amplifier (A3), the input (13) of the first amplifier (A2) being connected to a node K2, the output (15, 19) being connected in a node K3 to the input (17) of the second amplifier (A3). An output (19) of the second amplifier (A3) is connected to a node K4, the amplifier cascade (11) being arranged to produce a high signal gain with a low phase shift over a wide frequency range; a feedback network (F1), which is connected to the input (7) of the input stage (A1) in a node K1 and to the output (19) of the second amplifier (A3) in a node K4, said feedback network (F1) being designed to provide a high-ohm feedback resistance with a parasitic capacitance of less than 0.5 pF, the feedback network (F1) is arranged to provide a negative feedback to a structure comprising the input stage (A1) and the amplifier cascade (11), and a signal output (21) connected to a node K5, which is connected to or corresponds to a node K4. The invention also relates to a sensor system.

A control device (100) for controlling a number N, with N ≥ 1, of actuators (200) for actuating N optical elements (310) of an optical system (300), comprising a control node (K2) coupling to the actuator (200) for providing a control voltage (V2) for the actuator (200), and an amplifier (110) configured to receive a supply voltage (V1) provided at an input node (K1) and to provide an output voltage (V3) at an output node (K3), wherein the amplifier (110) comprises a plurality M, with M ≥ 2, of current sources (111, 112) comprising at least one controlled current source (112) and a holding capacitor (113) for maintaining the level of the provided output voltage (V3), wherein the controlled current source (112) comprises a transistor (114), whose gate terminal can be controlled by an adjustable first control signal (S1),and has an adjustable resistor (115) coupled to the transistor (114).

To suppress leakage of electric charges from capacitances even when fluctuation in voltage at capacitance terminals is large at phase transitions of an operation.SOLUTION: A switched capacitor circuit is configured by a fully-differential operational amplifier circuit A1, input capacitances C1_P and C1_N, and switches S1_P, S1_N, S2_P, S2_N, S3_P, S3_N, S4_P, S4_N, S5_P, and S5_N. The switches S1_P, S5_P, and S3_P periodically switch a connection destination of an input side terminal of the input capacitance C1_P in an order of an input voltage VI_P, a voltage VCM2, and an input voltage VI_N. The switches S1_N, S5_N, and S3_N periodically switch a connection destination of an input side terminal of the input capacitance C1_N in an order of the input voltage VI_N, the voltage VCM2, and the input voltage VI_P, in synchronization with the switches S1_P, S5_P, and S3_P.SELECTED DRAWING: Figure 1

A readout circuit (110) is proposed. The readout circuit (110) is configured to convert an analog sensor charge (112) into a digital output count (114). The readout circuit (110) comprises at least one integrate and fire (IAF) circuit (116). The IAF circuit (116) is configured to convert the analog sensor charge (112) into a first digital output count (118). An analog voltage residue (120) after the last IAF cycle is further processed. The readout circuit (110) includes at least one analog-to-digital converter (ADC) (122). The ADC (122) is configured to convert the analog voltage residue (120) into a second digital output (124). Furthermore, the input charge to the readout circuit is a photodetector (182), and a method of readout of the analog sensor charge (112) is proposed.

Disclosed in the present invention is a floating inverter amplifier based on capacitor stacking, which boosts a power supply of the floating inverter amplifier to 2 times VDD by means of the capacitor stacking; under such condition, a transistor in the inverter may be better turned on, and a cascode structure can be applied to an inverting amplifier operating at a low power supply voltage. Furthermore, an ADC system employing the floating inverter amplifier of the present invention can process an input signal with a common-mode voltage of VDD and an amplitude up to 2 times VDD, which effectively addresses a problem of a reduced input signal amplitude under an ultra-low voltage, thereby increasing a signal-to-noise ratio of the system.

An amplifier (309), comprising: an op-amp (391) configured to receive at an input thereof a first electric current; a first MOS capacitor (393) connected to the input and an output of the op-amp (391).

A circuit (300) includes a plurality of first stage integrators (106 (1,1) - 106(2,1)). Each of the plurality of first stage integrators (106 (1, 1 ) - 106(2, 1 )) includes a first input (324 ), a. second input (326), a third input (322) and an output (328). The first input (324) of each of the plurality of first stage integrators is coupled to a. different one of circuit inputs (304), the second input (326) is coupled to a first reference input, the third input (322) is coupled to a second reference input and the output (328) of each of the plurality of first stage integrators is coupled to the first input (324) of such first stage integrator. The circuit (300) includes a second stage integrator ( 108(1)) which includes a first input (386) coupled to each of the first inputs of the plurality' of first stage integrators, a second input. (388) coupled to the first reference input, and an output (392) coupled to the first input (386) of the second stage integrator (108(1)).

To provide a switched capacitor type amplifier which does not need a reference voltage source.SOLUTION: A switched capacitor type amplifier comprises: an operational amplifier including two input and output terminals of a positive polarity and a negative polarity; a first capacitive element connected between a voltage input terminal and the input terminal of the negative polarity of the operational amplifier; a second capacitive element connected between the input terminal and the output terminal of the negative polarity of the operational amplifier; a switch element for accumulating electric charge corresponding to a voltage of the voltage input terminal in the first capacitive element in a first phase; and a switch element for moving the electric charge accumulated in the first capacitive element to the second capacitive element in the second phase. In the switched capacitor type amplifier, the operational amplifier includes a pair of differential input transistors and a pair of load elements connected in series with the pair of differential input transistors. The input terminal of the positive polarity is connected to a reference potential point, and the pair of load elements is set to be different resistance values.SELECTED DRAWING: Figure 1

The invention relates to a piezoelectric measuring device (100) comprising a sensor element (10) which generates a measurement signal (M) for a pressure to be measured, a conductor element (13) for deriving the measurement signal (M) to a data acquisition device (12), which data acquisition device (12) is configured to acquire and evaluate the derived measurement signal (M), wherein the sensor element (10) comprises an operational amplifier (20) which has an inverting input and an output, a feedback capacitor (22) which is arranged in parallel to the inverting input and output of the operational amplifier (20), and a reset switching element (27) arranged in parallel to the inverting input and output of the operational amplifier (20), wherein the data acquisition device (12) is further configured toto provide an electrical supply voltage (U) for the sensor element (10), wherein the data acquisition device (12) has a measurement cycle circuit (35) configured to switch on the electrical supply voltage (U) for the sensor element (10) before the start of a measurement cycle and to switch it off after completion of the measurement cycle; and that the sensor element (10) has a power-on reset logic (25, 26) configured to detect the presence of the electrical supply voltage (U) and, if the electrical supply voltage (U) is present before the start of a measurement cycle, closes and reopens the reset switching element (27).

To provide a piezo-electric measuring device.SOLUTION: A piezoelectric measuring device of the invention comprises a sensor element and a conductor element. The sensor element comprises an operational amplifier comprising an inverting input and an output. The sensor element comprises a feedback capacitor arranged in parallel with the inverting input and the output of the operational amplifier, and a reset switching element arranged in parallel with the inverting input and the output of the operational amplifier. A data acquisition device comprises a measurement cycle circuit configured to provide supply voltage to the sensor element, to switch on the supply voltage to the sensor element before starting of a measurement cycle, and to switch off the supply voltage after completion of the measurement cycle. The sensor element comprises a power-on reset logic designed to detect presence of the supply voltage and to close and reopen the reset switching element if the supply voltage is present before the starting of the measurement cycle.SELECTED DRAWING: Figure 1

To provide a switched capacitor amplifier and a battery monitoring device that uses a telescopic type fully differential amplifier to significantly reduce output errors caused by common mode noise and achieve a high CMRR.SOLUTION: A telescopic type fully differential amplifier 14b includes an input portion 20 including input a transistor M1-M2. A bias generating portion 21 generates a bias Vbn1. A cascode portion 22 is cascode-connected to the input portion 20 of the fully differential amplifier 14b and applies the bias Vbn1 to the cascode portion 22. The bias generating section 21 generates the bias Vbn1 so as to depend on the source potentials of the input transistor M1-M2.SELECTED DRAWING: Figure 2

The present invention discloses an anti-high-frequency large-signal two-wire charge amplification circuit and its implementation method, which includes a charge-to-voltage conversion circuit, a low-pass filter circuit, an AC amplification circuit, and a power supply processing circuit; the low-pass filter circuit is a sixth-order low-pass filter circuit, the output end of the charge-to-voltage conversion circuit is connected to the low-pass filter circuit, the low-pass filter circuit is connected to the AC amplification circuit, and the AC amplification circuit is connected to the power supply processing circuit. By adopting a constant current source two-wire power supply to reduce the wiring harness, the front-stage charge-to-voltage conversion circuit uses a circuit with a field-effect transistor as the core to convert and attenuate the signal, so as to reduce the requirements for the electrical performance indicators of the operational amplifier in the subsequent signal processing circuit, and adopts a signal link based on signal attenuation, low-pass filtering, signal amplification, and power supply processing to achieve the suppression of high-frequency large signals under the condition of ensuring the amplitude-frequency characteristics of the required working frequency band, and ensure that the signal is not clipped and distorted and deeply saturated.

Device for operating a passive infrared (PIR) detector with a first connection (IN) and a second connection (IP), the device comprising: - an electrical circuit arrangement (R G ), wherein the electrical circuit arrangement (R G ) forms a leakage resistance between the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR) to discharge the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR); wherein the electrical circuit arrangement (R G ) includes a switch-capacitor circuit with transfer gates and storage capacities; and the device is set up for this purpose: - the transfer gates of the electrical circuit arrangement (R G) to switch alternately with a first clock (φ1) and a second clock (Φ2), and to advance a charge quantity by one node with each half-clock using the storage capacities, whereby the first clock (φ1) and the second clock (Φ2) do not overlap and, apart from the non-overlap, the first clock (φ1) is the inverse of the second clock (Φ2); and - to switch off the first clock (φ1) and the second clock (Φ2) during a measurement phase, so that the device is in a measurement state and the charge flow through the electrical circuit arrangement (R G ) is prevented.

A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal being asserted, to couple amplifier input nodes to the bias voltage node and to short-circuit amplifier output nodes. First and second feedback branches each include a respective circuit network including parallel capacitors, with first ones of the capacitors directly connected to the amplifier input nodes. The first and second feedback branches further include a second set of switches intermediate the amplifier input nodes and second ones of the capacitors, and a third set of switches intermediate amplifier output nodes and the capacitors. These switches selectively couple the capacitors to the amplifier input and output nodes, based on a second reset signal being asserted. The second reset signal is asserted for a time interval exceeding a time interval in which the first reset signal is asserted.

Provided is a weak-signal reading circuit for a sensor, comprising a sensing signal input amplifying unit and a signal reading unit. The sensing signal input amplifying unit comprises a first transistor, wherein a gate and a drain of the first transistor are connected with a sensor; the signal reading unit is connected to a source of the first transistor, the first transistor is turned on when the sensor generates a sensing signal, so that the sensing signal is captured by the signal reading unit. When the sensor senses a signal and generates a voltage, the first transistor tends to be switched on, then the signal reading unit reads the sensing signal through the first transistor which has been turned on, that is, by providing the first transistor, the weak-signal reading circuit for sensor can be self-driven according to the voltage generated by the sensor without an extra drive circuit, thereby achieving low power consumption.

A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal being asserted, to couple amplifier input nodes to the bias voltage node and to short-circuit amplifier output nodes. First and second feedback branches each include a respective circuit network including parallel capacitors, with first ones of the capacitors directly connected to the amplifier input nodes. The first and second feedback branches further include a second set of switches intermediate the amplifier input nodes and second ones of the capacitors, and a third set of switches intermediate amplifier output nodes and the capacitors. These switches selectively couple the capacitors to the amplifier input and output nodes, based on a second reset signal being asserted. The second reset signal is asserted for a time interval exceeding a time interval in which the first reset signal is asserted.

Device for operating a passive infrared detector (PIR) - wherein at least one of the terminals of the passive infrared detector (PIR) is connected by an electrical circuit arrangement (R G ) is discharged and - wherein the electrical circuit arrangement (R G ) comprises a switched capacitor circuit and - where the switched capacitor circuit comprises two strands and - where each strand comprises several transfer gates and - where each string comprises several storage capacities and - where the transfer gates are switched alternately with one of two non-overlapping clocks (ϕ1,ϕ2) and - where, apart from the non-overlapping, one measure is the inverse of the other measure and - whereby the storage capacities are designed to transport a certain amount of charge with each half cycle by one node and - wherein the respective strands are designed to be operated in a half-cycle staggered manner to cause a continuous charge discharge and - where the discharge rate depends on the input voltage.

The utility model provides a built-in IEPE circuit used for a piezoelectric type shock wave pressure sensor, comprising a high gain amplifier, a feedback capacitor and a constant current source, the high gain amplifier is composed of an N channel enhanced field effect transistor, a P channel enhanced field effect transistor, a resistor R1, a resistor R2, a feedback resistor R3 and a resistor R4, the two ends of the high-gain amplifier are connected with the constant current source, the positive electrode of the constant current source is an output end, and the constant current source is connected to the P-channel enhanced field effect transistor; the piezoelectric sensor sensitive element is connected with the input end and receives a charge signal generated by the piezoelectric sensor sensitive element through the input end; the feedback capacitor is installed between the input end and the output end to form negative feedback to form a charge amplifying circuit, a small number of electronic components are used for constructing a complete IEPE circuit, and the charge amplifying circuit has the advantages of being high in integration level, small in size and high in anti-interference capacity and can be integrated in a sensor to amplify charge signals.

The present invention increases the output voltage of a switching amplifier in a situation where the power supply voltage is limited. The switching amplifier includes first and second switches that are turned on and off in a complementary manner, and a capacitance, both ends of which serve as inputs to a power combiner. Both ends of the capacitance are connected to output ends of the first and second switches. The capacitance is supplied with power along with the operation of the first and second switches. As a result, an electric charge in the capacitance is used as a charge pump, and is used alternatingly for boosting or stepping down the output voltage depending on the operation frequency of the switching amplifier, thereby generating a rectangular voltage with a controlled wave height.

To provide a display driver that can reduce the adverse effect of noise at the latch timing of display data on an initialization operation of an amplifier circuit.SOLUTION: A display driver 10 includes: a line latch circuit; a first D / A conversion circuit; a second D / A conversion circuit; a first amplifier circuit 41 in which the electric charge of a capacitor of a first switched capacitor circuit SC1 is initialized in a first initialization period, and outputs data voltage in a first output period; a second amplifier circuit 42 in which the electric charge of a capacitor of a second switched capacitor circuit SC2 is initialized in a second initialization period, and outputs data voltage in a second output period; and a control circuit 50. The control circuit 50 ends the second initialization period of the second amplifier circuit before display data is latched by the line latch circuit 20 at the latch timing and output of the first amplifier circuit 41 changes.SELECTED DRAWING: Figure 1

The utility model belongs to the technical field of measurement, and relates to a double-shaft anti-seismic signal processing circuit of a vortex shedding flowmeter, which is characterized in that the output ends of a main probe and a Y-axis auxiliary probe of the circuit are respectively connected with the input end of a differential amplification circuit 1 through a charge amplification circuit 1 and a charge amplification circuit 2; the output end of the X-axis auxiliary probe is connected with the input end of the differential amplification circuit 2 through the charge amplification circuit 3, the output end of the differential amplification circuit 1 is connected with the input end of the differential amplification circuit 2, and the output end of the differential amplification circuit 2 and the output end of the CPU are connected with the input end of the shaping circuit and the input end of the AD conversion circuit through the adjustable gain amplification circuit. The output ends of the AD conversion circuit and the shaping circuit are connected with the input end of the CPU; vibration signals in two axial directions are obtained through the Y-direction auxiliary probe and the X-direction auxiliary probe, the anti-vibration effect is achieved through differential operation with signals of the main probe, and the measurement lower limit of the vortex shedding flowmeter is reduced.

Provided is a weak-signal reading circuit for a sensor, comprising a sensing signal input amplifying unit and a signal reading unit. The sensing signal input amplifying unit comprises a first transistor, wherein a gate and a drain of the first transistor are connected with a sensor; the signal reading unit is connected to a source of the first transistor, the first transistor is turned on when the sensor generates a sensing signal, so that the sensing signal is captured by the signal reading unit. When the sensor senses a signal and generates a voltage, the first transistor tends to be switched on, then the signal reading unit reads the sensing signal through the first transistor which has been turned on, that is, by providing the first transistor, the weak-signal reading circuit for sensor can be self-driven according to the voltage generated by the sensor without an extra drive circuit, thereby achieving low power consumption.

The present invention discloses a circuit device for eliminating baseline drift, comprising: a pre-stage processing circuit, a differential amplifier circuit, a low-pass filter, a nonlinear limiting stage circuit and an integral feedback circuit; wherein the pre-stage processing circuit converts and amplifies an input current pulse signal to obtain a voltage signal, and the voltage signal and a feedback signal output by the integral feedback circuit are simultaneously input into the differential amplifier circuit, and an output signal is obtained after passing through the differential amplifier circuit and the low-pass filter; in addition, an integral feedback circuit is added to the entire circuit to form a high-pass filter, thereby eliminating DC offset in the circuit, and on the basis of introducing the integral feedback, a nonlinear limiting stage circuit is added to the entire circuit, thereby eliminating baseline drift caused by AC coupling.

The invention relates to offset voltage cancellation for charge amplification circuits. A circuit includes an amplifier, a bias node, and a first set of switches configured to couple an amplifier input node to the bias node and a short-circuited amplifier output node based on an asserted first reset signal. Each of the first and second feedback branches includes a respective circuit network including a shunt capacitor, the first capacitor being directly connected to the amplifier input node. The first and second feedback branches further include a second set of switches intermediate the amplifier input node and the second capacitor, and a third set of switches intermediate the amplifier output node and the capacitor. The switches selectively couple the capacitors to the amplifier input and output nodes based on the asserted second reset signal. The time interval in which the second reset signal is asserted exceeds the time interval in which the first reset signal is asserted.

The utility model belongs to the technical field of charge signal processing, and particularly relates to a multiple-adjustable charge amplifier circuit, which comprises a low-pass filter circuit, an integral negative feedback amplification circuit, a high-pass filter circuit, a voltage amplification circuit and a double-T-shaped wave trap circuit, wherein the low-pass filter circuit is used for filtering a high-frequency signal of a charge signal; the integral negative feedback amplification circuit is used for converting the charge signal into a charge voltage signal; the high-pass filter circuit is used for filtering low-frequency signals; the voltage amplifying circuit is used for amplifying the charge voltage signal; the double-T-shaped wave trap circuit is used for filtering power frequency interference. The charge amplifier solves the problems that the amplification factor of the charge amplifier is adjustable, the impedance of the charge amplifier is large, and the charge amplifier is easily interfered by power frequency radiation or other noises.

Amplifier circuit (1) for broadband and low-noise amplification of a capacitive current source, comprising a signal input (3) which can be connected to the capacitive current source in a node K1, an input stage (A1), wherein the input stage (A1) is connected to the node K1 at an input (7) of the input stage (A1) and has a node K2 at the output (9) of the input stage (A1), wherein the input stage (A1) is arranged to amplify an input voltage at least 3 times, wherein the input stage (A1) is arranged to provide a high-impedance input resistor at the input of the input stage (A1), wherein the input stage (A1) is arranged to provide a stable and load-independent voltage at the output of the input stage (A1), an amplifier cascade, wherein the amplifier cascade (11) has at least a first and a second amplifier (A2, A3), each with an input (13, 17) and an output (15, 19), wherein the output (15) of the first amplifier (A2) is connected in a node K3 to the input (17) of the second amplifier (A3), wherein the input (13) of the first amplifier (A2) is connected to the node K2, wherein the output (19) of the second amplifier (A3) is connected to a node K4, wherein the amplifier cascade (11) is arranged to generate a high signal amplification with low phase shift over a wide frequency range, a feedback network (F1), wherein the feedback network (F1) is connected to the input (7) of the input stage (A1) in node K1 and the output (19) of the second amplifier (A3) in node K4, wherein the feedback network (F1) is arranged to provide a high-ohmic feedback resistor with a parasitic capacitance of less than 0.5 pF, wherein the feedback network (F1) is arranged to provide a negative feedback to a structure comprising the input stage (A1) and the amplifier cascade (11), and a signal output (21) connected to a node K5, wherein the node K5 is connected to the node K4 or corresponds to the node K4, wherein the input stage (A1) comprises a junction field effect transistor (Q1) and a bipolar transistor (Q2), wherein a drain terminal of the junction field effect transistor (Q1) is connected to a base terminal of the bipolar transistor, wherein the junction field effect transistor (Q1) is connected as a source circuit, wherein the bipolar transistor (Q2) is connected as an emitter follower, wherein the first and second amplifiers (A2, A3) of the amplifier cascade (11) are operational amplifiers (Q3, Q4), wherein the first operational amplifier (Q3) has a voltage gain of more than 10 4 has, wherein the second operational amplifier (Q4) has a voltage gain of maximum 10 3 has, wherein the feedback network (F1) has a high-ohm feedback resistor with a parallel capacitance, wherein the feedback network (F1) comprises a series-connected low-pass filter.