17results about "Time-varying network" patented technology

A fully differential switched capacitor amplifier receives a differential analog signal from a differential input terminal, amplifies the differential analog signal, and outputs an amplified signal from a differential output terminal. The fully differential switched capacitor amplifier includes: a sampling capacitor that respectively samples the differential analog signal input from the differential input terminal; a differential input switch connected to a path for inputting the differential analog signal between the differential input terminal and the sampling capacitor; a fully differential amplifier that amplifies the differential analog signal input to the sampling capacitor; and a differential input resistor connected between the differential input switch and the sampling capacitor.

To suppress leakage of electric charges from capacitances even when fluctuation in voltage at capacitance terminals is large at phase transitions of an operation.SOLUTION: A switched capacitor circuit is configured by a fully-differential operational amplifier circuit A1, input capacitances C1_P and C1_N, and switches S1_P, S1_N, S2_P, S2_N, S3_P, S3_N, S4_P, S4_N, S5_P, and S5_N. The switches S1_P, S5_P, and S3_P periodically switch a connection destination of an input side terminal of the input capacitance C1_P in an order of an input voltage VI_P, a voltage VCM2, and an input voltage VI_N. The switches S1_N, S5_N, and S3_N periodically switch a connection destination of an input side terminal of the input capacitance C1_N in an order of the input voltage VI_N, the voltage VCM2, and the input voltage VI_P, in synchronization with the switches S1_P, S5_P, and S3_P.SELECTED DRAWING: Figure 1

To provide an integration circuit having less power consumption.SOLUTION: A feedback rate correction capacitor CR is provided between two input terminals of a difference type amplification circuit 15, and is connected at the time of a sampling and hold mode. By controlling a separation at the time of an integration mode, a feedback rate in the sample and holding mode and the integration mode can be set to an almost same level, and an unnecessary power consumption does not flow in the integration mode because a phase margin in the integration mode is not required to be increased.SELECTED DRAWING: Figure 1

The band-pass filter (1) comprises an input terminal (2A) to which a high-frequency signal is input, an output terminal (2B) from which an output signal is output, a plurality of switches (10-21) connected in a tournament configuration between the input terminal (2A) and the output terminal (2B) and controlled by a clock signal, differential switches (4-9) each consisting of two switches, and capacitances (22-25) having one end connected to a connection point between the differential switches and the other end grounded.

Analysis channelizers are provided. In one embodiment, the channelizer includes an M-path filter receiving an input signal; a circular buffer in communication with the M-path filter; and an M-point inverse fast Fourier transform (IFFT) circuit in communication with the circular buffer, such that the channelizer aligns spectra of the input signal with spectral responses an odd length, non-maximally decimated filter bank by alternating sign heterodyne of the input signal. The channelizer applies an equivalency theorem to the non-maximally decimated filter bank formed by an odd length polyphaser filter. Advantageously, the M-path filter does not require on-line signal processing to obtain odd-indexed filter centers. In another embodiment, the channelizer alternates a sign heterodyne of a filter coefficient weight.

The utility model provides a switch filter bank. The switch filter bank comprises a first switch, a first filter bank, a second switch, a third switch, a second filter bank and a fourth switch which are connected in sequence, the first filter bank comprises a first filter, a second filter, a third filter, a fourth filter and a fifth filter which are connected in parallel; the second filter bank comprises a sixth filter, a seventh filter, an eighth filter, a ninth filter and a tenth filter which are connected in parallel. The first switch, the second switch, the third switch and the fourth switch are all single-pole five-throw switches. According to the utility model, accurate frequency point output is obtained by cascading the two groups of filters and switching the switches, the requirements of distribution of the frequency points and segmentation of the filters are met, and only the switches of one switch filter group need to be switched when adjacent frequency points are output in the scheme. Meanwhile, the switching filter bank is designed by utilizing the scheme, and the use passband of the filter bank can be changed by changing the frequency band of one of the filter banks.

According to a band-pass filter, n represents a natural number equal to or more than one, and the band-pass filter includes: an input terminal (1) to receive an input of an RF signal; a multi-phase splitter (3) to split the RF signal input to the input terminal into n RF signals whose phases each differ by 360 degrees / n; n signal paths (17 to 20) to receive from the multi-phase splitter, sample, and hold one of the n RF signals whose phases each differ by the 360 degrees / n, and output the held signal, the n signal paths being connected to the multi-phase splitter, and each signal path including a sample hold element including two switches; a multi-phase synthesizer (4) to synthesize n signals output from the n signal paths, the multi-phase synthesizer (4) being connected to the n signal paths; an output terminal (2) to output the signals to be synthesized by the multi-phase synthesizer; and a clock signal source (21) to output a clock signal (S1) for driving all of switches.

According to a band-pass filter, n represents a natural number equal to or more than one, and the band-pass filter includes: an input terminal to receive an input of an RF signal; a multi-phase splitter to split the RF signal into n RF signals whose phases each differ by 360 degrees / n; n signal paths to receive from the multi-phase splitter, sample, and hold one of the n RF signals, and output the held signal, the n signal paths being connected to the multi-phase splitter, and each signal path including a sample hold element including two switches; a multi-phase synthesizer to synthesize n signals output from the n signal paths, the multi-phase synthesizer being connected to the n signal paths; an output terminal to output the signals to be synthesized by the multi-phase synthesizer; and a clock signal source to output a clock signal for driving all of switches.

Embodiments may comprise low noise amplifier (LNA) circuitry with a tunable wideband and high linearity. Embodiments may increase the linearity of the LNA circuitry and reduce noise. The LNA circuitry may comprise an inverter having a differential input coupled with the antenna, a first cascode circuitry coupled between a differential output of the inverter and a second cascode stage circuitry, wherein the second cascode stage circuitry comprises a first N-path filter circuitry coupled with a first set of outputs of clock circuitry having a clock frequency of an incoming signal minus a delta frequency and a second N-path filter circuitry coupled with a second set of outputs of clock circuitry having a clock frequency of an incoming signal plus a delta frequency. Combining the response of the two N-path filter circuitries at plus and minus delta frequency may achieve frequency selectivity and attenuate blockers.

To provide a signal processing device and a signal processing method capable of separating a periodic signal (quasi-periodic signal) and an aperiodic signal (quasi-aperiodic signal) which have fluctuations in amplitude from estimated values and corrected values of a Kalman filter.SOLUTION: A signal processing device 1 includes a Kalman filter 11 that outputs an estimated value and an updated value of a system 20, and a signal separation filter 12 for separating at least any one of a quasi-periodic signal and a quasi-aperiodic signal from an input signal including the quasi-periodic signal and the quasi-aperiodic signal, the amplitude of the quasi-periodic signal in a separation target period which is a target period of a separation target signal fluctuating at a frequency lower than a predetermined separation frequency, and the amplitude of the quasi-aperiodic signal in the separation target period fluctuating at a frequency higher than the separation frequency. Further, the signal separation filter 12 has a feedforward path including a dead time element with the separation target period on a shoulder thereof, receives the estimated value and the updated value as input signals, and separates at least one of the quasi-periodic signal and the quasi-aperiodic signal for each input signal.SELECTED DRAWING: Figure 1

A filter circuit includes: a filter unit which is connected to a signal line and which has transistors and capacitors which constitute paths for N phases, and in which the transistors to which clock signals of N phases are applied electrically connect the capacitors to the signal line; and a dummy unit which has transistors and impedance parts which constitute dummy paths corresponding, respectively, to the paths for the N phases, and in which the transistors to which inverted signals of N phases are applied electrically connect the impedance parts to the signal line.

Impedance matching network (104, 204, 400, 500), comprising: a first signal terminal (212, 302, 402, 502) configured to receive a signal from a source circuit (102, 202); a second signal terminal (214, 304, 404, 504) configured to provide the signal to a load circuit (106, 206); a series branch comprising a variable capacitive component (208, 300, 350, 401, 501) between the first signal terminal (212, 302, 402, 502) and the second signal terminal (214, 304, 404, 504), wherein the variable capacitive component (208, 300, 350, 401, 501) comprises a plurality of series-connected capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508), wherein at least one of the capacitive sections comprises a switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) comprising a stack of series-connected transistors (352a...352N), and a control component (210, 426, 526) configured to control a capacitance of the variable capacitive component (208, 300, 350, 401, 501) by controlling at least one of the capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) based on a predetermined algorithm, wherein the at least one of the capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching element (316, 318, 320, 416, 418, 420, 516, 518, 520) comprises a first capacitive section comprising a first switching element comprising a stack of series-connected transistors, and a second capacitive section comprising a second switching element comprising a stack of series-connected transistors, wherein the control component (210, 426, 526) is configured to switch the capacitive sections (306, 308, 310, 312, 314, 406, 408, 410, 412, 414, 506, 508) comprising the switching elements (316, 318, 320, 416, 418, 420, 516, 518, 520) on or off in series in steps of one in a predetermined direction according to the predetermined algorithm in order to avoid voltage overload.

A bandpass filter (1) includes: an input terminal (2A) to receive an input of a high frequency signal; an output terminal (2B) to output an output signal; differential switches (4 to 9) provided between the input terminal (2A) and the output terminal (2B), connected in a tournament pattern with a plurality of switches (10 to 21) controlled according to a clock signal, and each including two switches; and capacitances (22 to 25) each including one end connected to a connection point between the switches of the differential switches, and another end grounded.