3results about "Time-varying network" patented technology

According to a band-pass filter, n represents a natural number equal to or more than one, and the band-pass filter includes: an input terminal (1) to receive an input of an RF signal; a multi-phase splitter (3) to split the RF signal input to the input terminal into n RF signals whose phases each differ by 360 degrees / n; n signal paths (17 to 20) to receive from the multi-phase splitter, sample, and hold one of the n RF signals whose phases each differ by the 360 degrees / n, and output the held signal, the n signal paths being connected to the multi-phase splitter, and each signal path including a sample hold element including two switches; a multi-phase synthesizer (4) to synthesize n signals output from the n signal paths, the multi-phase synthesizer (4) being connected to the n signal paths; an output terminal (2) to output the signals to be synthesized by the multi-phase synthesizer; and a clock signal source (21) to output a clock signal (S1) for driving all of switches.

According to a band-pass filter, n represents a natural number equal to or more than one, and the band-pass filter includes: an input terminal to receive an input of an RF signal; a multi-phase splitter to split the RF signal into n RF signals whose phases each differ by 360 degrees / n; n signal paths to receive from the multi-phase splitter, sample, and hold one of the n RF signals, and output the held signal, the n signal paths being connected to the multi-phase splitter, and each signal path including a sample hold element including two switches; a multi-phase synthesizer to synthesize n signals output from the n signal paths, the multi-phase synthesizer being connected to the n signal paths; an output terminal to output the signals to be synthesized by the multi-phase synthesizer; and a clock signal source to output a clock signal for driving all of switches.

A bandpass filter (1) includes: an input terminal (2A) to receive an input of a high frequency signal; an output terminal (2B) to output an output signal; differential switches (4 to 9) provided between the input terminal (2A) and the output terminal (2B), connected in a tournament pattern with a plurality of switches (10 to 21) controlled according to a clock signal, and each including two switches; and capacitances (22 to 25) each including one end connected to a connection point between the switches of the differential switches, and another end grounded.