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8168 results about "Analog to digital conversion" patented technology

Compression of baseband signals in base transceiver systems

A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses baseband signal samples resulting from analog to digital conversion of a received analog signal followed by digital downconversion. The compressed signal samples are transferred over the serial data link to the baseband processor then decompressed prior to normal signal processing. For the downlink, the baseband processor compresses baseband signal samples and transfers the compressed signal samples to the RF unit. The RF unit decompresses the compressed samples prior to digital upconversion and digital to analog conversion to form an analog signal for transmission over an antenna. Compression and decompression can be incorporated into operations of conventional base stations and distributed antenna systems, including OBSAI or CPRI compliant systems.
Owner:INTEGRATED DEVICE TECH INC

Avalanche photodiode controller circuit for fiber optics transceiver

A controller for controlling the reverse-bias voltage of an avalanche photodiode in a transceiver or receiver. The controller includes memory for storing information related to the avalanche photodiode, and analog to digital conversion circuitry for receiving an analog signal corresponding to the temperature of the avalanche photodiode, converting the received analog signal into a digital value, and storing the digital value in a predefined location within the memory. Control circuitry in the controller controls the operation of the avalanche photodiode in accordance with the digital value corresponding to the temperature of the avalanche photodiode and a temperature lookup table stored in the memory. A serial interface is provided to enable a host device to read from and write to locations within the memory. The invention is also implemented as a method for controlling the reverse-bias voltage of an avalanche photodiode in a transceiver or receiver and a method for calibrating a transceiver or receiver having an avalanche photodiode.
Owner:II VI DELAWARE INC

Programmable visual chip-based visual image processing system

Disclosed in the invention is a programmable visual chip-based visual image processing system, comprising an image sensor and a multilevel parallel digital processing circuit. The image sensor mainly includes a pixel array, an analog preprocessing circuit array and an analog-to-digital conversion circuit array; and the digital processing circuit consists of a parallel processing unit array with an M*M pixel level, a parallel processing unit array with M*1 rows, an on-chip artificial neural network and a reduced instruction processor dual-core subsystem. According to the provided system, high quality image collection with high speed and multilevel parallel image processing are realized and several high-speed intelligent visual application can be realized by programming; and compared with a traditional image system, the provided system has advantages of high speed, high integration, low power consumption and low cost. Moreover, the invention brings forward an embodiment for realizing the above-mentioned system as well as several high-speed intelligent visual image processing algorithms based on the embodiment. High-speed motion detection, high-speed gesture identification and rapid face detection are included; and the processing speed can reach 1000 frames per second. Therefore, a requirement of high-speed real-time processing can be met.
Owner:INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI

Systems and Methods for Reduced Format Data Processing

Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier circuit, an analog to digital conversion circuit, a cosine component calculation circuit, a sine calculation circuit, and a zero gain start calculation circuit. The variable gain amplifier circuit is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The analog to digital conversion circuit is operable to convert the amplified output to a corresponding series of digital samples. The cosine component calculation circuit is operable to calculate a cosine component from the series of digital samples, and the sine component calculation circuit operable to calculate a sine component from the series of digital samples. The zero gain start calculation circuit is operable to calculate a raw gain error value based on the cosine component and the sine component, where the gain feedback value is derived from the raw gain error value.
Owner:BROADCOM INT PTE LTD

Time-interleaved analog-to-digital conversion apparatus

A time-interleaved analog-to-digital conversion apparatus is disclosed. The time-interleaved analog-to-digital conversion apparatus is applied for a television system and includes an input multiplexing module, a gain multiplexer and an analog-to-digital converter. The input multiplexing module receives a plurality of image signals, and samples the image signals according to a clock signal to generate a sample multiplexing signal. The gain multiplexer receives a plurality of gain signals and selectively transmits one of the gain signals corresponding to the sample multiplexing signal according to the clock signal, so as to generate a gain multiplexing signal. The analog-to-digital converter receives the sample multiplexing signal, the gain multiplexing signal and the clock signal. The analog-to-digital converter amplifies and converts the sample multiplexing signal to a digital signal according to the gain multiplexing signal and the clock signal.
Owner:NOVATEK MICROELECTRONICS CORP

Systems and Methods for Mitigating Latency in a Data Detector Feedback Loop

Various embodiments of the present invention provide systems and methods for mitigating latency in a data detector feedback loop. For example, a method for reducing latency in an error corrected data retrieval system is disclosed. The method includes performing an analog to digital conversion at a sampling instant to create a digital sample, and performing a data detection on the digital sample to create a detected output. The detected output is compared with the digital sample to determine a phase error. During an interim period, the digital sample is adjusted to reflect the phase error to create an adjusted digital sample. After the interim period, the sampling instant is adjusted to reflect the phase error.
Owner:LSI CORPORATION +1

Highly linear analog-to-digital conversion system and method thereof

A highly linear analog-to-digital (ADC) conversion system has an analog front-end device in cascade with a standard ADC converter, and a tunable digital non-linear equalizer. The equalizer corrects the quantization distortion, deviations from ideal response, and additive noises generated by the analog front-end device and ADC converter. The equalizer is formed by three main parts: Generate Function Streams Unit, Finite Impulse Response FIR filters and a summer. The equalizer receives the unequalized output from the ADC converter and generates a plurality of monomial streams in a systolic fashion. Each of the monomial streams is passed through a corresponding linear finite impulse response FIR filter. A convolution sum of all outputs from the FIR filters produces a unique equalized output with the non-linear distortion reduced to a satisfactory level. The FIR filter coefficients are determined by an Identity Equalizer Coefficient Unit, and a Test Signal Generator with different types of test signals. The FIR filter coefficients are set to minimize an error function.
Owner:MASSACHUSETTS INST OF TECH
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