665 results about "Analog to information converter" patented technology

A power supply provides digital data coupling for power-line networking. The power supply includes a power supply side digital interface to transmit and receive a digital data passed through a digital coupler to and from a power-line network access circuitry side digital interface of power-line network access circuitry. The power supply further includes a digital-to-analog converter to process digital data into a high-frequency analog data carrier to provide to a power line of a power-line network. An analog-to-digital converter of the power supply converts a high-frequency analog data carrier from the power line into digital data for the power-line network access circuitry. A power-line analog front end of the power supply transmits and receives the high-frequency analog data carrier to and from the power line. Digital data exchanged between the power supply and the network access circuitry may include control signals for a control circuitry of the power supply. Control circuitry of the power supply may handle control of the digital-to-analog converter, the analog-to-digital converter and the analog front end.

Methods and systems for processing a single sub-channel that includes two or more combined channels. Using intermediate frequency sub-sampling, two or more channels from a broad band signal are combined into a single sub-channel for further analog and digital processing. Each of the two or more channels is down converted to an intermediate frequency, filtered to remove certain undesired channels, and combined such that the two or more channels are adjacent to each other. A digital representation of the sub-channel is produced from the combined intermediate frequency channels. Each channel within the digital representation is down converted to baseband, and the in-phase and quadrature components are separated from each other. Compared to one direct down conversion technique, intermediate frequency sub-sampling as described in the application may reduce the number of analog to digital converters and control amplifiers used in analog processing by a factor of four.

Systems and methods are described for a GPS receiver capable of functioning in the presence of interference. A method includes detecting an interfering signal including: tuning a band pass filter over a frequency range; and at each of a plurality of incremental frequencies: computing a set of band pass filter coefficients; sending the set of band pass filter coefficients to a digital filter; repeatedly transforming an analog-to-digital converter output having a quantization level in excess of 2 bits into a band pass filter output with the digital filter to obtain a plurality of samples; computing an average of the plurality of samples; and comparing the average to a threshold to detect peaks that exceed a threshold. An apparatus, comprising: an analog radio frequency circuit; an analog-to-digital converter coupled to the analog radio frequency circuit, the analog-to-digital converter providing a quantization level in excess of 2 bits; a digital filter coupled to the analog-to-digital converter; and a digital circuit coupled to the digital filter.

The present invention provides an adaptive, intelligent transform based Analog to Information Converter (AIC) for wideband signals by directly converting an analog signal to information (e.g., features, decisions). This direct conversion is achieved by (i) capturing most of the information of a wideband signal via hardware/software implemented mathematical transformations, (ii) effectively removing unwanted signals such as jammer and interfere from the input signal, and (iii) using novel algorithms for highly accurate decision making and feature extraction (e.g., high probability of detection with low probability of false alarm). The jump in the improvement over today's state-of-the-art is in terms of effective and optimum signal information extraction at high-speed.

A pipelined analog-to-digital converter (ADC) (30) with improved precision is disclosed. The pipelined ADC (30) includes a sequence of stages (20), each of which includes a sample-and-hold circuit (22), an analog-to-digital converter (23), and the functions of a digital-to-analog converter (DAC) (25), an adder (24), and a gain stage (27) at which a residue signal (RES) is generated for application to the next stage (20) in the sequence. A multiplying DAC (28) performs the functions of the DAC (25), adder (24), and gain stage (27) in the stage (20), and is based on an operational amplifier (29). Sample capacitors (C10, C20) and reference capacitors (C12₂, C22₂) receive the analog input from the sample-and-hold circuit (22) in a sample phase; parallel capacitors (C12₁, C22₁) are provided to maintain constant circuit gain. Extended reference voltages (V_REFPX, V_REFNX) at levels that exceed the output range (V₀+, V₀−) of the operational amplifier (29) are applied to the reference capacitors, in response to the digital output of the analog-to-digital converter (23) in its stage (20). The reference capacitors (C12, C22) are scaled according to the extent to which the extended reference voltages (V_REFPX, V_REFNX) exceed the op amp output levels (V₀+, V₀−). The effects of noise on the reference voltages (V_REFPX, V_REFNX) on the residue signal (RES) are thus greatly reduced.

A multistage ADC that subranges and interpolates, and that amplifies selected subranges to convert an analog signal to a stream of digital values. The ADC samples the analog signal and provides a stream of sample signals. A first stage flash converts each sample signal into a first multiple bit value and subranges a reference ladder according to the first multiple bit value into selected reference signals. Each additional secondary stage amplifies a selected subrange of signals from a prior stage, flash converts the amplified residual signals to provide an additional multiple bit value, interpolates each set of amplified residual signals and subranges the interpolated signals according to the corresponding multiple bit value. A final stage amplifies and flash converts to determine a final multiple bit value. An error corrector combines each set of multiple bit values into a digital value.

A method and apparatus are disclosed for improving the operation of an analog-to-digital converter ("ADC"). A separate "clean" oscillator clock is to be used in combination with a "noisy" ADC clock being regulated by a phase-locked-loop (PLL) circuit. The "noisy" ADC clock drives the digital control logic and also turns on the sample signal for the purpose of sampling. The second clock, which has a substantially fixed (i.e., "clean") frequency is used to generate a short pulse, the leading edge of which turns off the sample signal, thereby providing an improved sampling process with greater resolution. The interaction of the two clocks is controlled with digital logic circuitry.

The invention provides a successive approximation analog-digital converter and an analog-digital conversion method based on digital domain self-correcting. The successive approximation analog-digital converter comprises a CDAC, a comparator, an SAR control logic circuit, a correction control logic circuit, a storage, an adder and a clock circuit; a differential structure is adopted in the CDAC; capacitor arrays of the CDAC respectively form a high-M-level CDAC and a low-L-level CDAC; on the basis of a capacitor array reusing thought, mismatching errors of various capacitors in the high-M-level CDAC capacitor array are detected by reusing the low-L-level CDAC in a self-correcting stage; detected error values are quantized; error voltage is converted into an error code to output; the output error code is output into the storage; after mismatching error detection and quantization are completed, digital conversion of an input analog signal begins to perform; an original code is output, and operated with the error code at the corresponding bit called from the storage; therefore, the final output codeword after being corrected is obtained; and thus, the linearity of the SAR ADC is increased.

A solid-state imager includes a pixel unit for converting incident light into an electrical signal, a substrate bearing the pixel unit formed thereon, an analog-to-digital converter, formed on the substrate, for converting a signal read from the pixel unit into a digital signal, an optical communication unit, arranged on the bottom surface of the substrate opposite the surface of the substrate bearing opposite the top surface of the substrate bearing the pixel unit receiving the incident light, for converting the digital signal converted by the analog-to-digital converter into a light signal and outputting the light signal, and a signal line for transferring the digital signal, converted by the analog-to-digital converter, to the optical communication unit arranged on the bottom surface of the substrate.

A device and process to compensate for asymmetrical qualities of an analog input signal, if present, and generate a timing signal. The timing signal is then used for analog to digital conversion.

Methods and structures are provided for the interleaved calibration and subsequent correction of errors in switched-capacitor converter stages of pipelined analog-to-digital converters. The interleaved calibration can be run continuously or at selected times without disturbing the ongoing processing of input data signals. With first and second sets of capacitors, converter stages interleavably process input data signals and input calibration signals. Once these stages have been calibrated with their second sets of capacitors, the first and second sets are exchanged and the converter stages subsequently process input data signals with their second sets of capacitors.

The invention discloses a successive approximation type analog/digital converter, wherein a capacitor array digital/analog conversion circuit comprises a capacitor array, an auxiliary capacitor is connected between the capacitor array and the output end of a comparer, and the oscillation amplitude between the capacitor array and the output end of the comparer ranges from 0V to power voltage when the capacitance value of the auxiliary capacitor is selected in a range enabling the oscillation amplitude of the input voltage to be from 0V to the power voltage. A measure of carrying out limiting and compression on a quantification range or increasing complicated circuits, which is adopted for preventing voltage overshoot in the traditional scheme, is avoided. According to the circuit structure provided by the invention, the requirements on input offset of the comparer in the ADC (analog/digital converter) and performance of other internal circuits are reduced, so that higher resolution ratio can be achieved under the condition of not increasing power consumption of the ADC using the circuit structure.

A method and apparatus for effective through-the-earth communication involves a signal input device connected to a transmitter operating at a predetermined frequency sufficiently low to effectively penetrate useful distances through-the earth, and having an analog to digital converter receiving the signal input and passing the signal input to a data compression circuit that is connected to an encoding processor, the encoding processor output being provided to a digital to analog converter. An amplifier receives the analog output from the digital to analog converter for amplifying said analog output and outputting said analog output to an antenna. A receiver having an antenna receives the analog output passes the analog signal to a band pass filter whose output is connected to an analog to digital converter that provides a digital signal to a decoding processor whose output is connected to an data decompressor, the data decompressor providing a decompressed digital signal to a digital to analog converter. An audio output device receives the analog output form the digital to analog converter for producing audible output.

Power switches of circuits at respective stages of a low noise amplifier, demodulators, low-pass filers, variable gain amplifiers, and analog-to-digital converters are controlled to be off by an operation control unit in a non-reception period of an impulse signal. An increase in power consumption due to the adoption of an active filter or a variable gain amplifier is compensated for by a reduction in power consumption through intermittent operations of the circuits at the respective stages according to on and off control of the power switches.