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Successive approximation analog-digital converter and analog-digital conversion method based on digital domain self-correcting

An analog-to-digital converter, successive approximation technology, applied in analog/digital conversion, analog/digital conversion calibration/test, code conversion, etc., can solve problems such as increasing chip area

Active Publication Date: 2017-02-01
SOUTHEAST UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] Purpose of the invention: In order to solve the existing capacitance mismatch correction method, an additional correction DAC is usually used to detect and quantify the capacitance mismatch error of the main CDAC, thereby leading to the technical problem of increasing the area of ​​the chip. The present invention proposes a digital based Domain self-correcting successive approximation analog-to-digital converter and analog-to-digital conversion method, which can detect and quantify the capacitance mismatch error of CDAC without additional correction DAC

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  • Successive approximation analog-digital converter and analog-digital conversion method based on digital domain self-correcting
  • Successive approximation analog-digital converter and analog-digital conversion method based on digital domain self-correcting
  • Successive approximation analog-digital converter and analog-digital conversion method based on digital domain self-correcting

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Embodiment

[0058] Example: Assuming that the precision of the fully differential structure SAR ADC is 12 bits, CDAC 101 can be divided into high 8-bit sub-CDACII 1201 and low 4-bit sub-CDACII 1202, the input signal is directly sampled to CDAC, and the first conversion is performed, and the high 8-bit sub-CDACI 1201 Only a 7-bit capacitor array is required. In addition, the terminal matching capacitor in CDAC 101 is in the quantization process C p,0 and C n,0 Switch from the first level GND to the second level V according to the previous comparison result cm , after being compared by the comparator, a redundant bit with a weight of 0.5LSB is output, which is only used for correction purposes.

[0059] Figure 4 It is a schematic diagram of a differential switched capacitor structure CDAC 101 in a 12-bit SAR ADC, and the CDAC 101 is divided into two parts: the upper 8-bit sub-CDACI 1201 and the lower 4-bit sub-CDACII 1202.

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Abstract

The invention provides a successive approximation analog-digital converter and an analog-digital conversion method based on digital domain self-correcting. The successive approximation analog-digital converter comprises a CDAC, a comparator, an SAR control logic circuit, a correction control logic circuit, a storage, an adder and a clock circuit; a differential structure is adopted in the CDAC; capacitor arrays of the CDAC respectively form a high-M-level CDAC and a low-L-level CDAC; on the basis of a capacitor array reusing thought, mismatching errors of various capacitors in the high-M-level CDAC capacitor array are detected by reusing the low-L-level CDAC in a self-correcting stage; detected error values are quantized; error voltage is converted into an error code to output; the output error code is output into the storage; after mismatching error detection and quantization are completed, digital conversion of an input analog signal begins to perform; an original code is output, and operated with the error code at the corresponding bit called from the storage; therefore, the final output codeword after being corrected is obtained; and thus, the linearity of the SAR ADC is increased.

Description

technical field [0001] The invention relates to the technical field of analog-to-digital conversion, in particular to a successive approximation analog-to-digital converter and an analog-to-digital conversion method based on digital domain self-correction. Background technique [0002] As a bridge between the analog world and the digital world, the analog-to-digital converter plays a very important role. The successive approximation analog-to-digital converter has very low power consumption and can achieve high conversion accuracy. Although its serial operation mode results in slow conversion speed, it is very suitable for low-power applications, such as touch screens and wireless transmission. sense network etc. [0003] In addition, with the continuous development of technology in recent years, the conversion speed of the successive approximation converter has been greatly improved, making it possible for high-speed and low-power applications, such as mobile communication...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/38H03M1/10
Inventor 李冬孟桥黎飞王林锋
Owner SOUTHEAST UNIV
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