20 results about "Successive approximation ADC" patented technology

The invention discloses a hybrid level crossing analog-to-digital converter circuit integrating a successive approximation type analog-to-digital converter and an event-driven analog-to-digital converter. The circuit is composed of a level cross analog-to-digital conversion module LC ADC, a logic module LOGIC and a noise shaping successive approximation analog-to-digital converter module NSSAR ADC. The architecture effectively integrates the advantages of two converters, and has the characteristic of ultra-low power consumption of a level crossing analog-to-digital converter while keeping the high precision characteristic of a successive approximation type analog-to-digital converter. The level crossing analog-to-digital conversion module LC ADC does not participate in quantization of input signals and is only used as a pre-detection circuit of level crossing, and the noise shaping successive approximation analog-to-digital conversion module NSSAR ADC is used for completing signal processing actions such as comparison, quantization and output, so that the precision of the output signals is not restricted by the level crossing analog-to-digital conversion module LC ADC. The hybrid architecture can meet the requirements of low-power-consumption and high-precision acquisition of signals of the modern mobile Internet of Things.

This invention relates to a digital calibration method and system for analog-to-digital converters (ADCs) based on an affine projection algorithm, belonging to the field of analog integrated circuits. Taking a split-type successive approximation ADC as an example, the method includes: obtaining the output difference between the first and second ADCs to be calibrated and defining it as an error signal; constructing a projection input matrix and an error vector based on the error signal and the digital code values ​​corresponding to the most recent P conversions; using an affine projection algorithm to output first and second update parameters to update the calibration parameters; and continuously updating the calibration parameters to make the performance indicators of the ADC to be calibrated continuously approach the ideal performance indicators until the error is within the allowable range. This invention constructs a projection input matrix from the digital code values ​​obtained from the current and several historical conversions, and adaptively updates the calibration parameters based on the affine projection algorithm, thereby achieving faster convergence and suppressing oscillations even when the input code pattern correlation is strong.

The invention provides a conversion method and device for a successive approximation analog-to-digital converter, electronic equipment and a storage medium, the successive approximation analog-to-digital converter comprises a comparator, a converter and a capacitor array, the resolution of the successive approximation analog-to-digital converter is N, and the number of capacitors of the capacitor array is N; the method comprises the steps that high-order capacitors and low-order capacitors of a capacitor array are determined, the high-order capacitors comprise m capacitors, and the low-order capacitors comprise n capacitors; determining a first comparison result according to the m capacitors and the comparator, and converting the first comparison result into a first code value through the converter according to a first conversion algorithm; determining a second comparison result according to the n capacitors and the comparator, and converting the second comparison result into a second code value through the converter according to a second conversion algorithm; the first conversion algorithm is different from the second conversion algorithm; and determining a target code value according to the first code value and the second code value. By adopting the application, the conversion precision of the successive approximation analog-to-digital converter can be improved.

The application discloses a kind of based on the transconductance capacitance type residual amplification method and device of cycle operation, belong to integrated circuit design technical field.Transconductance capacitance type residual amplification device includes: based on the transconductance capacitance amplifier and amplifier bias circuit of cycle operation;Adopt odd-even cycle discharge technology, odd cycle and even cycle are alternately carried out cycle discharge and amplification cooperation, realize equivalent gain promotion under low voltage;At the same time, even cycle reduces power consumption by reducing supply voltage;Again adopt tail resistance linearization technology, inhibit the transconductance change in cycle amplification process;The application can more simply construct high-precision, medium-speed pipeline successive approximation ADC under the constraint of low voltage, low power consumption, applicable to industrial internet of things, intelligent sensor and portable medical monitoring and other energy efficiency requirements strict application scenarios, and need and digital chip deep combination system level design.

This invention discloses a dual passive noise shaping and correction method for high-precision successive approximation ADCs. It combines noise shaping technology with a correction algorithm. Within a short period after chip power-on, using a limited correction DAC capacitor array and noise shaping technology, it achieves higher-precision correction codes for SAR ADC capacitor mismatch and comparator offset voltage. In normal operating mode, this invention again incorporates noise shaping technology, adding the correction codes to the main DAC in analog form, reducing the impact of non-ideal factors. This invention reuses sampling integration capacitors, resulting in a simple structure. With minimal power consumption, it significantly improves correction accuracy and increases the overall signal-to-noise ratio and spurious-free dynamic range, thereby enhancing the overall efficiency of the SAR ADC.

This invention relates to the field of integrated circuit technology and provides a successive approximation analog-to-digital converter (ADC) and a comparison method. The comparison method includes: providing a successive approximation ADC comprising n-1 weighted capacitors, a charge transfer capacitor, and a comparator; sampling an input differential signal through the first weighted capacitor and the charge transfer capacitor; importing the input differential signal stored on the charge transfer capacitor, transferring and redistributing the input differential signal across the other n-2 weighted capacitors and the charge transfer capacitor (excluding the first weighted capacitor), completing the first comparison; importing the input differential signal stored on the first weighted capacitor and the input differential signal stored on the charge transfer capacitor, and importing a reference voltage through the second to j-th weighted capacitors, transferring and redistributing the input differential signal and the reference voltage across the capacitor array, completing the j-th comparison, thus solving the bandwidth mismatch problem.

The application discloses a multi-bit quantization discrete sigma-delta modulator and method based on capacitor multiplexing, and belongs to the field of analog-to-digital conversion in analog integrated circuits. The multi-bit quantization discrete sigma-delta modulator based on capacitor multiplexing comprises an integrator module, a P-terminal comparator module, an N-terminal comparator module, a SAR logic module, a P-terminal capacitor array module, an N-terminal capacitor array module, a P-terminal switch array module and an N-terminal switch array module. The application forms a full-differential quantizer by connecting two single-ended successive approximation ADCs in parallel, multiplexes the capacitive DAC of the single-ended successive approximation ADC, realizes the quantization function and the feedback function in the sigma-delta modulator, and improves the modulation precision of the modulator. The application can reduce the number of capacitors required by the multi-bit quantization discrete sigma-delta modulator, thereby reducing the power consumption of the switched capacitor network and the layout area of the modulator.

The invention provides a successive approximation analog-to-digital converter and a correction method thereof. The successive approximation analog-to-digital converter comprises a first digital-to-analog converter, a comparator, a successive approximation controller and a correction controller. The first digital-to-analog converter generates a difference voltage based on an input voltage and a digital code. The digital code corresponds to the sum of the input voltage and the difference voltage. When the difference voltage exceeds a threshold value, the comparator sets the comparison signal to an enabled state. The successive approximation controller adjusts the digital code based on the comparison signal so that the digital code corresponds to the input voltage. The correction controller executes a correction program and is used for determining the delay time required for changing the digital code to change the comparison signal from the disable state to the enabled state.

The present invention discloses a background calibration method for the offset voltage of a pipelined successive approximation ADC, comprising: simultaneously sampling an input signal through a main DAC and a small-capacitor DAC, the output of the small-capacitor DAC being input to the main DAC after passing through a comparator and a logic circuit, the main DAC being amplified by an amplifier to generate a residual signal; the successive approximation ADC receiving the residual signal, finding the maximum and minimum voltage values ​​of the residual signal, averaging to obtain a mean value, comparing the mean value with the amplifier output mean value in the absence of an offset voltage, and determining the polarity of the offset voltage; and controlling the calibration DAC to output a calibration voltage based on the offset voltage polarity determination result, inputting the calibration voltage into a comparator, and offsetting the offset voltage of the comparator and the amplifier. The present invention is unaffected by PVT variations and jitter in the presence of an offset voltage, performs statistics and calculations on the polarity of the offset voltage in the digital domain, and calibrates the offset voltage of the comparator in the analog domain, with low cost and high accuracy.

The application discloses a kind of applied to the calibration method and circuit of pipeline successive approximation type ADC, by input signal and residual signal injection Dither signal, and using Dither_2 signal corresponding to the estimated value Dd2 of digital domain and the gain estimation value of residual signal VR' after injection is calibrated, gain value after calibration is obtained;Using gain value after calibration, digital code D1 and digital code D2 are spliced, to realize the calibration of interstage gain error, output the output signal to be mismatched calibration;The corresponding Dither signal is subtracted in digital domain to the output signal to be mismatched calibration, to find demarcation point, the maximum value of the interval before each demarcation point and the minimum value of the interval after each demarcation point are used to represent the weight mismatch information of the corresponding capacitor of demarcation point;To obtain corresponding error amount by using LMS algorithm to constantly iterate, realize the mismatch calibration of the output signal to be mismatched calibration, to improve the quantization accuracy and linearity of ADC.

The invention discloses a low-noise sampling hold circuit for a successive approximation type ADC and a sampling hold method of the low-noise sampling hold circuit, the low-noise sampling hold circuit comprises a noise elimination sampling circuit comprising a capacitance multiplication circuit, and the output end of the noise elimination sampling circuit is sequentially connected with a comparator, an SAR logic control circuit and a segmented resistor DAC. The input end of the noise elimination sampling circuit is connected with sampling voltage and output voltage of the segmented resistor DAC. Noise of a switch and an operational amplifier in the sampling hold circuit is effectively eliminated through charge sharing and a capacitance multiplication circuit, equivalent input noise at the front end of the ADC is remarkably reduced, the problem that low noise of the operational amplifier, bandwidth and power consumption are difficult to consider at the same time is solved, and complex low-noise design of a main path operational amplifier is avoided. According to the invention, the signal-to-noise ratio of the sampling hold circuit is greatly improved, the significant digits and quantization precision of an ADC system are improved, and the sampling hold circuit has the advantages of being simple in structure and easy to implement.

The invention discloses a dynamic open-loop amplifier circuit for a pipelined successive approximation type ADC (Analog to Digital Converter), which comprises an amplifier input stage and a load output stage, and is characterized in that the amplifier input stage is of an FVF differential pair structure and is used for providing high-linearity transconductance for the circuit; the load output stage can avoid linearity deterioration caused by total output impedance change due to output MOS tube channel resistance change when the output end swing is too large. The method has the beneficial effects that the linearity of residual error amplification can be remarkably improved, the gain with highly stable PVT is generated, and the power consumption and the amplification time are saved.

A successive approximation ADC includes a switch circuit, a conversion circuit, a comparison circuit and a controller. The conversion circuit outputs first and second comparison voltages that are respectively equal to first and second input voltages when the switch circuit operates in an ON state. The comparison circuit compares the first and second comparison voltages to generate first and second comparison signals. Generation of least significant bits of the first and second comparison signals is related to two first capacitors and two second capacitors of the conversion circuit. When the other bits of the first comparison signal have identical logic values, the controller provides two different voltages respectively to the first capacitors and respectively to the second capacitors; and when otherwise, the controller provides one of the voltages to both of the first capacitors, and provides the other one of the voltages to both of the second capacitors.

An apparatus, system, and method for are provided. A device includes a time-to-digital converter (TDC) situated to convert a time-domain signal to a digital value, a delay circuit situated in parallel with the TDC and to delay the time-domain signal by a specified amount of time resulting in a delayed time-domain signal, a time-to-voltage converter (TVC) situated to produce a voltage-domain signal based on the delayed time-domain signal, and a successive approximation (SAR) circuit situated to receive the digital value and the voltage-domain signal and produce a digital-domain version of the input signal.

The invention discloses a segmented resistor DAC dynamic mismatch calibration circuit for a successive approximation type ADC, and the circuit comprises a switched capacitor sampling circuit, the input end of the switched capacitor sampling circuit is connected with a to-be-sampled voltage VIN and an output voltage VDAC of a segmented resistor DAC, and the output end of the switched capacitor sampling circuit is connected with the input end of a comparator module. The output end of the comparator module is connected with the input end of the SAR logic control circuit, the output of the SAR logic control circuit controls the output voltage of the segmented resistor DAC, the output of the SAR logic control circuit is further connected with the input end of the register, and the output end of the register is connected with the DEM averaging module. The invention further discloses a segmented resistor DAC dynamic mismatch calibration method for the successive approximation type ADC. According to the invention, the problem of resistor mismatch in the segmented resistor DAC is solved, and the output precision of the segmented resistor DAC is improved.

The present invention discloses a capacitance calibration method for a successive approximation ADC, comprising: initializing the differential mode digital weights and single-ended mode digital weights of all capacitances to be calibrated in a switched capacitor module with the digital weights of ideal capacitances; successively obtaining the actual digital weights of each capacitance to be calibrated in the differential mode and assigning them to the corresponding differential mode digital weights; successively obtaining the actual digital weights of each capacitance to be calibrated in the single-ended mode and assigning them to the corresponding single-ended mode digital weights; according to the selected differential mode or single-ended mode, assigning each of the differential mode digital weights or each of the single-ended mode digital weights to each actual final digital weight; adding the analog output signal of the successive approximation ADC bit by bit using each actual final digital weight to obtain a digital output signal. The present invention can achieve self-calibration of capacitances without the need for an additional calibration capacitance array.

The invention provides a sequential self-adjustment-based successive approximation analog-to-digital converter. The sequential self-adjustment-based successive approximation analog-to-digital converter comprises a sampling and holding switch, a capacitive digital-to-analog converter, a dynamic comparator COM, an XNOR gate, a phase inverter and M delay units Mlt, the bit number N of the analog-to-digital converter, the frequency selector, the output holding circuit and the input end of the sampling holding switch are connected with an external signal VIN, and the output end of the sampling holding switch is connected with an upper board of the capacitive digital-to-analog converter and the positive input end VP of the dynamic comparator COM; the negative input end VN of the dynamic comparator COM is connected with a reference voltage Vref, and the output ends OUTN and OUTP of the dynamic comparator COM are respectively connected with the input end of the XNOR gate and the input end of the output holding circuit; according to the invention, the successive comparison switching time after the sampling of the successive approximation type analog-to-digital converter is finished can be effectively reduced, so that the sampling speed of the whole successive approximation type analog-to-digital converter is improved.

The present invention discloses a method for ADC digital background calibration based on an intelligent optimization algorithm, comprising: after receiving M groups of output data sent by an analog-to-digital converter, constructing M groups of interpolation output codes using a Lagrange interpolation algorithm; constructing a target optimization function based on the M groups of output data and the M groups of interpolation output codes, and performing an optimization search using a particle swarm optimization algorithm to obtain M groups of weights so that the mean square error between each group of output data and its corresponding interpolation output code is minimized; and the average value of the M groups of weights is output as the optimal weight for this optimization search and as the central value for the next optimization search. By combining the interpolation and particle swarm optimization algorithms as a framework to optimize the search for the target optimization function, with the goal of minimizing the mean square error between the M groups of output data and their corresponding interpolation output codes, the optimal weight is obtained, thereby improving the accuracy of the successive approximation ADC and simply and efficiently implementing the digital background calibration of the ADC.

The invention belongs to the field of analog integrated circuit calculation, and particularly relates to a grid voltage bootstrapped switch circuit applied to an assembly line successive approximation type ADC, the working mode of the grid voltage bootstrapped switch circuit is divided into a sampling state and a holding state, and the two states are controlled by two non-overlapping clocks CLK and CLKB respectively; when the CLK is in a high level and the CLKB is in a low level, the grid voltage bootstrapped switch is in a holding state, and the output voltage VOUT is kept unchanged; on the contrary, when the CLK is in a low level and the CLKB is in a high level, the grid voltage bootstrapped switch is in a sampling state, and the output voltage VOUT changes along with the change of the input signal VIN. According to the circuit, the area of a traditional gate voltage bootstrapped switch is reduced, meanwhile, the gate parasitic capacitance of the sampling input tube is effectively reduced, and the linearity and speed of the gate voltage bootstrapped switch are improved on the whole.