97 results about "Track and hold" patented technology

Methods of and apparatuses for matching the signal delay, clock timing, frequency response, gain, offset, and/or transfer function of signal pathways in electrical circuits such as, for example, time-interleaved and pipelined circuits using analog-valued floating-gate MOSFETs are disclosed. The methods and apparatuses disclosed are applicable to a variety of circuits, including but not limited to, sample-and-hold or track-and-hold circuits, quadrature mixers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), analog or digital filters, and amplifiers.

An ultrasound imaging system uses a magnetic linear motor driven ultrasound scanner, with accurate track and hold operation and/or other motion feedback, to scan a two dimensional or three dimensional area of a sample. The scanner is implemented in a low-power and low-bandwidth handheld device and is connected with a remote image processing system that receives raw data and performs full ultrasound image analysis and creation, allowing the handheld to be used for scanning, pre-processing, and display.

A system and method for converting an analog signal to a digital signal is provided. The analog to digital conversion is achieved without a dedicated sample-and-hold circuit. An ADC stage, preferably the front-end stage in the case of a pipeline ADC, samples the input voltage within a quantizer and within a residue generator. The sampling is performed with associated clocking signals and with switch capacitors also fulfilling the comparison with threshold voltages, within the quantizer and the generation of a residue signal within the residue generator.

A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGS-VT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.

A method of and system of processing a phase-modulated optical signal includes performing, by demodulators, demodulation of the phase-modulated optical signal and outputting optical demodulated signals. The processing further includes performing, by pairs of gated photo detectors respectively connected to the I/Q demodulators, photo detection of the demodulated signals. The processing further tracks and holds electronicversions of the demodulated signals with a track and hold amplifier.

An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

The invention provides a measurement and control method based on a Ka-S-band relay integrated measurement and control system. The method comprises two communication links: S-band relay measurement and control and Ka-band relay measurement and control. An integrated association design technology is employed in the two kinds of band relay. Wide beam antennas are employed in the S-band relay measurement and control communication link and to-sky and to-ground array transmitting/receiving is realized, thereby realizing wide beam coverage. Phased array antennas are employed in the Ka-band relay measurement and control communication link, the Ka relay link can be rapidly tracked and held under the condition that platform postures are continuously changed, and to-sky and to-ground array transmitting/receiving is realized, thereby realizing wide beam coverage. According to the method, the problem that the communication rate is relatively low when the S-band relay measurement and control is employed independently, a real-time coverage range is small when the Ka-band relay measurement and control is employed independently, and the efficiency is relatively low when the two forms of relay measurement and control is not related, in aircraft relay measurement and control is solved.

The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Plasma processing apparatuses and techniques for processing substrates, which include the use of synchronized RF pulsing of a first RF signal and a delayed-and-shortened second RF signal. The first RF signal may be the primary plasma-generating RF signal and the second RF signal may be the RF bias signal or vice versa. Alternatively or additionally, the first RF signal may be the high frequency RF signal and the second RF signal may be the lower frequency RF signal. Either the first RF signal or the second RF signal may act as the master, with the other acting as the slave signal. Alternatively, an external circuit may be employed as a master to control both the first RF signal and the second RF signal as slave signals. Track-and-hold techniques and circuits are provided to ensure accurate measurement for process control and other purposes.

In an embodiment, an analog to digital converter (ADC) has a dynamic power circuit. The ADC has a track-and-hold circuit with an output and a track mode. The ADC also has a comparator with an input. A preamplifier is coupled between the track-and-hold output and the comparator input. At least one of a preamplifier current and a comparator current are limited during the track mode to reduce ADC power consumption.

A Sampled Pipeline Subranging Converter (SPSC) may include at least one stage—e.g. at least the input stage—operating in a time-continuous fashion. In the time continuous input stage, the analog input may be processed in two parallel paths. A lower path may comprise a track-and-hold (T/H) element, an Analog-to-Digital-Converter (ADC) and a Digital-to-Analog-Converter (DAC). The T/H element may be optional and may be present if required by the ADC. The signal entering the lower path may be sampled at the desired conversion rate. The time continuous stage(s) may additionally be configured with an upper path that includes a delay element configured to receive the analog input, a Low-Pass (LP) filter coupled to the delay element, and an anti alias filter. The output generated by the DAC may be subtracted from the output of the LP filter, and the resulting difference signal may be provided to the anti alias filter, which in turn may generate the residue (or error) output. The digital output of the time continuous converter may be calculated by combining the digital outputs of the various sections.

A wideband track-and-hold amplifier is provided. The wideband track-and-hold amplifier is provided in front of an analog-to-digital converter, receives and samples an analog signal, and transfers the sampled signal to the analog-to-digital converter, wherein an output load unit having an inductance component is connected to an input terminal of the analog-to-digital converter. Therefore, it is possible to compensate for a high capacitance component of an analog-to-digital converter, to increase the bandwidth of an output signal, and to improve system linearity.

An interleaved track-and-hold front-end with multiphase clocks computes and propagates unrolled decision feedback equalization results along a pipeline with the final outputs selected from one of the interleaved previous output bits with a multiplexer operating over multiple unit intervals instead of one unit interval. An n-way interleaved serializer/deserializer utilizes an n unit interval multiplexer or n one unit interval multiplexers. Pipelined decision feedback equalization allows multiple, slower multiplexers.

A circuit design incorporates charge compensation devices within a Track-and-Hold (T/H) circuit to control channel charge generated by a tracking switch. Calibrating a T/H circuit requires selecting charge compensation devices from an array of similar devices to function within the T/H circuit to absorb charge ejected from the tracking switch. The charge compensation devices can also be pseudorandomly selected to operate within the T/H circuit. Charge compensation devices are used to enhance the performance of bottom-plate sampling systems as well as bootstrapped T/H circuits.

The invention discloses a high-sampling-rate broadband track and hold circuit and relates to the technical field of electrons. The track and hold circuit comprises an input buffer unit IB, a track/hold switch T/H, a holding capacitor CH and an output buffer unit OB. A full-differential circuit structure is introduced to realize good common-mode noise suppression ability; through the input and output buffers having emitter degeneration resistors, linearity of the track and hold circuit is improved; an improved switch emitter follower having a Schottky diode is adopted as a track and hold switch, so that circuit stability is improved; and the track and hold circuit is designed by utilizing a GaAs HBT device having high cut-off frequency and good base-emitter match, thereby solving the defects of low sampling rate and narrow bandwidth of an existing sampling and hold circuit.

An exemplary differential track and hold amplifier includes a track stage including first and second linearized pairs connected in series at their respective inputs and in parallel at their respective outputs. The differential track and hold amplifier also includes a hold stage selectively coupled to the outputs of the first and second linearized pairs. The hold stage includes a unity gain buffer with feedback having a hold capacitor interconnected across its outputs. The differential track and hold amplifier also includes an output buffer coupled to the outputs of the hold stage. An exemplary analog-to-digital converter includes a differential track-and-hold amplifier, a voltage ladder, and a plurality of slices. Each of the slices in turn includes a differential preamplifier coupled to the track-and-hold amplifier and to a corresponding location on the voltage ladder; a current mode logic latch comparator coupled to the differential preamplifier; a large-swing latch coupled to the current mode logic latch comparator; a complementary metal oxide semiconductor latch having a dummy load; a calibration digital to analog converter connected across outputs of the differential preamplifier to inject calibration currents; and a register coupled to the calibration digital to analog converter and storing calibration values for use thereby. The analog-to-digital converter also includes a multiplexer which multiplexes outputs of the complementary metal oxide semiconductor latches down to a predetermined number of outputs.