203results about "Synchronisation receivers" patented technology

The invention provides a phase tracking enhancement method, a storage medium and a product. The method comprises the following steps: processing a received signal by a receiver to obtain a channel estimation value on each subcarrier; acquiring a first pilot signal inserted on a preset position subcarrier of each OFDM symbol based on the received signal, and performing initial phase tracking according to the first pilot signal and the channel estimation value to obtain an initial phase parameter; based on the first result after channel equalization, the second result after demapping or the third result after error correction decoding, reconstructing to obtain a second pilot signal; and performing enhanced phase tracking according to the first pilot signal, the second pilot signal and the channel estimation value to obtain an updated phase parameter. Therefore, phase tracking can be performed based on more pilot signals, the accuracy of phase tracking can be improved, and the phase parameter estimation error can be reduced.

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

This disclosure is generally directed to a full-duplex transceiver including a primary circuit and a secondary circuit communicating using a clock signal of the primary circuit (e.g., a single clock signal). The primary circuit may include circuitry to generate and / or forward the clock signal to the secondary circuit. The secondary circuit may sample received data using the clock signal. Moreover, the secondary circuit may generate data, perform data processing operations, and / or transmit data using the clock signal of the primary circuit.

The invention belongs to the technical field of multi-machine communication, and particularly relates to a multi-machine communication device and method for a 2.4 G wireless gamepad. Comprising a handle end; comprising a first handle and a second handle. The USB end is used for transmitting and receiving wireless data, performing wireless data interaction with the handle end and transmitting key value data to the PC; the private protocol is used for wireless data interaction; the time sequence synchronization module is used for synchronizing the receiving and transmitting time sequences of the USB end and the handle end; the self ID module is used for data interaction identification, and each USB end and each handle end respectively and independently have a unique ID; the mapping module is used for realizing mapping of a channel and an access address according to the ID module of the USB end; wherein the mapping of the channels is that the channels are mapped to 2402MHz-2530MHz according to the ID (Identity) of a USB (Universal Serial Bus) end in a user-defined manner, the interval between every two adjacent values is 1MHz, and the number of the channels is 129; the device has the advantages that the cost is low, the anti-interference performance is high, and the requirement that multiple sets of equipment work independently in the same space without interfering with one another can be met.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

A signal receiving circuit includes first to third pulse generators; and a clock signal recovery unit 100 for generating a recovery clock signal RCLK and a recovery clock delay signal RCLKD, which is a signal obtained by delaying the recovery clock signal as much as a first delay time, using at least one of pulses including a first pulse, a second pulse, a third pulse, and first to third inversion pulses, wherein the clock signal recovery unit includes: a loop interruption circuit including an input node and an output node and turned on and off by at least one of the pulses; and a delay circuit having an input terminal connected to the output node and an output terminal connected to the input node. A signal value of the input node and a signal value of the output node are in an inverse relationship.

Some embodiments relate to a communication network comprising at least one receiver system optically coupled to a plurality of transmitter systems for transmission of synchronization signals generated by the at least one receiver system to the plurality of transmitter systems over a unidirectional synchronization channel. The at least one receiver system configured to embed into the synchronization signals thereby generated additional data indicative of an internal time count thereof for synchronization of transmission of data / signals from each one of the plurality of transmitter systems to said at least one receiver system over a sparse data / signals unidirectional communication channel.

A method includes that a first secured frame to be transmitted in a slot in a first round belonging to a first block based on a block-based time structure or a hyper block-based time structure may be generated, where the block-based time structure or the hyper block-based time structure comprises a plurality of blocks, each block of the plurality of blocks comprises a plurality of rounds, each round of the plurality of rounds comprises a plurality of slots, the first secured frame is secured by a first nonce being constructed based on identifying information associated with the first secured frame, a round index and a block index, the round index is an index of the first round, and the block index is an index of the first block.

A clock circuit, a receiver, and a passive optical communication network system are disclosed. The clock circuit is applied to a receiver in a passive optical communication network and is configured to adjust the clock frequency of an output clock signal based on a transmission protocol, the clock circuit comprises at least one clock path and a frequency divider, and the at least one clock path comprises a first clock path; wherein the first clock path receives a reference clock signal from the first phase-locked loop circuit and a control signal from the clock data recovery circuit, and interpolates a conversion signal of the reference clock signal by using the reference clock signal so as to output a multi-phase clock signal; and the frequency divider receives the multi-phase clock signal and performs frequency division on the multi-phase clock signal based on a preset frequency division value, and the preset frequency division value is determined based on a transmission protocol. The clock circuit can be compatible with fast clock switching schemes of data rates of different PON protocols, so that the adaptability and the locking performance of a receiver in a burst mode are improved.

Embodiments herein describe techniques for area and power efficient clock data recovery (CDR) and adaptation implementations for dense wavelength-division multiplexing (DWDM) optical links and other types of links. One example is a system that includes a plurality of receiver circuits that sample signals based on respective receiver clocks, where the receiver circuits include a reference receiver circuit and remaining receiver circuits, and where the receiver clock of the reference receiver circuit comprises a reference clock. The system further includes a clock and data recovery (CDR) circuit that controls a phase of the reference clock based on outputs of the reference receiver circuit, and time-multiplexed de-skew circuitry configured to determine time-multiplexed phase offsets for the remaining receiver circuits based on time-multiplexed outputs of the remaining receiver circuits, where the remaining receiver circuits phase-shift the reference clock based on the respective time-multiplexed phase offsets to provide the respective receiver clocks.

A first device includes a transceiver to communicate with a second device over an interposer, the interposer comprising a plurality of conductive traces between the first device and the second device. The first device also includes control logic, coupled to the transceiver associated with the first device, configured to send first data to the second device over a conductive trace of the plurality of conductive traces, simultaneously receive second data from the second device over the conductive trace, and extract the second data from a combined signal comprising the first data and the second data.

The embodiment of the invention discloses a data synchronization method, device and system. In a scene of synchronizing data streams of a physical layer, the synchronization process of the data streams can be timed. Furthermore, whether the data stream with the time length meeting the timeout condition exists in the synchronization process is judged, which is equivalent to whether the situation that the synchronization time is too long exists. If the condition that the synchronization time is too long exists, it is indicated that a system fault or link deterioration may occur, then corresponding timeout processing, such as error reporting and system resetting, needs to be carried out, so that the system fault or link deterioration can be dealt with in time, and the data transmission efficiency is optimized.

The invention provides a data receiving method, a data sending method and a data exchange device, and the method comprises the steps: changing the frequency of a second clock signal in response to the change of a reference clock from a first preset frequency to a second preset frequency, and enabling the frequency of the second clock signal and the frequency of the reference clock to meet a preset relation; according to a second preset frequency, performing delay processing or advanced processing on the second clock signal to obtain a third clock signal; receiving a serial data stream according to the third clock signal, wherein the serial data stream has a data transmission delay of a first preset duration; wherein the frequency of the third clock signal is equal to that of the first clock signal, and the phase difference between the third clock signal and the first clock signal is equal to the first preset duration. According to the invention, the transmission accuracy of the serial data stream can be ensured after the frequency of the reference clock is changed.

Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

The present invention relates to the field of optical communication technologies, and discloses an optical clock recovery system and method. The present invention converts an optical signal of a clock to be recovered into an electrical signal, and outputs the electrical signal to a digital signal processing module; outputs a configuration instruction to the digital signal processing module, and when the digital signal configuration rate in the configuration instruction matches the electrical signal, performs signal locking, controls an indication module to perform corresponding locking indication, and configures the digital signal processing module to enable a clock output module to output the recovered clock in the optical signal of the clock to be recovered. The present invention has the technical effects of supporting single-mode and multi-mode optical signal input, fast signal locking, stability, and small output clock jitter.

The present invention provides a communication signal timing error compensation method and device, which includes: processing a signal sent by a transmitter through upsampling, a shaping filter, a transmission channel, a matched filter, and downsampling in sequence to obtain time domain samples of the signal; convolving the filter coefficients of the shaping filter with the filter coefficients of the matched filter to obtain filter coefficients of the time domain samples, and extracting the effective filter coefficients of each time domain sample; constructing a matrix based on the effective filter coefficients of the time domain samples, extracting a submatrix from the matrix based on the number of delayed samples corresponding to each timing error, and calculating the timing compensation coefficient for each timing error based on the submatrix; querying the timing compensation coefficient corresponding to the actual timing error of the current signal, performing timing compensation on the current signal based on the timing compensation coefficient corresponding to the actual timing error, and obtaining a timing-compensated signal. The present invention has a simple structure and low computational complexity, effectively reducing computational complexity and storage space.

Frequency error tracking and lane monitoring techniques for multi-lane optical transceivers are provided. In one aspect, a method includes capturing phase and frequency information recovered by clock-and-data recovery circuits from data traveling along a plurality of lanes of an optical transceiver, with one of the lanes being a master lane; determining a frequency error based on the phase and frequency information of the master lane; outputting, by a tunable oscillator, a reference clock based on the frequency error; and controlling the optical transceiver based on i) a transmitter clock signal generated by a transmitter phase-locked loop (PLL) using the reference clock signal, and ii) a receiver clock signal generated by a receiver PLL using the reference clock signal.

The invention provides a loop parameter adaptive measurement and control signal tracking method and device, and belongs to the technical field of measurement and control, and the method comprises the steps: obtaining the tracking state parameters of a carrier ring, a code ring and a bit ring in a current tracking period; determining a bandwidth adjustment direction of the carrier ring and a bandwidth adjustment rate of the carrier ring based on the tracking state parameter of the carrier ring and the tracking state parameter of the bit ring; determining the carrier ring bandwidth of the next tracking period based on the bandwidth adjustment direction and the bandwidth adjustment rate; and determining the code loop bandwidth of the next tracking period based on the tracking state parameter of the code loop, and determining the bit loop bandwidth of the next tracking period based on the tracking state parameter of the bit loop, so as to realize the combined tracking of the carrier loop, the code loop and the bit loop on the input measurement and control signal. According to the invention, high-precision robust tracking of the measurement and control signal in a high-dynamic and low-signal-to-noise-ratio environment can be realized.

The invention discloses a timing synchronization method based on an FSK (Frequency Shift Keying) signal, and relates to the technical field of timing synchronization in wireless communication. The method comprises the following steps: firstly, converting a signal on a time domain to a frequency domain through sliding discrete Fourier transform to be analyzed and processed, then respectively calculating the power of a corresponding frequency spectrum position, respectively summing and subtracting a positive frequency point spectral line and a negative frequency point spectral line, then extracting the power difference of the positive frequency point spectral line and the negative frequency point spectral line, and calculating the power difference of the positive frequency point spectral line and the negative frequency point spectral line. The sampling rate after extraction is quadruple or eight times of sampling signals, finally, digital square timing is carried out on the sampling signals to extract timing errors, a symbol clock is generated according to the errors, the optimal sampling point is selected to recover data, and timing is completed. The method is suitable for FSK signals of different modulation orders, is suitable for an FDMA system for processing continuous signals, has a wide application range, and has the advantage of low complexity based on sliding FFT processing.

Embodiments of the present disclosure relate to sensor devices and related methods and systems. A sensor includes a detection circuit device and a control circuit device coupled to the detection circuit device. The detection circuit device generates a detection signal indicative of a detected physical quantity. In operation, the control circuit device receives the detection signal and a frequency indication signal and generates a trigger signal based on the frequency indication signal and a set of local reference signals. The sensor generates a digital output signal and a lock signal based on the trigger signal and the detection signal. Generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal. The lock signal is temporally aligned with the digital output signal.

An embodiment includes a forward data receiving device that demodulates and receives an Amplitude Shift Keying (ASK) modulation signal, and includes: an input module configured to receive the ASK modulation signal as an input; a resonance regulating rectifier module configured to regulate and rectify an input voltage of the ASK modulation signal on the basis of Pulse Width Modulation (PWM) according to a preset target voltage, and apply a regulated voltage through an output transistor; and a demodulation module configured to demodulate the ASK modulation signal according to a trend in a change of the input voltage compared to the regulated voltage, wherein the resonance regulating rectifier module includes a comparison unit configured to generate a gate signal for controlling on / off of the output transistor, and generate a sample signal for demodulating the ASK modulation signal.

A network device includes control logic coupled to a receiver. The control logic detects an synchronization packet received via the receiver from a second network device over a network that is precision time protocol unaware. The control logic determines that a portion of the synchronization packet is asserted, indicating that the synchronization packet has incurred congestion traversing the network. The control logic adjusts, based on an assertion of the portion, a weight applied to timestamps associated with sending and receiving the synchronization packet in performing clock synchronization with the second network device.

The present invention relates to a composite differential frame synchronization algorithm for burst communication under high dynamic conditions. The algorithm comprises the following steps: Step 1: differentially processing the received signal. In high dynamic scenarios, differential processing is required to reduce the influence of frequency deviation and obtain a differential sequence; Step 2: processing multiple groups of differential sequences in parallel, repeating Step 1, wherein each differential process differs in that the delay period of the differential is different, i.e., obtaining multiple groups of differential sequences with different delay periods; then sliding the phase of each group of differential sequences, and using the maximum value as the cross-correlation value of the differential sequence after passing through a filter, etc. The method of the present invention has the following advantages: it is easy to implement in hardware, has low complexity, can quickly obtain frame synchronization results, and can then quickly demodulate the signal to obtain information. It is suitable for burst signals, has real-time performance, and has wide application value in military battlefields.

According to the invention, the optical signal wavelength test module, the optical signal frequency test module, the optical signal intensity test module and the optical signal rate test module are arranged to detect the wavelength, frequency, intensity and rate of an input optical signal; the method comprises the following steps: firstly, carrying out all-optical clock recovery processing on optical signals with different wavelengths and rates by setting a single recovery module and a multi-recovery module; classifying the optical signals with different wavelengths and rates; whether to carry out photoelectric signal conversion is to carry out mode locking by using a traditional electric module or directly carry out optical mode locking by using an active mode-locking laser module capable of carrying out mode locking on an optical signal with a higher transmission rate is determined by detecting the rate of the optical signal, so that the situation that the traditional electric module cannot process the optical signal with an overhigh rate is prevented; processing can be carried out according to different optical signal transmission rates; the mode locking modes of different electric signals after photoelectric transmission are determined by detecting the intensity and frequency of optical transmission signals.

A method of reducing the effects of variation in latency in data transfer between clock domains of a physical layer transceiver, the physical layer transceiver comprising physical coding sublayer circuitry having a first clock in a first clock domain and physical medium attachment circuitry having a second clock in a second clock domain, comprising: during initial training of the link, determining a transmit latency value in a transmission direction from the first clock domain to the second clock domain; during initial training of the link, separately from determining the transmit latency value, determining a receive latency value in a reception direction from the second clock domain to the first clock domain; and using the transmit latency value and the receive latency value to calculate latency in data transfer between the first clock domain and the second clock domain after the initial training until a subsequent training.

Embodiments herein describe techniques for area and power efficient clock data recovery (CDR) and adaptation implementations for dense wavelength-division multiplexing (DWDM) optical links and other types of links. One example is a system that includes a plurality of receiver circuits that sample signals based on respective receiver clocks, where the receiver circuits include a reference receiver circuit and remaining receiver circuits, and where the receiver clock of the reference receiver circuit comprises a reference clock. The system further includes a clock and data recovery (CDR) circuit that controls a phase of the reference clock based on outputs of the reference receiver circuit, and time-multiplexed de-skew circuitry configured to determine time-multiplexed phase offsets for the remaining receiver circuits based on time-multiplexed outputs of the remaining receiver circuits, where the remaining receiver circuits phase-shift the reference clock based on the respective time- multiplexed phase offsets to provide the respective receiver clocks.

An example device (102) includes a feed forward equalizer (FFE) (122) having an FFE output, a summer circuit (124) having a first summer input, a second summer input, and a first summer output, the first summer input coupled to the FFE output, a multiplexer (MUX) (126) having a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first summer output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) (130) having a DFE output coupled to the second summer input, and a timing error detector (TED) (136) having a first TED input coupled to the MUX output.

An electronic device includes a first electronic device and a second electronic device configured to transmit and receive signals based on a C-PHY protocol. The second electronic device includes a calibrator configured to receive recovered data via a data path used to receive real data and provide a calibration value; and a clock recoverer configured to recover a clock signal (CLK) using the calibration value.

Example embodiments of the present disclosure relate to methods, devices, apparatuses and a computer readable storage medium for communication. In some embodiments, a first secured frame to be transmitted in a slot in a first round belonging to a first block based on a block-based time structure or a hyper block-based time structure may be generated, where the block-based time structure or the hyper block-based time structure comprises a plurality of blocks, each block of the plurality of blocks comprises a plurality of rounds, each round of the plurality of rounds comprises a plurality of slots, the first secured frame is secured by a first nonce being constructed based on identifying information associated with the first secured frame, a round index and a block index, the round index is an index of the first round, and the block index is an index of the first block. As such, the security operation may be performed and the communication can be guaranteed to be secured.

A receiver and a related signal processing method are disclosed. The receiver includes a filter, a signal detection circuit, and a synchronization processing circuit. The filter is configured to perform a filtering operation on a filter input signal to generate a filter output signal. The signal detection circuit is configured to determine whether the filter input signal or the filter output signal includes an interference signal based on the filter input signal and the filter output signal to generate an interference signal indicator, and determine whether the filter output signal includes a valid signal based on the interference signal indicator when the interference signal indicator indicates that the filter input signal or the filter output signal includes the interference signal to generate a valid signal indicator. The synchronization processing circuit is configured to process the filter output signal based on the interference signal indicator and the valid signal indicator.