126results about "Synchronisation receivers" patented technology

This disclosure is generally directed to a full-duplex transceiver including a primary circuit and a secondary circuit communicating using a clock signal of the primary circuit (e.g., a single clock signal). The primary circuit may include circuitry to generate and / or forward the clock signal to the secondary circuit. The secondary circuit may sample received data using the clock signal. Moreover, the secondary circuit may generate data, perform data processing operations, and / or transmit data using the clock signal of the primary circuit.

Some embodiments relate to a communication network comprising at least one receiver system optically coupled to a plurality of transmitter systems for transmission of synchronization signals generated by the at least one receiver system to the plurality of transmitter systems over a unidirectional synchronization channel. The at least one receiver system configured to embed into the synchronization signals thereby generated additional data indicative of an internal time count thereof for synchronization of transmission of data / signals from each one of the plurality of transmitter systems to said at least one receiver system over a sparse data / signals unidirectional communication channel.

A method includes that a first secured frame to be transmitted in a slot in a first round belonging to a first block based on a block-based time structure or a hyper block-based time structure may be generated, where the block-based time structure or the hyper block-based time structure comprises a plurality of blocks, each block of the plurality of blocks comprises a plurality of rounds, each round of the plurality of rounds comprises a plurality of slots, the first secured frame is secured by a first nonce being constructed based on identifying information associated with the first secured frame, a round index and a block index, the round index is an index of the first round, and the block index is an index of the first block.

A clock circuit, a receiver, and a passive optical communication network system are disclosed. The clock circuit is applied to a receiver in a passive optical communication network and is configured to adjust the clock frequency of an output clock signal based on a transmission protocol, the clock circuit comprises at least one clock path and a frequency divider, and the at least one clock path comprises a first clock path; wherein the first clock path receives a reference clock signal from the first phase-locked loop circuit and a control signal from the clock data recovery circuit, and interpolates a conversion signal of the reference clock signal by using the reference clock signal so as to output a multi-phase clock signal; and the frequency divider receives the multi-phase clock signal and performs frequency division on the multi-phase clock signal based on a preset frequency division value, and the preset frequency division value is determined based on a transmission protocol. The clock circuit can be compatible with fast clock switching schemes of data rates of different PON protocols, so that the adaptability and the locking performance of a receiver in a burst mode are improved.

A first device includes a transceiver to communicate with a second device over an interposer, the interposer comprising a plurality of conductive traces between the first device and the second device. The first device also includes control logic, coupled to the transceiver associated with the first device, configured to send first data to the second device over a conductive trace of the plurality of conductive traces, simultaneously receive second data from the second device over the conductive trace, and extract the second data from a combined signal comprising the first data and the second data.

The invention provides a data receiving method, a data sending method and a data exchange device, and the method comprises the steps: changing the frequency of a second clock signal in response to the change of a reference clock from a first preset frequency to a second preset frequency, and enabling the frequency of the second clock signal and the frequency of the reference clock to meet a preset relation; according to a second preset frequency, performing delay processing or advanced processing on the second clock signal to obtain a third clock signal; receiving a serial data stream according to the third clock signal, wherein the serial data stream has a data transmission delay of a first preset duration; wherein the frequency of the third clock signal is equal to that of the first clock signal, and the phase difference between the third clock signal and the first clock signal is equal to the first preset duration. According to the invention, the transmission accuracy of the serial data stream can be ensured after the frequency of the reference clock is changed.

The present invention provides a communication signal timing error compensation method and device, which includes: processing a signal sent by a transmitter through upsampling, a shaping filter, a transmission channel, a matched filter, and downsampling in sequence to obtain time domain samples of the signal; convolving the filter coefficients of the shaping filter with the filter coefficients of the matched filter to obtain filter coefficients of the time domain samples, and extracting the effective filter coefficients of each time domain sample; constructing a matrix based on the effective filter coefficients of the time domain samples, extracting a submatrix from the matrix based on the number of delayed samples corresponding to each timing error, and calculating the timing compensation coefficient for each timing error based on the submatrix; querying the timing compensation coefficient corresponding to the actual timing error of the current signal, performing timing compensation on the current signal based on the timing compensation coefficient corresponding to the actual timing error, and obtaining a timing-compensated signal. The present invention has a simple structure and low computational complexity, effectively reducing computational complexity and storage space.

Frequency error tracking and lane monitoring techniques for multi-lane optical transceivers are provided. In one aspect, a method includes capturing phase and frequency information recovered by clock-and-data recovery circuits from data traveling along a plurality of lanes of an optical transceiver, with one of the lanes being a master lane; determining a frequency error based on the phase and frequency information of the master lane; outputting, by a tunable oscillator, a reference clock based on the frequency error; and controlling the optical transceiver based on i) a transmitter clock signal generated by a transmitter phase-locked loop (PLL) using the reference clock signal, and ii) a receiver clock signal generated by a receiver PLL using the reference clock signal.

The invention provides a loop parameter adaptive measurement and control signal tracking method and device, and belongs to the technical field of measurement and control, and the method comprises the steps: obtaining the tracking state parameters of a carrier ring, a code ring and a bit ring in a current tracking period; determining a bandwidth adjustment direction of the carrier ring and a bandwidth adjustment rate of the carrier ring based on the tracking state parameter of the carrier ring and the tracking state parameter of the bit ring; determining the carrier ring bandwidth of the next tracking period based on the bandwidth adjustment direction and the bandwidth adjustment rate; and determining the code loop bandwidth of the next tracking period based on the tracking state parameter of the code loop, and determining the bit loop bandwidth of the next tracking period based on the tracking state parameter of the bit loop, so as to realize the combined tracking of the carrier loop, the code loop and the bit loop on the input measurement and control signal. According to the invention, high-precision robust tracking of the measurement and control signal in a high-dynamic and low-signal-to-noise-ratio environment can be realized.

Embodiments of the present disclosure relate to sensor devices and related methods and systems. A sensor includes a detection circuit device and a control circuit device coupled to the detection circuit device. The detection circuit device generates a detection signal indicative of a detected physical quantity. In operation, the control circuit device receives the detection signal and a frequency indication signal and generates a trigger signal based on the frequency indication signal and a set of local reference signals. The sensor generates a digital output signal and a lock signal based on the trigger signal and the detection signal. Generating the digital output signal includes outputting a sample of the digital output signal based on the trigger signal. The lock signal is temporally aligned with the digital output signal.

An embodiment includes a forward data receiving device that demodulates and receives an Amplitude Shift Keying (ASK) modulation signal, and includes: an input module configured to receive the ASK modulation signal as an input; a resonance regulating rectifier module configured to regulate and rectify an input voltage of the ASK modulation signal on the basis of Pulse Width Modulation (PWM) according to a preset target voltage, and apply a regulated voltage through an output transistor; and a demodulation module configured to demodulate the ASK modulation signal according to a trend in a change of the input voltage compared to the regulated voltage, wherein the resonance regulating rectifier module includes a comparison unit configured to generate a gate signal for controlling on / off of the output transistor, and generate a sample signal for demodulating the ASK modulation signal.

A network device includes control logic coupled to a receiver. The control logic detects an synchronization packet received via the receiver from a second network device over a network that is precision time protocol unaware. The control logic determines that a portion of the synchronization packet is asserted, indicating that the synchronization packet has incurred congestion traversing the network. The control logic adjusts, based on an assertion of the portion, a weight applied to timestamps associated with sending and receiving the synchronization packet in performing clock synchronization with the second network device.

The present invention relates to a composite differential frame synchronization algorithm for burst communication under high dynamic conditions. The algorithm comprises the following steps: Step 1: differentially processing the received signal. In high dynamic scenarios, differential processing is required to reduce the influence of frequency deviation and obtain a differential sequence; Step 2: processing multiple groups of differential sequences in parallel, repeating Step 1, wherein each differential process differs in that the delay period of the differential is different, i.e., obtaining multiple groups of differential sequences with different delay periods; then sliding the phase of each group of differential sequences, and using the maximum value as the cross-correlation value of the differential sequence after passing through a filter, etc. The method of the present invention has the following advantages: it is easy to implement in hardware, has low complexity, can quickly obtain frame synchronization results, and can then quickly demodulate the signal to obtain information. It is suitable for burst signals, has real-time performance, and has wide application value in military battlefields.

A method of reducing the effects of variation in latency in data transfer between clock domains of a physical layer transceiver, the physical layer transceiver comprising physical coding sublayer circuitry having a first clock in a first clock domain and physical medium attachment circuitry having a second clock in a second clock domain, comprising: during initial training of the link, determining a transmit latency value in a transmission direction from the first clock domain to the second clock domain; during initial training of the link, separately from determining the transmit latency value, determining a receive latency value in a reception direction from the second clock domain to the first clock domain; and using the transmit latency value and the receive latency value to calculate latency in data transfer between the first clock domain and the second clock domain after the initial training until a subsequent training.

An example device (102) includes a feed forward equalizer (FFE) (122) having an FFE output, a summer circuit (124) having a first summer input, a second summer input, and a first summer output, the first summer input coupled to the FFE output, a multiplexer (MUX) (126) having a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first summer output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) (130) having a DFE output coupled to the second summer input, and a timing error detector (TED) (136) having a first TED input coupled to the MUX output.

An electronic device includes a first electronic device and a second electronic device configured to transmit and receive signals based on a C-PHY protocol. The second electronic device includes a calibrator configured to receive recovered data via a data path used to receive real data and provide a calibration value; and a clock recoverer configured to recover a clock signal (CLK) using the calibration value.

Example embodiments of the present disclosure relate to methods, devices, apparatuses and a computer readable storage medium for communication. In some embodiments, a first secured frame to be transmitted in a slot in a first round belonging to a first block based on a block-based time structure or a hyper block-based time structure may be generated, where the block-based time structure or the hyper block-based time structure comprises a plurality of blocks, each block of the plurality of blocks comprises a plurality of rounds, each round of the plurality of rounds comprises a plurality of slots, the first secured frame is secured by a first nonce being constructed based on identifying information associated with the first secured frame, a round index and a block index, the round index is an index of the first round, and the block index is an index of the first block. As such, the security operation may be performed and the communication can be guaranteed to be secured.

A receiver and a related signal processing method are disclosed. The receiver includes a filter, a signal detection circuit, and a synchronization processing circuit. The filter is configured to perform a filtering operation on a filter input signal to generate a filter output signal. The signal detection circuit is configured to determine whether the filter input signal or the filter output signal includes an interference signal based on the filter input signal and the filter output signal to generate an interference signal indicator, and determine whether the filter output signal includes a valid signal based on the interference signal indicator when the interference signal indicator indicates that the filter input signal or the filter output signal includes the interference signal to generate a valid signal indicator. The synchronization processing circuit is configured to process the filter output signal based on the interference signal indicator and the valid signal indicator.

The embodiment of the invention relates to a baud rate detection method and device, equipment and a storage medium. The method comprises the following steps: receiving interval section signals, recording interval transmission duration, and obtaining a preliminary baud rate according to the interval transmission duration; under the condition that the preliminary baud rate has the adjacent baud rate, setting a sampling baud rate matched with the preliminary baud rate; receiving a synchronous section signal, and sampling the synchronous section signal according to the sampling baud rate to obtain synchronous sampling data; and determining a target baud rate in the preliminary baud rate and the adjacent baud rate according to the synchronous sampling data. According to the technical scheme provided by the embodiment of the invention, high-precision Baud rate detection is realized without a high-frequency timer, the number of Baud rates which can be compatible with a self-adaptive Baud rate communication system is increased, and the operation resources and hardware cost of the system are saved.

This invention discloses a method, apparatus, system, and device for synchronizing feature information of power communication signal frames, belonging to the field of communication technology. The method includes: responding to a frame synchronization start signal of the current signal frame, triggering the calculation of corresponding feature information, and writing the feature information into a baseband buffer; after frame synchronization is completed, moving the feature information from the baseband buffer to a shadow register for subsequent reading by the processing module; while the data of the current signal frame stored in the memory module has not yet been read by the processing module, if a frame synchronization completion signal of the next signal frame is detected, updating the feature information stored in the shadow register according to a synchronization strategy. This invention effectively improves the accuracy of feature information synchronization and system stability by introducing a shadow register and combining it with a feature information retention mechanism based on a synchronization strategy.

The invention provides a receiving apparatus and a power management method thereof. The receiving device includes a receiving circuit disposed in a physical region and a controller disposed in a logical region. The reception circuit generates data based on the differential signal received from the transmitter, and transmits the data to the logic region. The controller determines an operating mode based on the data, generates an operating control signal based on the operating mode, and transmits the generated operating control signal to the receiving circuit.

The application provides a terahertz ISAC system design method based on delay alignment modulation and active RIS, and the steps are as follows: firstly, an active RIS assisted terahertz communication and sensing integrated (ISAC) system is built, and the signal received by the user and the signal signal-to-noise ratio of the terahertz ISAC system are calculated; secondly, the non-coherent accumulation is used to calculate the illumination power at the static target, and the received thermal noise at the static target and the power consumed by the active RIS are calculated based on the active RIS; finally, the reflection coefficient of the active RIS and the transmission beam forming vector at the DFBS are jointly designed to maximize the illumination power of the target, and the semi-definite program relaxation technology is used for solving. The application optimizes the transmission beam forming vector of the DFBS and the reflection coefficient of the active RIS, improves the sensing performance and guarantees the communication quality; the terahertz ISAC system utilizes the unique advantages of RIS and DAM, and provides incomparable benefits in the aspects of sensing and communication performance.

The invention discloses a feature information synchronization method, device, system and equipment of an electric power communication signal frame, and belongs to the technical field of communication. The method comprises the following steps: in response to a frame synchronization starting signal of a current signal frame, triggering calculation of corresponding feature information, and writing the feature information into a baseband cache; after frame synchronization is completed, the feature information is moved from a baseband cache to a shadow register for subsequent reading of a processing module; and when the data stored in the memory module by the current signal frame is not read by the processing module, if a frame synchronization completion signal of the next signal frame is detected, updating the feature information stored in the shadow register according to a synchronization strategy. According to the method, the shadow register is introduced, and a feature information retention mechanism based on a synchronization strategy is combined, so that the accuracy of feature information synchronization and the system stability are effectively improved.

Method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter,

The RAKE receiver signal synchronization detection method provided in the application comprises the following steps: sorting each correlation value in an initial correlation value set by a RAKE receiver to obtain a final correlation peak position set, selecting a first group of correlation value positions from the final correlation peak position set as a first correlation value position set, and selecting a second group of correlation value positions from the final correlation peak position set as a second correlation value position set; determining the initial position of each correlation value in the second correlation value position set, and selecting the associated position of each correlation value position to be detected based on the initial position to obtain an associated position set of each correlation value position; comparing the associated positions in each associated position set with the final correlation peak positions in the first correlation value position set to determine the number of paths; determining a synchronization detection position based on the number of paths, and processing the received signal based on the synchronization detection position. The synchronization performance under a low signal-to-noise ratio is improved.

A bidirectional communication system includes a signal transmitting and receiving device and a signal transmitting and receiving device that perform bidirectional communication via a transmission path. The signal transmitting and receiving device includes a driver, a filter, a receiver, and a controller. The receiver recovers a clock signal by performing frequency locking on a training pattern signal output through the filter, and outputs a recovered clock to the controller. The controller receives the recovered clock output from the receiver, controls a cutoff frequency of the filter, and controls an operation of the driver based on a frequency information of the recovered clock signal.

The application provides a serial transceiver-based data transmission method, a transceiver, a medium and equipment, and the method comprises the following steps: a serial transceiver switches clock frequency in the process of transmitting frame data, sends clock frequency switching information to a sending end parallel-serial conversion unit, and repeatedly writes current frame data into a sending data buffer; the sending end parallel-serial conversion unit reads parallel valid data of a preset bit number in the current frame data, counts the read bit number through a counter, and after receiving the clock frequency switching information, judges whether the count value is equal to the preset bit number value; if yes, it is determined that the parallel valid data is serialized, and serial data is obtained; the receiving end serial-parallel conversion unit converts the serial data into parallel data, and after detecting a frame header in the parallel data, it is determined that the frame header is in the aligned frame data, and the frame data is written into a receiving data buffer. The application realizes switching of data transmission rate of the serial transceiver in the data transmission process.

The invention discloses a signal sending and receiving method based on an overturning type synchronization sequence, and belongs to the field of electric power communication. In the sending method, a to-be-transmitted sequence is converted into a data symbol set; copying the polarity flipping type synchronization sequence into multiple copies, performing polarity flipping, and inserting the polarity flipping type synchronization sequence into different positions of the data symbol set according to a fixed interval; and performing shaping filtering and up-conversion on the framed signal to obtain a transmitted waveform signal. The receiving method comprises the following steps: performing down-conversion and matched filtering on a signal to obtain a received signal; frame synchronization is carried out on the received signals, and frequency offset compensation and channel equalization are completed; then executing demultiplexing to obtain a data symbol set; and performing de-mapping to obtain a transmission sequence. According to the method, the accuracy of frame synchronization, frequency offset compensation and channel equalization can be effectively improved, the bit error rate performance is improved, and the link deterioration resistance of a power wireless private network communication system is enhanced.

A phase detecting device according to some example embodiments includes: an analog front end for receiving a data signal and amplifying the data signal to generate an amplified signal; an analog-to-digital converter for sampling the amplified signal based on clock signals, and generating digital data signals; and a Mueller-Mueller phase detector for receiving the digital data signals from the analog-to-digital converter, and driving at least one operator from among operators based on transition between two continuously received digital data signals from among the digital data signals.

The invention discloses a communication system, a communication method, a host computer, a slave computer and a device with master-slave communication, the communication system comprises the host computer and at least one slave computer, and the host computer is in communication connection with the at least one slave computer for data interaction; the host sends host data, the data frame format of the host data comprises a frame type selection bit, the value of the frame type selection bit represents a target state machine of a target slave selected by the host, and the target slave is a slave which performs data interaction with the host in the at least one slave. According to the communication system and method, the data processing amount of the target slave can be reduced, and the data processing efficiency of the slave is improved.