64results about "Synchronisation receivers" patented technology

Some embodiments relate to a communication network comprising at least one receiver system optically coupled to a plurality of transmitter systems for transmission of synchronization signals generated by the at least one receiver system to the plurality of transmitter systems over a unidirectional synchronization channel. The at least one receiver system configured to embed into the synchronization signals thereby generated additional data indicative of an internal time count thereof for synchronization of transmission of data / signals from each one of the plurality of transmitter systems to said at least one receiver system over a sparse data / signals unidirectional communication channel.

A method includes that a first secured frame to be transmitted in a slot in a first round belonging to a first block based on a block-based time structure or a hyper block-based time structure may be generated, where the block-based time structure or the hyper block-based time structure comprises a plurality of blocks, each block of the plurality of blocks comprises a plurality of rounds, each round of the plurality of rounds comprises a plurality of slots, the first secured frame is secured by a first nonce being constructed based on identifying information associated with the first secured frame, a round index and a block index, the round index is an index of the first round, and the block index is an index of the first block.

The invention provides a loop parameter adaptive measurement and control signal tracking method and device, and belongs to the technical field of measurement and control, and the method comprises the steps: obtaining the tracking state parameters of a carrier ring, a code ring and a bit ring in a current tracking period; determining a bandwidth adjustment direction of the carrier ring and a bandwidth adjustment rate of the carrier ring based on the tracking state parameter of the carrier ring and the tracking state parameter of the bit ring; determining the carrier ring bandwidth of the next tracking period based on the bandwidth adjustment direction and the bandwidth adjustment rate; and determining the code loop bandwidth of the next tracking period based on the tracking state parameter of the code loop, and determining the bit loop bandwidth of the next tracking period based on the tracking state parameter of the bit loop, so as to realize the combined tracking of the carrier loop, the code loop and the bit loop on the input measurement and control signal. According to the invention, high-precision robust tracking of the measurement and control signal in a high-dynamic and low-signal-to-noise-ratio environment can be realized.

A network device includes control logic coupled to a receiver. The control logic detects an synchronization packet received via the receiver from a second network device over a network that is precision time protocol unaware. The control logic determines that a portion of the synchronization packet is asserted, indicating that the synchronization packet has incurred congestion traversing the network. The control logic adjusts, based on an assertion of the portion, a weight applied to timestamps associated with sending and receiving the synchronization packet in performing clock synchronization with the second network device.

A method of reducing the effects of variation in latency in data transfer between clock domains of a physical layer transceiver, the physical layer transceiver comprising physical coding sublayer circuitry having a first clock in a first clock domain and physical medium attachment circuitry having a second clock in a second clock domain, comprising: during initial training of the link, determining a transmit latency value in a transmission direction from the first clock domain to the second clock domain; during initial training of the link, separately from determining the transmit latency value, determining a receive latency value in a reception direction from the second clock domain to the first clock domain; and using the transmit latency value and the receive latency value to calculate latency in data transfer between the first clock domain and the second clock domain after the initial training until a subsequent training.

An example device (102) includes a feed forward equalizer (FFE) (122) having an FFE output, a summer circuit (124) having a first summer input, a second summer input, and a first summer output, the first summer input coupled to the FFE output, a multiplexer (MUX) (126) having a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first summer output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) (130) having a DFE output coupled to the second summer input, and a timing error detector (TED) (136) having a first TED input coupled to the MUX output.

An electronic device includes a first electronic device and a second electronic device configured to transmit and receive signals based on a C-PHY protocol. The second electronic device includes a calibrator configured to receive recovered data via a data path used to receive real data and provide a calibration value; and a clock recoverer configured to recover a clock signal (CLK) using the calibration value.

Example embodiments of the present disclosure relate to methods, devices, apparatuses and a computer readable storage medium for communication. In some embodiments, a first secured frame to be transmitted in a slot in a first round belonging to a first block based on a block-based time structure or a hyper block-based time structure may be generated, where the block-based time structure or the hyper block-based time structure comprises a plurality of blocks, each block of the plurality of blocks comprises a plurality of rounds, each round of the plurality of rounds comprises a plurality of slots, the first secured frame is secured by a first nonce being constructed based on identifying information associated with the first secured frame, a round index and a block index, the round index is an index of the first round, and the block index is an index of the first block. As such, the security operation may be performed and the communication can be guaranteed to be secured.

A receiver and a related signal processing method are disclosed. The receiver includes a filter, a signal detection circuit, and a synchronization processing circuit. The filter is configured to perform a filtering operation on a filter input signal to generate a filter output signal. The signal detection circuit is configured to determine whether the filter input signal or the filter output signal includes an interference signal based on the filter input signal and the filter output signal to generate an interference signal indicator, and determine whether the filter output signal includes a valid signal based on the interference signal indicator when the interference signal indicator indicates that the filter input signal or the filter output signal includes the interference signal to generate a valid signal indicator. The synchronization processing circuit is configured to process the filter output signal based on the interference signal indicator and the valid signal indicator.

The application provides a terahertz ISAC system design method based on delay alignment modulation and active RIS, and the steps are as follows: firstly, an active RIS assisted terahertz communication and sensing integrated (ISAC) system is built, and the signal received by the user and the signal signal-to-noise ratio of the terahertz ISAC system are calculated; secondly, the non-coherent accumulation is used to calculate the illumination power at the static target, and the received thermal noise at the static target and the power consumed by the active RIS are calculated based on the active RIS; finally, the reflection coefficient of the active RIS and the transmission beam forming vector at the DFBS are jointly designed to maximize the illumination power of the target, and the semi-definite program relaxation technology is used for solving. The application optimizes the transmission beam forming vector of the DFBS and the reflection coefficient of the active RIS, improves the sensing performance and guarantees the communication quality; the terahertz ISAC system utilizes the unique advantages of RIS and DAM, and provides incomparable benefits in the aspects of sensing and communication performance.

Method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter,

A bidirectional communication system includes a signal transmitting and receiving device and a signal transmitting and receiving device that perform bidirectional communication via a transmission path. The signal transmitting and receiving device includes a driver, a filter, a receiver, and a controller. The receiver recovers a clock signal by performing frequency locking on a training pattern signal output through the filter, and outputs a recovered clock to the controller. The controller receives the recovered clock output from the receiver, controls a cutoff frequency of the filter, and controls an operation of the driver based on a frequency information of the recovered clock signal.

The application provides a serial transceiver-based data transmission method, a transceiver, a medium and equipment, and the method comprises the following steps: a serial transceiver switches clock frequency in the process of transmitting frame data, sends clock frequency switching information to a sending end parallel-serial conversion unit, and repeatedly writes current frame data into a sending data buffer; the sending end parallel-serial conversion unit reads parallel valid data of a preset bit number in the current frame data, counts the read bit number through a counter, and after receiving the clock frequency switching information, judges whether the count value is equal to the preset bit number value; if yes, it is determined that the parallel valid data is serialized, and serial data is obtained; the receiving end serial-parallel conversion unit converts the serial data into parallel data, and after detecting a frame header in the parallel data, it is determined that the frame header is in the aligned frame data, and the frame data is written into a receiving data buffer. The application realizes switching of data transmission rate of the serial transceiver in the data transmission process.

A phase detecting device according to some example embodiments includes: an analog front end for receiving a data signal and amplifying the data signal to generate an amplified signal; an analog-to-digital converter for sampling the amplified signal based on clock signals, and generating digital data signals; and a Mueller-Mueller phase detector for receiving the digital data signals from the analog-to-digital converter, and driving at least one operator from among operators based on transition between two continuously received digital data signals from among the digital data signals.

The invention discloses a communication system, a communication method, a host computer, a slave computer and a device with master-slave communication, the communication system comprises the host computer and at least one slave computer, and the host computer is in communication connection with the at least one slave computer for data interaction; the host sends host data, the data frame format of the host data comprises a frame type selection bit, the value of the frame type selection bit represents a target state machine of a target slave selected by the host, and the target slave is a slave which performs data interaction with the host in the at least one slave. According to the communication system and method, the data processing amount of the target slave can be reduced, and the data processing efficiency of the slave is improved.

Some methods for triggering cameras in an autonomous vehicle (AV). The methods include receiving, by a programmable circuit, Generalized Precision Time Protocol (gPTP) information for synchronizing the programmable circuit with a gPTP Grand Master (GM); generating, by the programmable circuit, a pulse per second (PPS) signal having a peri-od of one second based on the gPTP time information; generating, by the programmable circuit, a synchronizing signal having a period less than the period of the PPS signal; generating, by the programmable circuit, a triggering signal based on the PPS signal, wherein a period of the triggering signal is the same as the period of the synchronizing signal; and sending, by the programmable circuit and to one or more cameras of an AV, the triggering signal for triggering the one or more cameras to capture one or more images. Systems and computer program products are also provided.

The invention provides a permanent magnet synchronous motor high-speed position acquisition system based on an FPGA and an SSI. The technical problem that the control requirement of a high-speed permanent magnet synchronous motor cannot be met is solved. Comprising a DSP which provides a reference clock, a control signal, an address bus and a data bus communicating with an FPGA through an XINTF interface; the FPGA is communicated with the DSP, forms a clock interface and a data interface which are communicated with the absolute value encoder, and provides a data transmission process between a system clock and the DSP and an acquisition and processing process of position data of the absolute value encoder; the differential signal transceiver forms a differential transmission channel between the FPGA and the absolute value encoder, outputs a system clock and receives a serial signal; and the absolute value encoder is used for collecting position information of the permanent magnet synchronous motor rotor and outputting a position signal through an SSI interface. And parallel processing of data acquisition and transmission based on clock synchronization is realized. And the control requirement of the high-speed permanent magnet synchronous motor is met.

A first device communicating with a second device through a high-speed serial interface includes an interface controller configured to recover data received via the high-speed serial interface and a component configured to perform a selected operation based on the recovered data, the interface controller including a recovered clock domain circuit configured to operate based on a recovered clock corresponding to a data transmission rate of the high-speed serial interface and a local clock domain circuit configured to operate based on a local clock having a frequency adaptively controlled based on a frequency of the recovered clock.

Examples of a receiver, a controller unit (e.g., for a receiver), and related methods (e.g., for a receiver) are provided. A receiver is provided that includes a tunable sample provider configured to provide samples of an input signal using tunable sample timing, a feedback path configured to provide a feedback signal to the tunable sample provider based on a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the tunable sample provider, and a replacement value provider configured to provide replacement sample timing information that replaces the sample timing information provided by the feedback path when the input signal does not satisfy predetermined requirements for feedback-based sample timing adjustment, wherein the replacement value provider is configured to provide the replacement sample timing information taking into account timing error information or a quantity derived from the timing error information over a longer period of time than a period of time taken into account by the loop filter for providing the sample timing information.

Exemplary embodiments of this disclosure relate to methods, apparatus, devices, and computer-readable storage media for communication. In some embodiments, a first protective frame to be transmitted in a slot within a first round belonging to a first block may be generated based on a block-based time structure or a hyperblock-based time structure, wherein the block-based time structure or the hyperblock-based time structure comprises a plurality of blocks, each block comprising a plurality of rounds, and each round comprising a plurality of slots, and the first protective frame is protected by a first nonce comprising identification information, a round index, and a block index associated with the first protective frame, wherein the round index is the index of the first round, and the block index is the index of the first block. In this way, security operations can be performed and the security of the communication can be ensured.

An integrated circuit with an interface circuit is described. During operation, the interface circuit may receive signals corresponding to a header of a frame that is compatible with a serial communication protocol, where the received signals include a temporal pattern of binary bits with instances of a dominant signal level and a recessive signal level. Then, the interface circuit may compute a set of conditions based at least in part on the receive signals, where, when valid, the set of conditions identify a first dominant bit in the binary bits having the dominant signal level. Moreover, when the set of conditions are valid, the interface circuit may: determine a location of synchronization field in the header relative to the identified first dominant bit; and calculate a baud rate of the receive signals based at least in part on a subset of the binary bits in the synchronization field.

The invention relates to the technical field of wireless communication, and discloses a simplified AGC-based frame synchronization method for a wireless communication receiver of a satellite portable station, which is characterized by comprising the following steps of: receiving a signal and separating an IQ component, simplifying AGC processing, preprocessing the signal, performing differential processing and simplifying correlation operation, and judging a peak value and completing frame synchronization. A feed-forward AGC structure is adopted, detection calculation is simplified through Taylor expansion first-order approximation, frequency offset and phase offset influences are eliminated through differential processing, correlation operation is simplified, a preprocessing mode of normalization processing or self-adaptive threshold adjustment is matched, efficient frame synchronization of a wireless communication receiver is achieved, system operation complexity and hardware resource consumption are reduced, and the system performance is improved. And the frame synchronization real-time performance and stability are improved.

A clock drift indicating an internal clock in a sensor device is provided. A method for indicating a clock drift of an internal clock comprised in a sensor device, the method comprising: capturing (S302), by the sensor device, a first data frame; associating (S304), by the sensor device, the first data frame with a first point in time indicating a point in time of the internal clock when the first data frame is captured; receiving (S306), by the sensor device, time synchronization data via a network protocol for clock synchronization; determining (S308), by the sensor device, a reference time point using the time synchronization data, the reference time point indicating a time point of the reference clock when the first data frame is captured; determining (S310), by the sensor device, an offset between the first point in time and a reference point in time; and associating, by the sensor device, the first data frame with data indicative of the offset when the offset exceeds a threshold offset (S312).

Some methods for triggering a camera in an autonomous vehicle (AV). These methods include receiving, with a programmable circuit, universal precision time protocol (gPTP) information, the gPTP information for synchronizing the programmable circuit with a gPTP master clock (GM); generating, with a programmable circuit, a pulse per second (PPS) signal having a period of one second based on the gPTP time information; generating, using a programmable circuit, a synchronization signal having a period smaller than that of the PPS signal; generating, using a programmable circuit, a trigger signal based on the PPS signal, in which the cycle of the trigger signal is the same as the cycle of the synchronization signal; and transmitting, with the programmable circuit, a trigger signal to one or more cameras of the AV for triggering the one or more cameras to capture the one or more images. A system and a computer program product are also provided.

The application belongs to the technical field of communication and particularly relates to a partial matching filter signal acquisition method based on time domain averaging. The method mainly sets M partial matching filters in a receiving end, simultaneously divides the received signals into M segments, inputs the signals into the M partial matching filters for partial matching filter processing, performs a difference operation on the obtained filter outputs, obtains a correlation peak value according to a time domain average length, and finally performs signal acquisition judgment by using the correlation peak value. The method has small calculation amount, simple realization, and can obtain certain gain at a small cost.

A method, system, and apparatus for digital clock and data recovery (CDR) with analog signal that samples blindly (i.e., independent of the baud rate). The CDR further has a digital monolithic circuit that includes an interpolator circuit, and a fully digital clock (FDC) that recovers the digital data from the analog signal.

The application provides a signal sampling time determination method, device and terminal equipment, and relates to the technical field of communication. The signal sampling time determination method comprises the following steps: obtaining a signal estimation error in a first sampling interval; the first sampling interval is an interval between a first signal sampling time and a second signal sampling time; obtaining a signal sampling error threshold of a second sampling interval according to the signal estimation error in the first sampling interval and a time length of the first sampling interval; determining a third signal sampling time according to the signal sampling error threshold of the second sampling interval and a first sampling signal sent at the second signal sampling time; the second sampling interval is an interval between the second signal sampling time and the third signal sampling time; and the second signal sampling time is located before the third signal sampling time. The signal sampling time obtained in the application is used for sending a sampling signal, which can reduce a signal estimation error obtained by terminal signal estimation and increase the accuracy of estimated signal state information.

A receiver includes: a PHY layer; and a processor coupled to the PHY layer. The processor is configured to: receive a set of data bits from the PHY layer; compare the set of data bits to a sync header pattern; determine a mismatch metric responsive to the comparison and to an adjustable scaling factor; and execute link synchronization operations based on the mismatch metric.

Systems and methods for synchronizing with and decoding radio frequency signals are provided. In one aspect, a radio receiver includes an antenna configured to receive a radio frequency signal and digital signal processing circuitry configured to receive the radio frequency signal from the antenna and perform a first synchronization algorithm and a second synchronization algorithm on the radio frequency signal in parallel. The digital signal processing circuitry is further configured to determine which of the first synchronization algorithm and the second synchronization algorithm completes first and begin playback on the radio frequency signal based on synchronization with the radio frequency signal based on the determination of which of the first synchronization algorithm and the second synchronization algorithm completed first.

A method and apparatus for transmitting a data signal, comprising receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting a clock signal by a first counter; transmitting a first select signal to a first select signal input of the transmitter multiplexer in response to the first counter counting a threshold number of clock cycles by the first counter; and alternately transmitting the digital data signal and the inverted digital data signal as a transmitter output signal to a receiver in response to the first select signal and by a first digital data signal output of the transmitter multiplexer, the receiver and the digital data signal output operably coupled to a data link.