37results about How to "Low timing requirements" patented technology

A multi-point probe particularly suitable for automated handling is disclosed. An automated multi-point measuring system including the multi-point probe and a probe manipulator head is also disclosed In addition, an automated multi-point probe gripping system including a probe holder and the probe manipulator head is revealed. Further, a loaded probe loader comprising a probe loader and a probe cassette for handling the multi-point probe is also revealed, where the probe cassette is provided with the probe holder for securing the multi-point probe.

The present invention relates to a two-level comparator circuit, belonging to the technical field of analog integrated circuits. The two-level comparator circuit comprises an input level and a latch level. The input level comprises a first N-channel metal oxide semiconductor (NMOS) transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), a first p-channel metal oxide semiconductor (PMOS) transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4). The latch level comprises a fourth NMOS transistor (MN4), a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), a ninth NMOS transistor (MN9), a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6), a seventh PMOS transistor (MP7) and an eighth PMOS transistor (MP8). Due to reset of a node X+ and a node X- in a latch level circuit, circuit maladjustment and noise are lowered. A pair of cross-coupling transistors MP1 and MP2 is added in the input level circuit, so that the comparator has the characteristic of working at a high-speed. The two-level comparator is applicable to system circuits of high accuracy.

The invention relates to the field of fiber sensing and circumference security and protection, in particular to a 3x3 coupler scheme-based all-fiber interference type circumference security and protection system. The 3x3 coupler scheme-based all-fiber interference type circumference security and protection system is characterized by comprising a multi-wavelength single-frequency laser emission unit (1), a light source protection unit (2), a wavelength multiplexing unit (3), a pulse modulation unit (4), a power amplifier (5), a power distributor (6), a space division sensing array (7), a preamplification unit (8), a wavelength demultiplexing unit (9), an interference matching unit (10), a photoelectric conversion and demodulation unit (11) and a display and control unit (12), wherein the space division sensing array (7) comprises a transmission optical cable (701) and wavelength division sensing arrays (702); each group of wavelength division sensing array (702) comprises multiple groups of wavelength delete multiplexers (7021), wavelength increase multiplexers (7022) and interferometers (7023); each interferometer (7023) corresponds to a single-frequency light source wavelength; the COM (cluster communication) ports of the wavelength delete multiplexers (7021) are input ports.

The present invention provides a parallel-serial conversion circuit. The circuit comprises a phase inverter and N dynamic triggers, wherein N is identical to the number of the bits of received parallel data; the output ends of the N dynamic triggers are connected with the input end of the phase inverter; the data receiving end of the n-th dynamic trigger receives n-th-bit data in the N-bit parallel data; the clock signal receiving end of the n-th dynamic trigger receives n-th clock signals; the clock periods of the clock signals are the same as the update period of the N-bit parallel data; the high eclectic level of the clock signals does not overlap; the circuit structure of each dynamic trigger does not include the phase inverter; and the value of n is a positive integer from 1 to N. The structure of the parallel-serial conversion circuit provided by the invention is simplified, time sequence requirements on paths are lowered, and an area occupied by the circuit is decreased.

The invention discloses a method for sharing a single program memory by a four-core processor system. The method that two-phase clocks are used and the method that memory addresses are separately piled according to odd serial numbers and even serial numbers are combined. Four processors of the four-core processor system are respectively a Core0, a Core1, a Core2 and a Core3, and memory access addresses, corresponding to the four processors, on an address bus are respectively addr0, addr1, addr2 and addr3, wherein the Core0 and the Core1 belong to a set A1 and are driven by the clock phi 1, the Core2 and the Core3 belong to a set A2 and are driven by the clock phi 2, the shared memory SMEM is driven by a clock HCLK, the phase of the clock phi 1 and the phase of the clock phi 2 are opposite, and the frequency of the clock phi 1 and the phase of the clock phi 2 are half the frequency of the clock HCLK. Because the phase of the clock phi 1 and the phase of the clock phi 2 are opposite, the two groups of Cores, namely the A1 and the A2, can independently access the memory without being mutually interrupted or generating accessing competition. The method for sharing the single program memory by the four-core processor system solves the problem of access competition generated when the memory is shared by the four-core processor system.

The invention discloses a parallel AltBOC navigation signal intermediate frequency generation method, comprising the steps of: generating I and Q paths of baseband orthogonal signals; utilizing complex filtering to perform amplitude-frequency distortion compensation on I and Q to generate cI and cQ paths of baseband orthogonal signals; performing low pass filtering on generated cI and cQ paths of baseband orthogonal signals; generating intermediate frequency carrier waves; parallelly modulating the intermediate frequency carrier waves and the cI and cQ paths of baseband orthogonal signals; and finally performing parallel-serial conversion to output intermediate frequency signals. The method can generate AltBOC signals with lower frequency, guarantee the channel feature consistency of the I and Q branches, and meanwhile guarantee signal quality.

The invention discloses a real-time protection method for single particles of a memory of satellite-borne software. The real-time protection method includes judging whether content in the memory is rewritten or not by comparing itself with the corresponding content in a program storage during idle time of operation of the satellite-borne software; if yes, rewriting correct codes into the memory form the program storage. By the real-time protection method, reliability and stability of in-orbit operation of satellite-borne software products are greatly improved, influences of single particle events during in-orbit operation are eliminated, and in-orbit operation requirements of memory operation based satellite-borne software products can be met, so that the real-time protection method has broad engineering application prospect and important engineering application value in the field of satellite-borne real-time embedded systems.

The invention discloses an estimation method and module for in-phase/ quadrature-phase (IQ) imbalance in an OFDM (Orthogonal Frequency Division Multiplexing) system. The estimation method comprises the following steps: S1, performing frequency offset compensation on received time domain signals; S2, after removing cyclic prefixes, transforming two different pilot symbols adjacent on time to a frequency domain; S3, extracting subcarriers occupied by the pilot symbols according to the system bandwidth; S4, for the two pilot symbols, obtaining received signals of two pilot signals on each subcarrier; and S5, removing coupling of IQ imbalance parameters and channels, and solving an IQ imbalance estimation value. The method and the module are wide in application and low in requirement for the processing time sequence of a receiver, conform to the demands of most practical application scenes, and are simple in algorithm and small in calculation quantity.

The embodiment of the invention provides a timestamp jitter compensation method and device, and the method comprises the steps: carrying out the clock synchronization of a timestamp sampling identification signal of a first system clock domain based on a 1588 clock, and obtaining a timestamp sampling identification signal of the 1588 clock domain; performing clock synchronization on the timestampsampling identification signal of the 1588 clock domain based on a system clock to obtain a timestamp sampling identification signal of a second system clock domain; and performing timestamp delay compensation according to the interval period between the timestamp sampling identification signal of the first system clock domain and the timestamp sampling identification signal of the second system clock domain. According to the timestamp jitter compensation method and device provided by the embodiment of the invention, errors caused by synchronization of timestamp sampling identification signalsof a system clock domain are amplified, and then discrimination compensation is carried out, so that the jitter of the timestamp is effectively compensated.

The present invention relates to a device and a method for measuring an axial polarizing angle of a polarizer. The apparatus can have a to-be-measured polarizer disposed therein, and comprises a light generating device, a light polarizing device and a measurement comparison device. The light generating device provides a light source. The light polarizing device is disposed corresponding to the light generating device to load the to-be-measured polarizer, and measures a light signal after the light source passes through the to-be-measured polarizer without rotating the to-be-measured polarizer, and transforms it into readable data. The measurement comparison device is electrically connected with the light polarizing device and has at least one preset comparison data to receive the data provided by the light polarizing device and compare it with the comparison data. Thus, after comparing the data provided by the light polarizing device with the comparison data, an axial polarizing angle of the to-be-measured polarizer is quickly and accurately measured and calculated.

The embodiment of the invention provides a shift register circuit, a driving method thereof and a display device, relates to the technical field of display, and aims to reduce the power consumption of the display device. The shift register circuit comprises a shift control circuit used for outputting a driving signal; the output control circuit is electrically connected between the shift control circuit and the driving signal line and is used for controlling a signal transmission path between the shift control circuit and the driving signal line to be communicated in a data frame; and in the holding frame, a signal transmission path between the shift control circuit and the driving signal line is controlled to be disconnected, and a disable voltage is output to the driving signal line.

The invention discloses a voltage interactive synchronous sampling method, and belongs to the electric power technology field. The method comprises the following step of measuring the channel time delay between a bus voltage local module and an interval voltage local module and the internal sampling time delay of the bus voltage local module, solves the technical problem that the high-voltage sidebus voltage HSR in-loop local module and the spaced HSR in-loop local modules at the middle-voltage side and the low-voltage side need the clock synchronization, and is simple in system architecture,less in HSR in-loop nodes, high in communication efficiency and low in clock synchronization requirement. The synchronization does not depend on an external reference clock source, and the reliability is high.