A time-interleaved pipeline ADC system and its timing operation method

Abstract

The invention discloses a time-interleaved assembly line ADC system and a sequential operation method thereof. The time-interleaved assembly line ADC system comprises a digital-analogue converter structure, a disturbance calibrating signal injection structure and a self-adaptive algorithm principle; under the relatively low system overhead, the digital-analogue converter structure can realize injection of disturbance signals and normalized capacitance parameter correction of various channels; sampling randomization is realized by using a redundancy sampling channel, such that the channel delay deviation is reduced to the noise background; compared with the traditional delay correction method, a lot of power consumption and area overheads can be saved; in combination with randomized sampling channel section, a dynamic reverse circuit in the traditional operational amplifier offset correction circuit is saved by using a non-fixed positive and negative signal polarity channel, such that time sequence requests are reduced; injection of gain correction disturbance signals is separated by using multiple correctable channels; compared with the traditional scheme, a front high-speed sample hold circuit having high power consumption is saved; and the sampling speed of the time-interleaved assembly line ADC system is increased.

Description

technical field [0001] The invention relates to a time-interleaving pipeline ADC system and a timing operation method thereof. Background technique [0002] Due to the processing speed limitation of single-channel pipeline ADC system, time-interleaving structure splicing is often used when realizing high-speed pipeline ADC. The time-interleaved pipeline ADC structure can reduce the speed requirement of the original single-channel ADC by N times, and N is the number of single-channel pipeline ADCs spliced ​​in the system. Although the time-interleaving structure greatly expands the sampling speed of the ADC system, various matching errors between single-channel ADCs limit the performance improvement of the time-interleaving ADC system. [0003] With the advancement of integrated circuit technology, digital adaptive correction technology (LMS for short) is widely used to solve various deviation problems of ADC. A time-interleaved pipeline ADC system generally involves three ...

AI Technical Summary

Problems solved by technology

For example, it is necessary to design a special full-speed sample-and-hold circuit to uniformly inject gain correction or offset correction disturbance signals, making the sample-and-hold circuit a system bottleneck and consuming a lot of power consumption; it is necessary to design a high-cost fractional digital delay circuit to correct the delay between channels deviation

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