A kind of sram timing control circuit with word line voltage boosting technology of duplication unit
A technology of timing control circuit and duplication unit, applied in digital memory information, information storage, static memory and other directions, can solve the problems of inability to better improve process deviation, increase of multiplying circuit area, delay quantization error, etc., and achieve optimal performance. Ability to resist process variation, reduce delay deviation, and improve the effect of deviation
Active Publication Date: 2018-02-06
ANHUI UNIVERSITY
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Problems solved by technology
[0004] In order to obtain optimal timing control, a timing replication bit line technology was proposed in 1998. Compared with the inverter chain delay technology, this technology has better resistance to process deviation and can more accurately track the bit line discharge. With the advancement of process technology, this traditional copy bit line technology can no longer improve the process deviation with the reduction of power supply voltage.
[0005] Y.Niki et al. proposed a digital replication bit line delay technology in 2011. This technology greatly improves the timing deviation at low voltage by increasing the replication unit and combining the delay multiplication circuit, but The multiplication circuit will bring a large increase in area and delay quantization error
In 2014, Y. Li et al. proposed the double-copy bit line technology, which improved the 6-tube unit and made full use of the bit line resources, which improved the circuit’s ability to resist process deviation without increasing the area. However, due to The capacitance of the bit line becomes larger, which increases the precharging time of the bit line and reduces the working speed of the chip.
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[0034] figure 1 A timing control circuit for an SRAM with the word line voltage boosting technique for replicating cells provided for an embodiment of the present invention, such as figure 1 As shown, it mainly includes: timing replication circuit module and replication cell word line voltage boosting module; where:
[0035] The timing replication circuit module is connected in parallel between the replication unit word line and the replication bit line, and is used to replicate the discharge time of the storage array, which includes n serially connected replica cells (RC) and several serially connected redundant cells (DC) ; There are two copy bit lines, such as figure 1 Replica BL and Replica BLB in the replication unit; wherein, both ends of all the replication units are connected to the replication bit lines Replica BL and Replica BLB respectively, and the control terminals of all the replication units are connected to the replication unit word line (RWL); Both ends of t...
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The invention discloses a SRAM replicating bit line circuit, comprising: a timing replicating circuit module and a replicating unit word line voltage raising module; wherein: the timing replicating circuit module is connected in parallel between the replicating unit word line and the replicating bit line; One end of the copy unit word line voltage boost module is connected to the clock signal terminal, and the other end is connected to the copy unit word line, which is used to process the input clock signal into a high voltage level signal and transmit it to the copy unit word line; The greater the voltage of the cell word line, the greater the discharge cell current and its deviation, so that the delay deviation of the timing control circuit is smaller. The circuit provided by the invention not only has good process deviation resistance under low power supply voltage, but also does not greatly increase the area of the chip and does not affect the running speed of the chip.
Description
technical field [0001] The invention relates to the technical field of integrated circuit (IC) design, in particular to an SRAM timing control circuit with word line voltage raising technology for replicating cells. Background technique [0002] In modern society, due to the rapid development of mobile communication technology, 3D technology, GPS navigation technology and high-speed wireless network technology, IC design is driven to pursue faster speed, higher stability and lower power consumption. SRAM (Static Random Access Memory) occupies the main area of on-chip memory because of its high speed, low power consumption and high robustness, so the performance of SRAM seriously affects the function of SoC chip. [0003] At this stage, the power consumption is mainly reduced by reducing the operating voltage of the SRAM, because for the SRAM, the power consumption is linearly related to the square of the low voltage of the power supply. However, as the power supply voltag...
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IPC IPC(8): G11C11/413
Inventor李正平尚凤仪谢明明李颂卢文娟周永亮彭春雨谭守标陈军宁
OwnerANHUI UNIVERSITY