Read operation control signal generator and its working method

Abstract

The invention discloses a read-operation control signal generator. The read-operation control signal generator comprises three delay circuits with same structures and different delay time setting; the input terminal of a first delay circuit is connected with internal clock signals, three delayed output signals are generated successively by the delay circuits because of rising edge trigger of external clock signals, and signal saeq is subjected to miteinander with nonsignals of second output signals and first output signals, and then is output via a noninverting amplifier; signal saen1 is output by a noninverting amplifie via first output signals; signal saen2 is output by a noninverting amplifie via third output signals; zero clearing of the three delay circuits can be realized via rising edge trigger of external clock signals, third output signals can be delaed by a fourth delay circuit, and zero clearing signals are lower by the fourth delay circuit so as to realize zero clearing of the three delay circuits. The invention also discloses an operation method of the read-operation control signal generator. The read-operation control signal generator is simple in circuit structure, and is capable of reducing delay skew, domain area, and circuit powder consumption.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a read operation control signal generator. The invention also relates to a working method of the read operation control signal generator. Background technique [0002] The function of the read operation control signal generator in the non-volatile memory (Non-Volatile Memory, NVM) is to use the rising edge trigger of aclk to generate the three signals required for the read operation when performing the read operation (read is high level). The control signal is a signal amplification equalization signal (Sense Amplifier Equiplirium, saeq), a signal amplification enable signal (Sense Amplifier Enable, saen) one is saen1, and a signal amplification enable signal two is saen2. Such as image 3 Shown is the timing waveform diagram of the above three control signals generated by the existing read operation control signal generator. During the read operatio...

AI Technical Summary

Problems solved by technology

A disadvantage of the existing delay circuit 2 is that the layout structure of the NMOS transistor MN104 and the NMOS transistor MN105 cannot be completely matched (match), that is, the NMOS transistor MN105 is also connected in series with the NMOS transistor MN106, so that the drains of the NMOS transistor MN104 and the NMOS transistor MN105 Pole voltages are not exactly the same

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