337 results about "Circuit diagram" patented technology

The invention discloses a circuit netlist generation method supporting deep learning model multi-stage reasoning, and belongs to the technical field of electronic circuit design and automation, and the method comprises the steps: obtaining a circuit diagram image through optical scanning, carrying out the preprocessing of the image, carrying out the recognition of a component through a deep learning model YOLOv5, and determining the boundary frame coordinates and class information. And further performing port fine identification on the component, and determining the position and the direction of the port. And eliminating character interference by using an optical character recognition technology, performing wire recognition, including Hough straight line detection and jumper processing, and determining starting point and ending point coordinates of the wire. And matching the identification results of the components, the ports and the wires, constructing a topological structure of a circuit diagram, finally generating a circuit netlist, and performing error elimination and JSON format output. According to the method, automatic netlist generation of the analog circuit diagram can be realized, the analog circuit diagram file is converted into the netlist file with device function annotations, and the efficiency and quality of circuit design and simulation are improved.

The present disclosure provides a method and device for calculating fault measurement impedance of a hybrid-connected grid-following and grid-forming wind power system. The method includes: obtaining characteristics of the grid-following and grid-forming converters and a corresponding low voltage ride-through control strategy; establishing an equivalent circuit under a corresponding fault state; conducting a simplified analysis on the wind power system to obtain an equivalent network diagram; obtaining a sub-circuit diagram of each power source excitation acting alone; obtaining short-circuit currents on both sides of the corresponding system and a grid connection point voltage; superimposing to obtain total short-circuit current on both sides of the wind power system and total grid connection point voltage; and obtaining a measurement impedance at a protection installation location on the new energy source side. The method can accurately calculate the measurement impedance value at the protection installation location after the wind power system has fault.

The invention relates to the technical field of PCB detection, and discloses an online defect detection method and system in the PCB production process and computer equipment, the detection accuracy can be improved by combining production parameters, image information and a design circuit diagram, potential defects can be found in the early stage, the PCB is divided into a plurality of areas, and the detection efficiency is improved. According to the PCB, each area can be independently welded and detected, the complexity of the whole PCB is reduced, the PCB is divided into a plurality of areas which are detected one by one, a specific defect area can be effectively positioned, through the regionalized detection and maintenance process, the unqualified area can be locally processed, the production efficiency is improved, and the production cost is reduced. By adopting the strategy based on multi-round detection, feedback and regional repair, through accurate positioning, local repair, detection efficiency improvement and automatic processing, the rejection rate of unqualified products is greatly reduced, the maintenance success rate is improved, and the problems of difficulty in PCB defect detection and resource waste in the prior art can be effectively solved.

The invention relates to the technical field of communication network fault diagnosis, and discloses a communication information processing method and device. The method comprises the steps that a voiceprint sensor collects an original signal, and a quantum coding time-frequency matrix is generated through time-frequency conversion and quantum coding; the matrix and real-time circuit diagram data are fused, and topology-fault joint features are generated through feature alignment and wavelet-convolution joint extraction; analyzing the features to reconstruct a node relation graph, and generating real-time updated circuit diagram data through graph optimization; loading an incremental parameter adapter initialization graph neural network based on the data, and executing fault propagation deduction to output fault coordinates and confidence data; generating an incremental parameter adapter according to confidence data federal optimization; and analyzing the fault coordinate matching topology library based on the adapter, and associating the maintenance knowledge base to output a visual repair suggestion. According to the method, fault dynamic deduction is realized, the cross-line generalization ability is enhanced by an incremental learning mechanism, bandwidth occupation is reduced by edge-cloud cooperation, and the fault positioning efficiency and accuracy are remarkably improved.

The invention belongs to the technical field of integrated circuit design automation, and discloses an anti-radiation standard unit automatic layout method, which adopts a two-stage reinforcement learning strategy: in the first stage, training a device layout strategy model, extracting MOS device information by analyzing a CDL file, and constructing a circuit diagram structure as state representation; generating a preliminary device layout result by using a dynamic action mask mechanism; and in the second stage, independently training the guard band insertion strategy model, and optimizing the guard band insertion position and sequence based on the candidate insertion point set so as to meet the anti-radiation design rule and reduce the wiring difficulty. The two stages both adopt a Maskable PPO algorithm, encourages gate alignment, source-drain proximity and shortest connection path through a reward function, and punishes layout conflicts and DRC violations. According to the invention, by means of the two-stage design of division of labor and cooperation, the layout efficiency and compliance of the anti-radiation standard unit are significantly improved, and the method has the characteristics of high efficiency, self-adaption and high engineering practicability.

The invention discloses a GIS circuit diagram intelligent generation method based on an electric power pipe arrangement engineering drawing, and relates to the technical field of electric power engineering design. The method comprises the steps of preprocessing multi-source data, planning a path and detecting conflicts, intelligently generating a dynamic layer and adaptively outputting in a cross-platform manner. The preprocessed multi-source data receives design parameters and multi-class data to generate a standardized data set; the path planning and conflict detection are combined with various conditions to generate constraints, and accurate parameters are output; the dynamic layer intelligent generation module is used for generating multiple types of layers according to the data, generating drawings and accounting the cost; in the cross-platform self-adaptive output step, graphs are displayed on multiple terminals based on a framework, and a multi-format export interface is provided. According to the method and the system, intelligent generation of the GIS circuit diagram of the electric power tube bank engineering drawing is realized, and the design efficiency and accuracy are improved.

The invention relates to the field of electronic design automation (EDA), and provides an AMS circuit automatic design method using a large language model. The method aims at solving the problem that an existing AMS circuit design is insufficient in automation degree, and mainly comprises the steps that a schematic circuit diagram and text description are extracted from literatures, and a data set containing the schematic circuit diagram, a netlist and annotation information is constructed; performing connectivity detection on the schematic circuit diagram, and extracting a netlist; carrying out annotation processing to obtain annotation information; constructing a knowledge graph for storing circuit information; obtaining a design strategy by using a large language model, and describing a circuit architecture; according to the design strategy and the local annotation, relevant circuits and test platforms are retrieved, a complete circuit topology is assembled, and simulation is carried out; size optimization is carried out based on constraints, and a Bayesian optimization algorithm is used for solving; and if the initial topological structure cannot meet the performance target, carrying out topological reconstruction. According to the invention, the automation level and efficiency of analog and mixed signal circuit design are improved.

The invention discloses an integrated circuit layout design teaching assistance method, and relates to the field of integrated circuits, and the method comprises the steps: receiving a circuit diagram creation instruction, and generating a circuit diagram drawing interface according to the circuit diagram creation instruction; identifying types and connection relations of circuit devices in the circuit diagram drawing interface; according to the identified circuit device type and the connection relation, generating a corresponding circuit schematic diagram data structure by adopting a graph neural network GNN algorithm based on message passing; converting the schematic circuit diagram data structure into a layout data structure; the layout data structure comprises geometric parameters and layout position data of layout elements; and according to the layout data structure, generating a circuit layout by using a reinforcement learning algorithm based on a graph neural network. In view of low integrated circuit layout design efficiency in the prior art, the design efficiency is improved by constructing a multi-objective optimized Markov decision process, utilizing deep learning and reinforcement learning algorithms and the like.

The invention relates to a circuit diagram-to-netlist generation method and system based on deep learning and a product. The circuit diagram-to-netlist generation method comprises the following steps: S1, identifying devices in a circuit diagram through a YOLOv8 model to obtain position information and category of each device; identifying a straight line segment in the circuit diagram through a probabilistic Hough transform algorithm to obtain a starting point coordinate, an end point coordinate and an orientation corresponding to the straight line segment; and S2, generating corresponding text description information according to the position information, the category, the starting point coordinate, the end point coordinate and the orientation. According to the method, by effectively integrating multi-modal information and combining image and text data, comprehensive understanding of a circuit diagram is provided, the recognition accuracy and robustness are improved, even if a single component has a recognition error, the influence of noise on the whole model can still be reduced through final information fusion, and the recognition accuracy and robustness are improved. Therefore, misjudgment and missed judgment in recognition are reduced, and the recognition accuracy of the element and the connection relation is remarkably improved.

The invention belongs to the technical field of analog switches, and particularly relates to a double-channel single-pole double-throw analog switch circuit which comprises two turn-off leakage compensation modules, two ISO isolation circuits, two turn-on leakage compensation modules, eight MOS tubes M5-M12 and a current source. All the devices are correspondingly connected according to a circuit diagram to form an analog switch circuit; the invention designs a dual-channel single-pole double-throw analog switch, a 0.25 [mu] m BCD process is adopted, two groups of completely consistent single-pole double-branch CMOS switches are arranged in a chip, the normal temperature interval is-40 DEG C to 125 DEG C, the analog switch can normally work under three power supply conditions of + / -15V, 12V, 0V and + / -5V, and the analog switch has the advantages of low on-resistance, high switching speed, high reliability and the like. And conduction electric leakage and turn-off electric leakage are small.

The invention discloses a method and device for automatically designing a gas path diagram. The method comprises the following steps: carrying out element identification on an input three-dimensional model to obtain the element type of each element in the three-dimensional model; based on the element type, selecting elements contained in an action group through interaction setting of a client, and configuring corresponding action instructions for the action group to obtain action group configuration data; performing legend matching on elements contained in the action group to obtain model element legend data; and carrying out legend feature recognition on the model element legend data, and carrying out legend connection and content labeling on the basis of a legend feature recognition result and the action group configuration data so as to generate a gas path diagram. The technical problems that an existing gas circuit diagram is low in design efficiency and prone to errors are solved.

The invention discloses a circuit diagram analysis method for automatically generating an analog circuit netlist, and the method comprises the steps: carrying out the recognition of an input to-be-processed circuit diagram through a target detection model, and outputting the type and position of each component in the circuit diagram; removing components from the circuit diagram to be processed to obtain a circuit diagram without components; a representative template picture of each component is called, the matching degree of the template picture and the identified component area is calculated, and the pin function and the position coordinate of each identified component are determined; identifying connecting line segments in the circuit diagram without components by adopting a connected domain detection method, and judging to obtain a really connected circuit network in the circuit diagram in combination with connecting points; and matching the pin ports of the components with the circuit network endpoints one by one, generating a netlist file of the circuit diagram to be processed, and checking and outputting the netlist file. According to the method, circuit schematic diagrams of different styles can be processed, and the accuracy of circuit netlist conversion is remarkably improved.

The invention provides a multi-agent cooperative positioning navigation method and device based on quantum computing, and relates to the technical field of quantum multi-agent systems. The method comprises the following steps: according to an initial position set and a speed space set, performing particle quantization by using a Hadamard gate to obtain a position superposition state set; according to the position superposition state set and the observation information set, position estimation is carried out through a quantum search algorithm, and a position estimation set of the cluster robot is obtained; according to the observation information set, performing quantum state coding by using a quantum coding circuit diagram to obtain a quantum state observation information set; based on the quantum variational circuit diagram, according to the quantum state observation information set, a quantum actor-commentator network is used for evaluation learning; and according to the data of the experience pool, parameter gradient optimization is carried out on the quantum actor-commentator network to obtain an optimized quantum actor-commentator network. The invention provides an efficient and accurate multi-agent cooperative positioning method based on quantum computing.

The invention provides an automatic layout method for electronic components of a circuit board, and the method comprises the steps: exporting functional modules in a schematic circuit diagram into an independent circuit netlist, carrying out the layout modeling of the components through employing a single-layer binary tree structure, and carrying out the layout modeling of the whole circuit based on a multi-layer binary tree structure. Therefore, a multi-layer nested binary tree structure is formed. An optimization algorithm is combined with a heuristic strategy, and circuit performance parameters such as wire length, layout area and signal integrity are used as optimization targets to carry out iterative optimization on the layout model. And automatically generating a detailed layout scheme of the circuit board according to the optimized layout model. Before layout, preprocessing of a schematic circuit diagram is carried out, after layout, verification of a layout scheme is carried out, and it is ensured that all design constraints are met. The circuit board design efficiency and quality can be remarkably improved, the workload of manual adjustment is reduced, the risk of design reworking is reduced, and the automatic design level is improved.

The invention provides a circuit identification method, system and device based on a topological island and a medium, and is applied to the technical field of power electronic electromagnetic transient simulation. The circuit identification method based on the topological island comprises the following steps: acquiring all hierarchical circuit diagrams in a graphical interface; determining a first topological island corresponding to the circuit simulation model according to a connection relationship among elements in all hierarchical circuit diagrams; according to the first topology island corresponding to the circuit simulation model, port node numbers of elements in the circuit diagrams of all levels are determined, and the port node numbers are used for determining a matrix in the circuit simulation model. According to the method, the connection relationship between the elements in the graphical interface circuit diagram is abstracted into a topological island, and the port node numbers of the elements in the circuit diagram are identified and marked, so that input data are provided for a circuit simulation model, and a required simulation result is obtained.

The invention provides an electrostatic discharge structure robustness evaluation method and device, and belongs to the technical field of semiconductors, and the method comprises the steps: carrying out the layer-by-layer removal of a chip, carrying out the circuit analysis of the obtained layout information, obtaining a schematic circuit diagram, carrying out the section dyeing processing according to the schematic circuit diagram, and obtaining the geometric information, and detecting the electrostatic discharge structure to obtain PN region distribution information, performing TCAD simulation by using the layout information, the geometric information and the PN region distribution information, and determining the robust performance of the electrostatic discharge structure of the chip according to the obtained electrical characteristic information. According to the electrostatic discharge structure robustness evaluation method and device provided by the invention, an electrostatic discharge structure robustness evaluation means based on structure extraction and TCAD simulation is provided, and a device design manufacturer does not need to provide a schematic circuit diagram and layout of the electrostatic discharge structure and does not need to provide process parameters; and the robustness evaluation efficiency of the ESD structure of the semiconductor device is effectively improved.

The invention discloses a high-precision circuit board and a preparation method thereof. The preparation method comprises the following steps: acquiring a preset circuit diagram; setting a plurality of conductive layer groups according to a preset circuit diagram; wherein the conductive layers which need to form the same blind hole or buried hole form a conductive layer group, and the adjacent conductive layers which do not need to form the blind hole or buried hole form a conductive layer group; each conductive layer group comprises a core plate; placing the conductive layers in a stacked manner, placing bonding layers between the core plates in the same group or between the core plates and the conductive layers, and placing auxiliary layers between different conductive layer groups; laminating the conductive layer, the bonding layer and the auxiliary layer which are stacked, and stripping the auxiliary layer after lamination so as to enable the conductive layer group to form a sub-board; drilling a hole in a preset position of the daughter board to form a through hole; the daughter boards are placed in a stacked mode, and bonding layers are placed between the adjacent daughter boards; and laminating the sub-board and the bonding layer which are stacked. By adopting the technical scheme, the problems of alignment and warping caused by an asymmetric structure due to respective pressing of the sub-boards can be solved.

The invention provides a circuit test point generation method and system. The method comprises the following steps: obtaining layout information and setting rules of a circuit; a circuit diagram is generated according to the layout information. Obtaining a plurality of center lines of a plurality of traces of the circuit diagram; a plurality of test points are provided on each of the center lines. Judging whether the test points of each center line conform to a setting rule or not, and removing one part of the test points which do not conform to the setting rule and reserving the other part of the test points which conform to the setting rule; arranging and combining the other part of the test points of each of the center lines according to a setting rule to generate a plurality of candidate circuit test point diagrams, and calculating the test point coverage rate of each of the candidate circuit test point diagrams; and determining the candidate circuit measuring point diagrams with the highest measuring point coverage rate as a target circuit measuring point diagram. Therefore, the setting coverage rate of the test points is improved.

The invention relates to the technical field of PCB preparation, in particular to a preparation method of a PCB for an AI server, and the method comprises the steps: drawing a schematic circuit diagram, generating a PCB layout diagram, and dividing a stacked structure and a plurality of temperature control regions; determining the position of a heat source, determining a heat dissipation mode of each temperature control area, generating a heat distribution model through simulation to plan a heat dissipation path, and determining a hole plan in combination with a PCB layout; calculating a heat dissipation characterization value to generate a heat dissipation evaluation value of each inner layer; determining a target layer, setting a protective layer for the target layer, and performing etching treatment on each inner layer; a test heat source is placed in a blind hole in the outer layer of one side of the PCB and makes contact with the bottom of the blind hole, the temperature value, corresponding to the blind hole, of the outer layer of the other side of the PCB is detected, and a heat dissipation efficiency value is generated based on the temperature value and the heat dissipation path; and judging whether to modify the PCB layout according to the heat dissipation efficiency value. According to the invention, the heat dissipation efficiency of the PCB is effectively improved, and meanwhile, the preparation accuracy of the PCB is improved.

The invention provides an intelligent design method of an analog circuit based on process and post-simulation optimization feedback, and belongs to the field of multi-objective optimization of circuit design. The method comprises three processes: a circuit diagram optimization process, a layout optimization process and a device process optimization process. In the circuit diagram optimization process, parameters of circuit components are optimized by using a GLAL-MOPSO algorithm; in the layout optimization process, on the basis of a GLAL-MOPSO algorithm, a decision variable grouping strategy is designed to cope with the optimization problem of large-scale variables in layout optimization; in order to increase the optimization range of the circuit design, a device process optimization process is added in the circuit optimization process. In the process optimization process, parameters of a device process are optimized by using a GLAL-MOPSO algorithm, and a circuit diagram and a layout can be optimized again on the basis of a result obtained in the device process optimization process. According to the method, automatic optimization iteration is carried out on analog circuit design and device process optimization, so that the time cost and the manual design cost are saved, and the circuit design efficiency is effectively improved.

The invention belongs to the technical field of new energy automobile teaching practical training equipment, and discloses a high-voltage safety practical training interaction system and method based on Arduino and Unity 3D, and a storage medium. The system comprises a modular vehicle unit, an interactive display module and a safety control module group, wherein a detection terminal of a vehicle high-voltage system circuit diagram is electrically connected with a real vehicle high-voltage connector; the interactive display module carries a Unity 3D platform and integrates a teaching mode selection module, a high-voltage operation module, a data simulation measurement module, a fault assessment module and the like; the safety control module group performs dual protection through a leakage protector and a physical safety lock. The practical training method comprises system detection, vehicle type authorization, safety verification, multi-mode operation and generation of a multi-dimensional scoring report containing a fault positioning thermodynamic diagram. Real-time synchronization of physical operation and virtual simulation is achieved through combination of software and hardware, the problems that an existing practical training device is disjointed from a virtual object, adaptation of multiple vehicle types is poor, safety protection is insufficient and the like are solved, and the system is suitable for vocational colleges, vehicle enterprise training centers and other scenes.

The invention belongs to the technical field of FPC circuit board manufacturing. The composite structure for manufacturing the FPC circuit board sequentially comprises a wiring base material layer, a thermal viscosity reduction adhesive film layer, a circuit diagram layer, a substrate adhesive film layer and a substrate base material layer from top to bottom, and the thermal viscosity reduction adhesive film layer and the substrate adhesive film layer are opposite in viscosity change along with temperature change. The composite structure used for manufacturing the FPC circuit board is subjected to transfer hot pressing, the circuit diagram layer is bonded with the substrate base material layer and is stripped from the wiring base material layer, and transfer of the circuit is completed; and covering the surface of the circuit pattern layer with a layer of covering film, and sealing the circuit through sealing and hot pressing to obtain the FPC circuit board. According to the technical scheme, circuit printing is carried out in a printing mode, no three wastes are discharged in the printing process, compared with the original industry, power consumption is greatly reduced, the usage amount of production materials, especially copper, is greatly reduced, and the raw material cost is greatly reduced.

The invention discloses an intelligent simulation method, system and device based on freehand circuit recognition, and relates to the technical field of electronic engineering and artificial intelligence. The method comprises the following steps: receiving hand-drawn circuit image data and preprocessing the hand-drawn circuit image data; detecting elements in the preprocessed hand-drawn circuit image by adopting a pre-constructed target detection model, and extracting to obtain a detection result; processing the detected hand-painted circuit image through a pre-constructed image processing module, and extracting to obtain communication regions and node information of each element; generating an SPICE netlist by using a large language model according to the image detection result and the communication region and node information of each element in the image; and inputting the SPICE netlist into an Ngspice simulation engine to carry out circuit simulation. According to the method, the improved YOLOv9t model and the DAG-ChiSynth algorithm are used for data generation and recognition, elements, topology and parameters can be automatically extracted from the hand-drawn circuit image of the student, end-to-end simulation is achieved, interactivity and efficiency in electronic education are remarkably improved, and teaching cost is reduced.

The invention discloses a method for generating an SPICE netlist by a circuit diagram driven by a multi-modal large model. The method comprises the following steps: completing construction from a circuit image to an SPICE netlist data set; supervising and finely tuning the circuit-to-netlist model; a step-by-step reasoning normal form in a track guiding reinforcement learning stage; a multi-level reward mechanism in the track guide reinforcement learning stage evaluates the performance of the circuit-to-netlist model from the aspects of reasoning quality, netlist generation accuracy and logic consistency; a reflection learning mechanism in a track-guided reinforcement learning stage; and carrying out overall optimization in a trajectory-guided reinforcement learning stage. According to the method, the precision of conversion from the circuit image to the SPICE netlist and the reasoning consistency can be improved by utilizing a track guide reinforcement learning normal form and integrating step-by-step reasoning, a multi-level reward mechanism and an inverse learning mechanism.

The present specification discloses a modeling simulation analysis method, device, storage medium and equipment for circuit diagrams. In this method, the target circuit diagram drawn by the user in the graphical interface can be converted into a form of graph data that does not depend on a specific simulation analysis program and stored as an intermediate representation, so that the topological structure between the electronic components in the target circuit diagram and the basic properties of the electronic components can be supported while the editing operation of the user in the graphical interface can be intuitively represented. At the same time, when simulation analysis is required, it can be converted into netlist data in different formats supported by different simulation analysis software, so as to facilitate flexible data exchange in different simulation analysis software and different functional modules, thereby effectively reducing the cost of simulation analysis.

The invention discloses a schematic circuit diagram generation method and system based on an action mask and a diagram neural network, and the method comprises the steps: 1, carrying out the preprocessing of a circuit netlist, and obtaining a circuit netlist topological matrix; 2, connecting a preset pin state and the number of the arranged units to obtain features after connection; 3, inputting a preset canvas state, the circuit netlist topological matrix and the connected features into the intelligent agent to obtain a layout and wiring result; and 4, constructing an action mask according to a layout wiring result, obtaining a predicted action by using the action mask, and generating a schematic circuit diagram according to the predicted action. According to the method, the schematic circuit diagram can be automatically generated, diagram information in a circuit netlist is concerned, and selection of invalid actions is avoided through action masks.

The invention relates to a method and device for automatically generating a schematic circuit diagram sketch and a storage medium, and belongs to the technical field of circuit design, and the method comprises the following steps: extracting target parameters of netlist information by using a script function of circuit drawing software and a file type of the netlist information of a circuit board; and based on the target parameters, generating a schematic circuit diagram sketch containing the network labels and the annotation characters in circuit drawing software. According to the method for automatically generating the schematic circuit diagram sketch provided by the invention, the file type of the netlist information is determined according to the netlist information of the circuit board, and the target parameters are accurately extracted according to the file type by utilizing the script function of the circuit drawing software, so that errors possibly introduced by manual operation are avoided; according to the method, the schematic circuit sketch containing the network label and the annotation characters is generated in the circuit drawing software according to the target parameters, the schematic circuit sketch easy to read can be quickly generated, and compared with traditional manual drawing, time and labor cost are greatly saved.

The invention provides an automatic layout method and device for a main wiring diagram of a transformer substation, and belongs to the technical field of circuit diagram drawing, and the method comprises the steps that first data is processed to obtain transformer parameters, and the first data is power grid equipment topological structure data; determining a plurality of buses and bus equipment corresponding to each bus, and calculating a first connection relation line taking the bus equipment as a starting point based on the transformer parameters, the bus equipment and each node; carrying out layout on the bus equipment and the load equipment based on the first connection relation line to obtain a first main wiring diagram; and optimizing the first main wiring diagram based on the first data to obtain a target main wiring diagram. The graph drawing efficiency can be improved, and the drawing result display effect is enriched.

The invention relates to a distribution network line risk prediction method based on natural language processing and rule matching. The method comprises the specific steps that road construction information data in a target webpage are collected based on a Rust language and by means of a plurality of databases; the method comprises the following steps: constructing a BERT natural language learning model based on a Transformers architecture, and carrying out pre-training, wherein the BERT natural language learning model adopts a bidirectional encoder and a self-attention mechanism; performing text cleaning on the acquired road construction information data, performing word segmentation on the road construction information data by utilizing a BERT natural language learning model, and extracting event feature data in the road construction information data; extracting time and place information of each event from the feature data of the road construction information data by using a pre-trained BERT natural language learning model; collecting latitude and longitude coordinates of the power distribution network circuit diagram, and drawing the circuit diagram on the map according to the latitude and longitude coordinates; and converting each event site in the road construction information data into latitude and longitude coordinates.

The present invention proposes an analog circuit intelligent design method based on process and post-simulation optimization feedback, which belongs to the field of multi-objective optimization of circuit design. The method includes three processes: a circuit diagram optimization process, a layout optimization process, and a device process optimization process. The circuit diagram optimization process uses the GLAL-MOPSO algorithm to optimize the parameters of circuit components; the layout optimization process designs a strategy for grouping decision variables on the basis of the GLAL-MOPSO algorithm to cope with the optimization problem of large-scale variables in layout optimization; in order to increase the optimization range of circuit design, the device process optimization process is added to the circuit optimization process. The process optimization process uses the GLAL-MOPSO algorithm to optimize the parameters of the device process, and the results obtained in the device process optimization process can be used as the basis for re-optimization of the circuit diagram and layout. The present invention saves time cost and manual design cost by automating the optimization iteration of analog circuit design and device process optimization, and effectively improves the design efficiency of the circuit.