119 results about "Circuit diagram" patented technology

The invention relates to the technical field of communication network fault diagnosis, and discloses a communication information processing method and device. The method comprises the steps that a voiceprint sensor collects an original signal, and a quantum coding time-frequency matrix is generated through time-frequency conversion and quantum coding; the matrix and real-time circuit diagram data are fused, and topology-fault joint features are generated through feature alignment and wavelet-convolution joint extraction; analyzing the features to reconstruct a node relation graph, and generating real-time updated circuit diagram data through graph optimization; loading an incremental parameter adapter initialization graph neural network based on the data, and executing fault propagation deduction to output fault coordinates and confidence data; generating an incremental parameter adapter according to confidence data federal optimization; and analyzing the fault coordinate matching topology library based on the adapter, and associating the maintenance knowledge base to output a visual repair suggestion. According to the method, fault dynamic deduction is realized, the cross-line generalization ability is enhanced by an incremental learning mechanism, bandwidth occupation is reduced by edge-cloud cooperation, and the fault positioning efficiency and accuracy are remarkably improved.

The invention belongs to the technical field of integrated circuit design automation, and discloses an anti-radiation standard unit automatic layout method, which adopts a two-stage reinforcement learning strategy: in the first stage, training a device layout strategy model, extracting MOS device information by analyzing a CDL file, and constructing a circuit diagram structure as state representation; generating a preliminary device layout result by using a dynamic action mask mechanism; and in the second stage, independently training the guard band insertion strategy model, and optimizing the guard band insertion position and sequence based on the candidate insertion point set so as to meet the anti-radiation design rule and reduce the wiring difficulty. The two stages both adopt a Maskable PPO algorithm, encourages gate alignment, source-drain proximity and shortest connection path through a reward function, and punishes layout conflicts and DRC violations. According to the invention, by means of the two-stage design of division of labor and cooperation, the layout efficiency and compliance of the anti-radiation standard unit are significantly improved, and the method has the characteristics of high efficiency, self-adaption and high engineering practicability.

The invention discloses a method and device for automatically designing a gas path diagram. The method comprises the following steps: carrying out element identification on an input three-dimensional model to obtain the element type of each element in the three-dimensional model; based on the element type, selecting elements contained in an action group through interaction setting of a client, and configuring corresponding action instructions for the action group to obtain action group configuration data; performing legend matching on elements contained in the action group to obtain model element legend data; and carrying out legend feature recognition on the model element legend data, and carrying out legend connection and content labeling on the basis of a legend feature recognition result and the action group configuration data so as to generate a gas path diagram. The technical problems that an existing gas circuit diagram is low in design efficiency and prone to errors are solved.

The invention discloses an intelligent simulation method, system and device based on freehand circuit recognition, and relates to the technical field of electronic engineering and artificial intelligence. The method comprises the following steps: receiving hand-drawn circuit image data and preprocessing the hand-drawn circuit image data; detecting elements in the preprocessed hand-drawn circuit image by adopting a pre-constructed target detection model, and extracting to obtain a detection result; processing the detected hand-painted circuit image through a pre-constructed image processing module, and extracting to obtain communication regions and node information of each element; generating an SPICE netlist by using a large language model according to the image detection result and the communication region and node information of each element in the image; and inputting the SPICE netlist into an Ngspice simulation engine to carry out circuit simulation. According to the method, the improved YOLOv9t model and the DAG-ChiSynth algorithm are used for data generation and recognition, elements, topology and parameters can be automatically extracted from the hand-drawn circuit image of the student, end-to-end simulation is achieved, interactivity and efficiency in electronic education are remarkably improved, and teaching cost is reduced.

The invention discloses a method for generating an SPICE netlist by a circuit diagram driven by a multi-modal large model. The method comprises the following steps: completing construction from a circuit image to an SPICE netlist data set; supervising and finely tuning the circuit-to-netlist model; a step-by-step reasoning normal form in a track guiding reinforcement learning stage; a multi-level reward mechanism in the track guide reinforcement learning stage evaluates the performance of the circuit-to-netlist model from the aspects of reasoning quality, netlist generation accuracy and logic consistency; a reflection learning mechanism in a track-guided reinforcement learning stage; and carrying out overall optimization in a trajectory-guided reinforcement learning stage. According to the method, the precision of conversion from the circuit image to the SPICE netlist and the reasoning consistency can be improved by utilizing a track guide reinforcement learning normal form and integrating step-by-step reasoning, a multi-level reward mechanism and an inverse learning mechanism.

Embodiments of the present application disclose a kind of integrated circuit digital back-end physical optimization method, equipment, medium and product.The method comprises: the pin node in circuit diagram and the interconnection between nodes in the circuit diagram are obtained by pre-processing to be optimized circuit diagram;According to pin node and interconnection, the wiring estimation of circuit diagram is carried out;According to the pre-processing result and the wiring estimation result of circuit diagram, the layout optimization index and timing index in circuit diagram are determined;Layout optimization index includes at least one of the following: power consumption parameter, gate circuit area parameter, buffer area parameter and half perimeter line length;Timing index includes at least one of the following: load violation parameter, signal conversion violation parameter and timing margin parameter;According to layout optimization index and timing index, the target optimization function of circuit optimization is determined, the circuit layout optimization in integrated circuit optimization, gate size adjustment and buffer layout adjustment are carried out, and optimization result is obtained, and circuit layout, gate size adjustment and buffer layout can be optimized.

The application belongs to the field of computer-aided teaching, and discloses a simulation method and system of interactive circuit experiment and a computer program product, comprising: randomly generating the number of circuit nodes, and planning the circuit layout according to the number of nodes; forming an initial node full connection matrix according to the circuit layout by adopting the three-short principle; eliminating the cross connection in the grid in the node full connection matrix, and randomly removing part of the connection between the nodes connected to each other with a preset probability, thereby forming different node connection matrices; generating different circuit topology graphs according to the circuit layout and the different node connection matrices; adding circuit components to the circuit topology graphs to obtain circuit diagrams; and generating an interactive experiment interface for users to conduct independent experiments according to the circuit topology graphs or the circuit diagrams in combination with the knowledge points related to the circuit simulation experiment, so as to overcome the problem that the existing circuit simulation teaching platform cannot meet the personalized experiment or interactive exploration of students due to the fixed circuit diagram.

The invention provides a python-based clock tree visualization implementation method and system, and relates to the technical field of integrated circuits, and the method comprises the steps: reading an sdc file, extracting all clock information according to a grammar rule of the sdc file, and storing the clock information into a first dictionary according to names; reading the netlist, obtaining port information of all modules, and storing the port information into a second dictionary according to the names of the modules; reading a file of the library file, extracting port information of each module, and supplementing the port information to a second dictionary; all clock paths in the sdc are traced, and a fourth dictionary only containing all clock paths is generated; according to the fourth dictionary, dividing and drawing a port connection relationship in each module according to the modules, and forming a circuit diagram of each module; and developing a graphical interface for displaying the drawn circuit diagram, and setting functional keys in the interface. According to the method, a complete clock path and an integrally designed clock structure can be presented, a graphical interface can be provided, and the clock structure and the clock path can be visually viewed.

A method for forming a quadrant control valve system V2 of a hydraulic system 200 is provided. The quadrant control valve system V2 includes at least one control valve assembly SVA2, which includes at least one control valve SV1, SV2, SV3, SV4, and includes an electronic valve controller C2 and a control valve sensor system. The method includes the following steps: automatically performing a quadrant-based load case analysis, automatically performing a circuit diagram synthesis, automatically performing a controller synthesis, and implementing the synthesized circuit diagram and implementing the synthesized controller.

The invention discloses a non-protocol equipment IO data acquisition and processing method and system, and belongs to the technical field of data acquisition and processing. The method comprises the following steps: identifying a preprocessed non-protocol equipment circuit diagram based on a YOLOv8 model, and generating a five-dimensional protocol dictionary based on an identification result; generating semantic label data based on the five-dimensional protocol dictionary; based on the semantic label data, obtaining health states of multi-dimensional feature vectors and fault prediction results of different risk levels; and based on the semantic label data and the health state of the multi-dimensional feature vector, adjusting the data acquisition frequency of various industrial scenes to obtain a new data acquisition frequency instruction. According to the method and the device, the problems of high manual dependence, data classification semantic deficiency, low retrieval efficiency, equipment state detection simplification, early warning lag, collection frequency solidification, insufficient gateway reliability, poor adaptability of old equipment and serious energy consumption waste of non-protocol IO collection in the prior art are solved.

This invention discloses a method, apparatus, medium, and device for adjusting the multi-segment layout of circuit diagram traces. The method includes: determining a target line segment and its displacement point, and multiple pushing lines parallel to the target line segment located on the target line segment's movement path, wherein the slope and connection relationship of the preceding and following line segments remain unchanged during the target line segment's movement; selecting the pushing line segment closest to the target line segment as a comparison line segment, and sorting the pushing line segments according to a preset order; sequentially finding pushing line segments whose inflection points with the comparison line segments are not all located on opposite sides of each other as new comparison line segments, and selecting the other pushing line segments as merged line segments; sequentially moving each comparison line segment in the normal direction to a preset distance beyond the displacement point, and merging the two when it connects with the merged line segment during the movement; and moving the target line segment in the normal direction until it is collinear with the displacement point. This invention can automatically move other conflicting parallel line segments during the movement of the target line segment.

Embodiments relate to the field of semiconductors, and provide a method for layout placement and routing, a circuit layout, an electronic device, and a storage medium. The method includes: generating a plurality of layout units (100) arranged along a preset direction (X) based on a schematic circuit diagram, each of the plurality of layout units (100) having a plurality of connection nodes (101), and two connection nodes (101) at two ends of each of the plurality of layout units (100) being defined as assessment nodes; determining any one of the plurality of layout units (100) as a target layout unit, and obtaining a positional relationship between the connection nodes (101) in rest of the plurality of layout units having same node information as the assessment nodes in the target layout unit and the assessment nodes; and performing routing to electrically connect the connection nodes (101) having the same node information.

The present application belongs to the technical field of electrical fingerprint identification, and specifically relates to a non-intrusive event detection method based on image features and retrieval. The present application determines the event or state of a certain electrical equipment within a period of time through a multi-layer full convolutional network, adds an attention score mechanism after network feature extraction, decomposes the image into several key points, and simultaneously gives the local features of the key points an attention score; through the network-extracted features and in combination with the attention score, the weight of the event occurring in the voltage and current change section of the circuit diagram is readjusted, and finally the matching event features in the feature library are retrieved to identify the event category. The present application improves the accuracy of switching event identification, and simultaneously has a light model order, a simple method, flexible use, simple and efficient training, high detection accuracy, and a wide range of application scenarios.

The application relates to a substation physical circuit design and SPCD modeling integrated method, which comprises the following steps: constructing substation basic data at a client end; drawing a total physical circuit diagram of the whole station by a graphic element model with information attributes at a mapping end; adding a preset number of optical distribution ODFs in each physical circuit based on the total physical circuit diagram of the mapping end or a physical circuit list generated by a server database of a physical circuit submission end; configuring an IPCD model of secondary equipment at the client end; instantiating the port of the secondary equipment IPCD model based on the physical circuit; customizing a drawing template of each device based on the instantiated IPCD model, and automatically realizing the conversion of a database information model to a mapping end graphic model; intelligently grouping cables, and outputting design drawings and SPCD model files of construction drawings in depth. The application can effectively improve the design efficiency and quality of drawings, and automatically generates SPCD model files required for debugging and operation and maintenance.

The power grid standard analysis method, device, equipment and storage medium provided by the application relate to the field of power systems. The method comprises the following steps: obtaining a power grid standard document, wherein the power grid standard document comprises standard text clauses, circuit diagram images and parameter table data; performing semantic labeling on the standard text clauses to identify power terminology entities; performing disambiguation processing on the power terminology entities to obtain disambiguated standard text clauses; generating standardized knowledge units based on the disambiguated standard text clauses, the circuit diagram images and the parameter table data; and performing logical reasoning on the standardized knowledge units to determine a content consistency checking result of the power grid standard document. Through the application, the drawbacks of low efficiency, strong subjectivity and unstable quality of manual analysis are overcome, and efficient, objective and standardized processing of the power grid standard is realized.

The invention provides a freehand circuit diagram recognition method, device and equipment based on an improved YOLOv11 algorithm, and relates to the technical field of image recognition. The method comprises the following steps: inputting a freehand circuit diagram to be recognized into an improved YOLOv11 algorithm to obtain an element recognition result and a textbox recognition result of the freehand circuit diagram to be recognized; wherein the improved YOLOv11 algorithm comprises an improved C3k2-PSE module based on a partial convolution unit and an enhanced space-channel cooperation unit; extracting coordinate information of element end points, coordinate information of nodes and characters in each textbox in the to-be-recognized hand-drawn circuit diagram from the to-be-recognized hand-drawn circuit diagram; and according to the coordinate information and the recognition result of the YOLOv11 algorithm, combining the endpoints and nodes of the elements, each element and the characters in each textbox into an electronic circuit diagram, and obtaining the recognition result of the freehand circuit diagram to be recognized. According to the invention, the discrimination degree of similar elements can be improved, so that the to-be-recognized hand-painted circuit diagram can be recognized accurately.

This application relates to the field of integrated circuit design automation technology, and provides a method and system for verifying analog circuit structures based on graph neural networks. The method includes: converting a SPICE netlist into a graph structure representation, where nodes correspond to devices and edges correspond to electrical connections, and extracting feature vectors containing device type, parameters, functional roles, connection types, and signal directions; encoding the circuit diagram using a graph attention network to obtain node embeddings and graph embeddings; performing multi-task prediction based on the embedding results, including node classification, graph classification, structure scoring, and error localization; and finally generating a verification report containing an error list, location information, and repair suggestions. This application achieves automatic detection and precise localization of errors in analog circuit structures, improving detection accuracy by a significant margin and possessing strong generalization capabilities.

The invention belongs to the technical field of image processing, and particularly relates to a circuit graph feature matching method based on dense matching, which comprises the following steps of: firstly, respectively carrying out multi-scale feature fusion on an image to be detected and a template image to obtain a low-resolution fusion image, and then carrying out convolution on the multi-scale features of the two images to obtain key point heating power; the low-resolution fusion image passes through a linear layer to obtain a confidence map, finally, in a feature matching stage, key points with high confidence scores form feature descriptors, the feature descriptors are adjusted to obtain image descriptors, the similarity between the image descriptors is calculated to carry out nearest neighbor matching, and rough key point matching pairs are obtained through calculation; the matching result obtained from the coarse-grained matching stage is used for further fine alignment, and the positions of the corresponding key points in the image are adjusted more accurately, so that more accurate matching is obtained. According to the method, the positions of the matched key points are more accurate, and more accurate and efficient image matching is realized.

The invention discloses a low-noise amplifier circuit design method, a low-noise amplifier circuit and a low-noise amplifier chip. The low-noise amplifier circuit design method comprises the following steps: constructing a small-signal equivalent circuit diagram of a transistor added into a feedback network; obtaining the input impedance and the output impedance of the transistor according to the small signal equivalent circuit diagram; according to the input impedance and the output impedance, obtaining a feedback gain of a transistor added to the feedback network and an intrinsic gain of a transistor without the feedback network, and according to the feedback gain and the intrinsic gain, obtaining a proportionality coefficient; constructing a noise analysis equivalent circuit diagram of the transistor added into the feedback network; obtaining a total noise coefficient according to the noise analysis equivalent circuit diagram, and obtaining an influence coefficient according to the total noise coefficient; and constructing a contour map about feedback parameters of the feedback network according to the proportionality coefficient and the influence coefficient, and analyzing the gain flatness and noise performance of the transistor according to the contour map. According to the invention, a low noise coefficient, a high power gain and an excellent gain flatness index are synchronously realized in an ultra-wide frequency band.

A high-precision circuit board and a preparation method therefor. The method comprises: acquiring a preset circuit diagram (S1001); arranging a plurality of conductive layer groups on the basis of the preset circuit diagram, wherein conductive layers requiring formation of the same blind hole or buried hole constitute a conductive layer group, adjacent conductive layers requiring no formation of a blind hole or buried hole constitute a conductive layer group, and the conductive layer groups comprise core boards (S1002); disposing conductive layers in a stacked manner, disposing adhesive layers between the core boards of the same group or between the core boards and the conductive layers, and disposing an auxiliary layer between different conductive layer groups (S1003); laminating the stacked conductive layers, the adhesive layers, and the auxiliary layer, and peeling off the auxiliary layer after the lamination, so that the conductive layer groups constitute sub-boards (S1004); performing drilling at a preset position of a sub-board to form a through hole (S1005); disposing the sub-boards in a stacked manner, and disposing an adhesive layer between adjacent sub-boards (S1006); and laminating the stacked sub-boards and the adhesive layer (S1007).

The invention provides a schematic circuit diagram comparison method and device, electronic equipment and a storage medium, and relates to the technical field of circuit design, and the method comprises the steps: converting a conventional schematic circuit diagram comparison idea, converting circuit elements into graph units, and determining a boundary region of the comparison circuit elements by comparing the shape description information of the graph units, a reference circuit schematic diagram is obtained, a target reference graph unit is determined in a boundary area in the reference circuit schematic diagram, difference information corresponding to reference circuit elements is determined by comparing a contrast graph unit with the target reference graph unit, the difference information is overlaid on the reference circuit schematic diagram for visual display, and the comparison process is completed in a number-form combination mode. The difference information can be visually displayed, the comparison efficiency and accuracy of the schematic circuit diagram are improved, the user experience is improved, a user can rapidly master the difference information of the reference schematic circuit diagram and the contrast schematic circuit diagram, and then the design quality and development efficiency of the user are improved.

The application belongs to the technical field of image processing, and particularly relates to a circuit pattern feature matching method based on dense matching. The method firstly performs multi-scale feature fusion on a to-be-detected image and a template image respectively to obtain a low-resolution fusion image, then the multi-scale features of the two images are subjected to a convolution to obtain key point heat; the low-resolution fusion image is subjected to a linear layer to obtain a confidence map, finally in a feature matching stage, a feature descriptor is formed by key points with high confidence scores, the feature descriptor is adjusted to obtain an image descriptor, the similarity between the image descriptors is calculated to perform nearest neighbor matching, and a rough key point matching pair is calculated; the matching result obtained from the rough granularity matching stage is used for further fine alignment, the positions of the corresponding key points in the image are more accurately adjusted, and therefore more accurate matching is obtained. The method makes the positions of the matching key points more accurate, and realizes more accurate and efficient image matching.

The utility model discloses a working state checking circuit of explosion-proof electrical equipment. The working state checking circuit comprises a plurality of state detection circuits, a display and a backup intrinsic safety battery, two ends of each electronic component in the explosion-proof electrical equipment are respectively connected to a detection point of one state detection circuit; the state detection circuit is used for detecting and outputting the voltage of an electronic element or outputting a voltage value under a self fault; the output end of the state detection circuit is connected with the display; the display is arranged on a shell of the explosion-proof electrical equipment; and the state detection loop is respectively connected with alternating current and the backup intrinsic safety battery. According to the invention, a maintainer can determine a fault point on site according to the schematic circuit diagram and the measured and recorded voltage value of the electronic component on site, maintenance is carried out in time, the equipment fault maintenance time is shortened, and the production efficiency is improved.

The invention discloses a method and device for automatically designing a gas path diagram based on AI. The method comprises the steps that based on feature points of a three-dimensional model, key point cloud of the three-dimensional model is generated through a point cloud processing algorithm, and based on the key point cloud, part category recognition is conducted through a neural network model; correspondingly binding the identified part category with a preset two-dimensional legend block to obtain part legend binding data; analyzing the gas path schematic diagram vector file, extracting graphic metadata in the gas path schematic diagram vector file, and generating part connection relation data based on the part legend binding data and the extracted graphic metadata; and based on the part connection relation data, connecting the corresponding two-dimensional legend blocks and adding feature attributes to generate a gas path diagram. According to the invention, the technical problems of inaccurate gas path diagram generation and low efficiency in the prior art are solved.

The invention provides a sequential circuit characterization learning method based on a graph neural network and a state space model, and belongs to the field of electronic design automation, and the method comprises the steps: obtaining a sequential circuit diagram, and constructing a graph neural network reasoning module through designing a quadrupole embedding space; performing dynamic function modeling on the time sequence circuit diagram by using a diagram neural network reasoning module to obtain a node embedding vector; the method comprises the following steps: constructing a Mama memory module on the basis of a token method and a Mama framework; and performing dual structure modeling on node embedding by using a Mamba memory module to obtain an embedded vector, and completing sequential circuit characterization learning. The method solves the problems that an existing sequential circuit characterization learning method destroys the original structure of the circuit, cannot capture the core of the sequential circuit, is low in processing efficiency, is low in training speed, is limited in performance improvement, and is not obvious in precision advantage.

A temperature-controlling system for controlling the temperature of at least three components via a temperature-controlling agent is disclosed. The system includes a system inlet for supplying the temperature-controlling agent, a system outlet for discharging the temperature-controlling agent, and at least three components to be temperature-controlled. Each component has a component inlet for supplying the temperature-controlling agent and a component outlet for discharging the temperature-controlling agent from the respective component. The system inlet is fluidically connected to at least two component inlets. The system outlet is fluidically connected to at least one component outlet. The at least three components are fluidically interconnected according to a circuit diagram such that a number of components fluidically connected in parallel with regard to the temperature-controlling agent is greater at the system inlet than at the system outlet.

The application relates to a circuit diagram checking method and device, computer equipment, a storage medium and a computer program product. The method comprises the following steps: obtaining a target net list of a circuit to be checked, the target net list comprising a connection relationship between each pin of the circuit to be checked; simulating the circuit to be checked based on the target net list; if the simulation determines that the number of external pins of the circuit to be checked is different from the number of pins of the connected internal circuit unit, no special element is arranged between two connected external pins of the circuit to be checked. The method can avoid errors in a circuit layout converted from a circuit schematic diagram.

The invention discloses a synchronous generator single-phase ground sequence impedance parameter identification method based on RTDS real-time simulation modeling and a feedforward neural network. The method comprises the following steps: (1) building a synchronous generator RTDS model; (2) deriving a single-phase grounding short-circuit transient stator current expression on the basis of the equivalent circuit diagram, the flux link equation and the voltage equation of the synchronous generator; and (3) taking the minimum standardized error sum of squares between a single-phase grounding short-circuit current test value and a short-circuit current calculation value obtained by calculating parameters obtained by identification as a target, and proposing a synchronous generator single-phase grounding sequence impedance parameter identification method based on a feedforward neural network. According to the method, the RTDS is utilized to perform accurate modeling on the synchronous generator, the neural network-based synchronous generator sequence impedance parameter identification method is provided on this basis, the neural network model is trained by utilizing short-circuit experiment current data, high-precision mapping from short-circuit current to impedance parameters is realized, and the intelligence and accuracy of parameter identification are improved.

The application discloses a kind of multi-modal large model driven circuit diagram generation SPICE netlist method, comprising: complete from circuit image to the construction of SPICE netlist dataset;Supervision fine-tuning is carried out to circuit conversion netlist model;Trajectory-guided reinforcement learning phase's step-by-step inference paradigm;Trajectory-guided reinforcement learning phase's multilevel reward mechanism respectively from inference quality, the accuracy of generated netlist and logic consistency aspect to the performance of circuit conversion netlist model is evaluated;Trajectory-guided reinforcement learning phase's reflective learning mechanism;Trajectory-guided reinforcement learning phase's overall optimization is carried out.The present application utilizes trajectory-guided reinforcement learning paradigm, through integration step-by-step inference, multilevel reward mechanism and reflective learning mechanism, can improve the precision and inference consistency of circuit image to SPICE netlist conversion.

An apparatus for automatically determining an electronic circuit diagram of a vehicle includes n system code determination unit configured to, when component codes of electronic components mounted on a vehicle are input, determine system codes of electronic systems configurable based on the electronic components, a circuit diagram determination unit configured to select and determine, from a circuit diagram database, standard circuit diagrams matched with the system codes determined by the system code determination unit, and a display unit configured to display the standard circuit diagrams determined by the circuit diagram determination unit to be matched with electronic systems predetermined for respective system codes.