Circuit layout method, graphic display method and system thereof

A logic circuit, layout and wiring technology, applied in the field of programmable logic arrays, can solve problems such as system jamming and occupying system memory, and achieve the effect of reducing the number, compact arrangement, and optimization method

Active Publication Date: 2019-01-29
SHANGHAI ANLOGIC INFOTECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When drawing a complex logic circuit, through reasonable layout and wiring of the circuit, the logic circuit diagram is evenly distributed, the number of connection intersections is reduced, and the existing drawing tools are improved due to unreasonable layout and wiring. Dayton's problem

Method used

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  • Circuit layout method, graphic display method and system thereof
  • Circuit layout method, graphic display method and system thereof
  • Circuit layout method, graphic display method and system thereof

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Embodiment Construction

[0043]In the following description, many technical details are proposed in order to enable readers to better understand the application. However, those skilled in the art can understand that the technical solutions claimed in this application can be realized even without these technical details and various changes and modifications based on the following implementation modes.

[0044] Explanation of some concepts:

[0045] 1. Programmable logic array (PLA): It is a programmable device that can be used to implement combinational logic circuits.

[0046] 2. Logic circuit (schematic): It is a circuit for the transmission and processing of discrete signals, based on the principle of binary, to realize the logical operation and operation of digital signals.

[0047] 3. FPGA (Field-Programmable Gate Array): Field Programmable Gate Array, which is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in...

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Abstract

The present application relates to a programmable logic array, and discloses a logic circuit layout and routing method, a graphical display method and a system thereof. The present invention is directed to graphical display of logic circuits, directed acyclic graph generation algorithm and preset column distribution rules are used to allocate logical columns, and heuristic algorithm is used to allocate logical rows based on median sorting, so as to optimize the number of intersection points. At the same time, the physical coordinates of components are allocated according to their physical dimensions in the process of automatic layout, so that the components are centralized and arranged compactly. The method of cache and windowing is also used to realize the fast response when the logic circuit of large layout is dragged to view. Finally, the generated logic circuit diagram is uniformly distributed, the input and output conform to the circuit habits, the number of intersection points isless, and the plotting is fast.

Description

technical field [0001] The present application relates to a programmable logic array, in particular to a logic circuit layout and wiring method, a graphical display method and a system thereof. Background technique [0002] Programmable Logic Array (PLA) is a kind of programmable logic device. It is a large-scale integrated circuit that is programmable with and / or array and contains memory elements. It can realize any logic function. combinational circuits and sequential circuits. [0003] As the complexity of programmable logic array such as FPGA circuit design increases, designers pay more and more attention to high-level design methods. To improve the interactivity in the design process, the use of schematic diagrams is crucial. Traditionally, designers draw logic circuit diagrams manually according to the feedback results of EDA tools, which will lead to a lot of waste of time and energy, especially in the case of large-scale circuits, which are prone to errors. Altho...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/392
Inventor 熊发田
Owner SHANGHAI ANLOGIC INFOTECH CO LTD
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