293 results about "Combinational logic" patented technology

The invention discloses an Agent-based tool combination and task processing method and device, equipment and a medium, and the method comprises the steps: carrying out the natural language processing of a task instruction inputted by a user, and generating a structured semantic vector containing task semantics; performing similarity matching on the structured semantic vector and a predefined tool node semantic tag in a knowledge base, and outputting a candidate tool node set related to the current task; performing dynamic priority ranking on the candidate tool node set based on context parameters to generate an initial thinking chain; converting the thinking chain into a tree flow chart structure, and performing dynamic addition and deletion or parameter adjustment on tool nodes in the flow chart according to a feedback or preset optimization strategy; and updating tool combinational logic according to the adjusted thinking chain, processing the task instruction, and outputting a task processing result. The tool nodes are matched through the Agent agents, and the thinking chain is generated through dynamic sorting, so that the task processing efficiency and accuracy are improved.

A multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit.

The invention discloses a combinational logic clustering optimization method and system based on reinforcement learning. The method comprises the following steps: S1, counting fan-out information of registers and combinational logic units in a circuit netlist; s2, according to the fan-out information, screening out registers and combinational logic units of which the fan-out quantity is greater than a first preset threshold and the worst time sequence path time sequence violation value of the output signal is smaller than a second preset threshold, and generating a target unit list; s3, acquiring fan-out combinational logic information of each unit in the target unit list; s4, on the basis of the fan-out combinatorial logic information, clustering operation is carried out on fan-out logic units on the basis of a reinforcement learning algorithm; s5, after logic clustering is completed, revising the netlist of the circuit; after the revision is completed, carrying out equivalence check; and S6, rearranging and wiring the circuit according to the modified netlist. The method can effectively reduce key path delay, optimizes circuit performance, and is especially suitable for large-scale integrated circuit design.

The invention relates to an analog quantity selection method and system based on a Boolean switch, in particular to the field of industrial automation, and aims to directly realize signal mapping by adopting a pure hardware combinational logic circuit and thoroughly eliminate instruction execution time, so that the state change of a Boolean switch signal can be instantaneously reflected on analog quantity output; according to the method, real zero-delay switching is achieved, meanwhile, program adjusting algorithms in any form are avoided, disturbance phenomena such as overshoot or undershoot are completely eradicated from the principle, and high stability and accuracy of output signals are ensured. Finally, according to the technology, the control instruction can be accurately and synchronously issued without delay, and the response speed and the synchronization precision of the whole control system in a high dynamic response industrial scene are remarkably improved.

An apparatus to facilitate redundant parallel computing structures as a cache is disclosed. The apparatus includes redundant parallel computing hardware circuitry comprising redundant sets of computing combinatorial logic and register-based storage circuitry; and crossbar fabric connected to the registers of the redundant parallel computing hardware circuitry, wherein the crossbar fabric to cause register state of the register-based storage circuitry to be selected based on a tagged cache model.

The invention discloses a digital circuit optimization method and system based on logic clustering. The method comprises the following steps: S1, counting fan-out information of all registers in a circuit netlist; s2, according to the fan-out information of the registers, screening out the registers of which the fan-out quantity is greater than a first preset threshold value and the logic series is greater than a second preset threshold value and which are located on the critical path, and generating a candidate register list; s3, obtaining register fan-out first-level combinatorial logic information; s4, performing clustering operation on the logic units based on the first-level combinational logic information, and dividing physically adjacent logic units into the same cluster according to the physical position relationship of the logic units; s5, associating the clustered logic units together and adjusting the connection relation of the logic units; s6, carrying out equivalence check; and S7, rearranging and wiring the circuit according to the modified netlist. The physical distance of a time sequence path can be effectively reduced, the time sequence performance of the circuit is optimized, and the method is suitable for large-scale integrated circuit design.

The subject matter of the invention is a redundant parallel computing structure as a cache. An apparatus for facilitating a redundant parallel computing fabric as a cache is disclosed. The device comprises a redundant parallel computing hardware circuit module, wherein the redundant parallel computing hardware circuit module comprises computing combinatorial logic and a redundant set of register-based storage circuit modules; and a crossbar fabric connected to the registers of the redundant parallel computing hardware circuit module, where the crossbar fabric is to cause the tag-based cache model to select the register state of the register-based memory circuit module.

The invention relates to the technical field of multi-scene dynamic orchestration, in particular to a multi-scene-based orchestrable unified preprocessing rule method and system, and the method comprises the steps: carrying out the dynamic matching of a rule according to scene information, employing a visual rule orchestration engine, and employing a micro-service architecture design; the method has the beneficial effects that different service scenes can be covered through the modular rule base and the dynamic configuration capability, repeated development of a traditional single scene preprocessing system is avoided, and the technology reuse rate is improved. Visual flow arrangement is adopted, a user is allowed to customize a rule execution sequence, conditional branches and combinatorial logic, complex business demand changes are flexibly dealt with, and the technology coupling degree is reduced.

The invention relates to a current source inverter short circuit fault diagnosis method based on phase current and average absolute value mixed error thereof. The invention relates to the technical field of motor control, and the method comprises the steps: collecting the A, B and C three-phase current of a permanent magnet synchronous motor in real time in a process that a current source inverter drives the permanent magnet synchronous motor to operate, and carrying out the filtering and noise reduction of the A, B and C three-phase current; a Park vector module value is obtained through Park transformation, and the three-phase current is divided by the Park vector module value to carry out normalization processing on the phase current; generating a hybrid diagnosis variable and an auxiliary diagnosis variable based on the reference current and actual current error and the average absolute value and average value error of the normalized current; and in combination with a preset threshold value and variable combinational logic, precise positioning of single-tube short circuit, same-side out-of-phase double-tube short circuit and different-side out-of-phase double-tube short circuit is realized.

The invention discloses a self-service door opening method for a store, and relates to the technical field of self-service stores. The system carries out intelligent matching according to a pre-stored user file, calculates a similarity threshold value through an algorithm, judges that a user is a legal user if the matching degree exceeds a preset value, or rejects access; a dynamic combination strategy is adopted to allow an administrator to configure weights and combination modes of different fields according to the security requirements of the store, so that the user experience is optimized and the privacy leakage risk is reduced on the premise of ensuring the security; a background management system flexibly sets a weight value and combinatorial logic of each verification element, the matching efficiency is dynamically optimized based on a preset similarity threshold, if a comprehensive score after element combination reaches a security level score configured by the system, rapid door opening is automatically authorized, otherwise, secondary verification or manual auditing is triggered, and the safety of the system is ensured. The false rejection rate is reduced, the safety protection capability is improved, the verification modes are automatically switched according to regions or time periods, and the door opening speed is high when the operation is successful.

The invention discloses a single-phase photovoltaic energy storage inverter parallel operation system relay fault detection method. The method comprises the following steps of determining a relay detection sequence according to configuration of a master machine and a slave machine; obtaining an absolute value of a difference value between the grid-connected port voltage effective value and the load port voltage effective value, comparing the absolute value with a preset first threshold value, and selecting a corresponding relay detection logic; the photovoltaic energy storage inverter unit is controlled to output open-loop voltage, the turn-on and turn-off sequence of the corresponding relays is controlled, and whether each relay has a sticking fault or a non-closing fault or not is detected in combination with a voltage judgment result. According to the method, all-working-condition adaptation of all-unit detection before grid connection of the parallel operation system, independent detection of a new machine and a reconnected slave machine in operation and all-unit re-detection after failure recovery of a host is met, and the detection problem in a dynamic adjustment scene of the parallel operation system is solved. Through the combinational logic of voltage threshold judgment and relay action time sequence control, the faults that the relay is stuck and cannot be closed can be accurately recognized, and missing detection and false detection are avoided.

The invention discloses a universal multiphase clock generation circuit and a combinational logic circuit thereof. The combinational logic circuit comprises a first-stage NAND gate and a second-stage NAND gate which are cascaded, the generation circuit is constructed by taking the combinational logic circuit as a basic unit; the generation circuit is a closed loop formed by connecting 2N basic units end to end; the first-stage NAND gates of the odd-numbered basic units form latches pairwise, and the first-stage NAND gates of the even-numbered basic units also form latches pairwise; each basic unit takes the output of the adjacent previous basic unit as the input and outputs a basic clock signal with a preset duty ratio based on a preset selection signal; performing odd number of times of phase inversion on the 2N basic clock signals output by the 2N basic units to obtain 2N-phase non-overlapping clock signals; and when N is an odd number, performing NAND operation on the N groups of adjacent two basic clock signals to obtain N-phase non-overlapping clock signals.

Receiving a codeword of a forward error correction (FEC) code, each codeword in the FEC code having a minimum distance of at least seven to any other codeword in the FEC code, calculating multi-bit syndromes by applying columns of a check matrix to the received codeword using combinatorial logic, and responsively determining the received codeword comprises at least three errors, determining coefficients of an error locator polynomial using a coefficient combinatorial logic circuit by combining the multi-bit syndromes using non-iterative combinatorial logic performing arithmetic operations in a finite field F(2 n ), determining respective error positions for each error of the at least three errors by determining roots of the error locator polynomial using a non-iterative root-finding combinatorial logic circuit, the non-iterative root-finding combinatorial logic circuit performing arithmetic operations in the finite field F(2 n ), and correcting each of the at least three errors in the received codeword.

The invention belongs to the technical field of tag systems, and provides a user-defined tag generation method and system based on a metadata configuration tag rule, and the technical scheme is as follows: constructing a database by using obtained data information of each enterprise; reading table field information based on the database, and setting a label rule based on the read table field information; the method comprises the following steps: receiving batch label generation tasks, judging an associated label rule according to the generation tasks, determining the size of a required thread pool and a thread allocation scheme based on the label rule, hardware resources of a system and the complexity of the tasks, executing the label generation tasks by each thread, and generating corresponding labels; and assembling based on the generated single label result and a set combinatorial logic relationship to obtain a composite label. The custom labels can be timely and effectively generated in batches, and the real-time data analysis requirement of an enterprise is met.

A critical path tracking system for an integrated circuit (IC) is described. The system may include a real critical path with a first set of combinatorial logic receiving data and clock inputs, generating a first output. The system may include a replica critical path with a second set of combinatorial logic replicating the first set, generating a second output. Capture flip-flops (CFFs) may be coupled to paths, capturing the first and second outputs at different points. A programmable delay element may introduce adjustable delays to the second output. A multiplexer may select between the first and delayed outputs for the CFFs, and a comparator may generate a path_failure_signature by comparing the outputs. A control circuit may dynamically adjust the delay settings and the IC's supply voltage based on the path failure signature. A software loop may read the signature, analyze timing margins, and control the circuit.

The present application relates to the field of communication technology, especially to a CRC check code generation circuit, wherein the first input end of the jth first calculation unit is used for receiving the jth data block of current data to be processed, when j=1, the second input end is used for receiving data 0, when j>1, the first input end is used for receiving the output data of the j-1th first calculation unit. The jth first calculation unit is used for generating output data, which is transmitted to the first input end of the jth exclusive or unit. The jth second calculation unit is used for generating output data, which is transmitted to the second input end of the jth exclusive or unit. The jth exclusive or unit is used for generating output data, which is transmitted to the jth input port of the J-way selector; the J-way selector is used for selecting the kth input port and outputting the CRC check code. The present application can reduce the combination logic resources occupied by the CRC check code generation circuit and improve the operation frequency of the CRC check code generation circuit.

The invention discloses a memory alloy part durability experiment data analysis method and system, relates to the technical field of data processing, and aims to solve the problem of poor alloy performance detection effect caused by environmental noise interference and signal scattering of existing memory alloy durability experiment data. A differential signal processing strategy is adopted to carry out noise reduction optimization on multi-dimensional performance response data, characteristic factors representing deformation recovery, residual deformation and energy dissipation are extracted and corrected, and combined logic of the characteristic factors is dynamically judged by combining a recognition rule set based on an application scene so as to determine a specific performance degradation mode. Corresponding residual use cycle prediction models are constructed according to different degradation modes, the credibility range is calculated, finally, a performance optimization strategy is generated through matching, and full-process closed-loop analysis from data preprocessing and feature extraction to degradation mode recognition, service life prediction and strategy generation is achieved. And the performance prediction precision and the reliability evaluation efficiency of the memory alloy part under the complex working condition are remarkably improved.

A method and system for ensuring consistency between a floating-point arithmetic algorithm verification prototype and hardware engineering, relating to the field of floating-point arithmetic, are disclosed. The method includes: obtaining the HDL source code of a hardware floating-point IP core; converting the sequential logic describing floating-point operations in the HDL source code into a behavioral-level combinational logic expression, which retains the computational logic of floating-point operations; compiling the converted HDL source code using an HDL compilation tool to generate a library file executable on a processor; calling function interfaces in the library file to perform floating-point operations in a prototype verification program running on the processor; and integrating a hardware floating-point IP core into the hardware system to implement floating-point operations, wherein the library file and the hardware floating-point IP core are based on the same HDL source code. Implementing this method can reduce the cost of ensuring consistency between the floating-point arithmetic algorithm verification prototype and hardware engineering.

The invention discloses a domestic FPGA-based complex switch control circuit and method, and the circuit comprises an FPGA minimum system circuit and a peripheral serial-parallel conversion circuit, and the FPGA minimum system circuit is connected with the peripheral serial-parallel conversion circuit. Through complex combinational logic of the multi-channel switch, control can be conveniently carried out, use of devices is reduced, the design cost of the switch is saved, due to the fact that the multi-channel switch is a domestic device, the readability of a manual is high, the function implementation difficulty can be reduced, meanwhile, the multi-channel switch has the advantages of being convenient to operate and high in response speed, and the working efficiency is greatly improved.

The application discloses a micro-vibration motor armature defect detection method and system, based on collected images, multi-scale features are extracted by using a backbone network; and the multi-scale features are fused by using a feature pyramid network (FPN); the fused features are classified and positioned by using a detector, and tin segment, boundary line and cross point auxiliary features are detected and marked; according to the auxiliary features, combined with complex combination logic conditions, effective detection of tin prying defects with high identification difficulty can be realized.

The application discloses a batch control switching method based on dynamic recombination and decoupling, comprising the following steps: step 1, constructing an extensible control unit library, wherein the control unit library comprises a plurality of independent control modules formed by abstracting the functions of physical devices; step 2, in response to a new production task request, selecting corresponding control modules from the control unit library, and performing dynamic recombination to generate a unit combination logic matched with the production task; and step 3, providing a recipe parameter set separated from the unit combination logic. Through the implementation of the application, the modular dynamic recombination of the control logic is realized, the production line can be quickly adapted to a new production task within minutes, and the problems of low switching efficiency and poor flexibility caused by unit rigidity, process and recipe coupling and chain waiting in the traditional system are fundamentally solved, and the agility and overall equipment efficiency of batch production are significantly improved.

The invention provides a synchronous time sequence sub-threshold logic circuit optimization method and device, and relates to the technical field of electronics. Converting a basic combinational logic unit in the sub-threshold logic circuit to be optimized into a sensitive amplifier-pass transistor logic circuit to form a first sub-threshold logic circuit; the sub-threshold logic circuit to be optimized is a circuit which is based on a sub-threshold digital standard cell library and is composed of a basic combinational logic unit and a trigger unit. Then determining matching device groups respectively included in a sensitive amplifier and a transmission transistor network in the sensitive amplifier-transmission transistor logic circuit, setting an incidence relation of device size parameters in each matching device group, and optimizing the device size parameters of the sensitive amplifier-transmission transistor logic circuit; and forming a second sub-threshold logic circuit. Thus, signal weakening is reduced, time delay is reduced, the working frequency of the subthreshold logic circuit is improved, and the transmission transistor network is adopted to support circuit units with unfixed logic functions.

The application discloses a view processing method, system and device based on DSL, and a storage medium, and the method comprises the following steps: constructing a DSL query statement according to view configuration information input by a user, and executing the DSL query statement to query library table data and obtain a data query result; wherein the view configuration information comprises field filtering logic information and multi-field combination logic information; matching the data query result with a preselected view component to obtain a data dimension mapping relationship; rendering the preselected view component according to the data dimension mapping relationship, and displaying a view rendering result; the application supports a user in editing filtering logic by using a natural language, and a back end automatically analyzes a word meaning to translate a DSL query statement, so that a data query result is returned based on the DSL query statement, a visual page is automatically rendered, quick view rendering is realized, a developer does not need to participate, and front-end development is reduced.

Embodiments of the present disclosure include countermeasure circuit techniques for cyberattacks. In one embodiment, portions of combinational logic receive shared input bit groups and produce shared output bit groups. Shared output bit groups may be coupled between series configured combinational logic portions using control gates. Clock signals are delayed to activate the control gates after the outputs are stable. In some embodiments, a first combinational logic group and second combinational logic group operate on a clock and inverse clock.

An embodiment of the present application provides a vulnerability scanning method, device, storage medium, and computer device. By obtaining a flow graph description, the flow graph description is compiled from the proof-of-concept names of multiple proofs-of-concept in a proof-of-concept library according to flow graph rules; converting the flow graph description into a syntax tree, the syntax tree includes the proof-of-concept names of each proof-of-concept and the execution rules between each proof-of-concept; calling each proof-of-concept for vulnerability scanning according to the execution rules in the syntax tree to obtain a scanning result. Through the flow graph description, the combined logic of multiple POCs is represented in an abstract manner of flow graph rules, so that the computer device converts the flow graph description into a syntax tree, visually presenting the execution rules between POCs in a tree form, and then sequentially calling each POC for vulnerability scanning, avoiding recompiling the POCs stored in the POC library, improving the POC reusability and vulnerability scanning efficiency.

The invention discloses a gated clock conversion method, device and system for realizing a double-edge clock selection circuit based on a frequency multiplication clock. The method comprises the following steps: acquiring design information of a to-be-converted circuit; generating a frequency multiplication clock signal based on the clock input signal; constructing a combinational logic circuit; constructing a clock enabling generation logic based on the frequency multiplication clock signal, the post comb, the pre comb, the gating signal and the edge selection signal; a clock input terminal of the timing device is connected to the frequency multiplication clock signal, and an output of the clock enable generation logic is connected to a clock enable terminal of the timing device. According to the invention, the output of the combinational logic driven by the frequency multiplication clock sampling frequency dividing circuit is utilized, so that the function of selecting the rising edge and the falling edge is realized on the clock enabling pin of the register, the clock tree on the register is very clean, the higher frequency on an FPGA (Field Programmable Gate Array) is realized, and the hold timing is easier to converge.

This application discloses a signal distortion processing method, apparatus, device, and medium, relating to the field of server design technology. Applied to complex programmable logic devices (CPLs), the method includes: debouncing and filtering a real-time acquired external signal to filter out instantaneous stray interference signals with a duration less than a filtering time threshold; performing multiple judgment processing on the debounced signal to be judged to generate multiple judgment results, including: constructing a purely digital delay circuit within the CPL for delayed judgment; repeatedly superimposing the signal to be judged onto the conditional statements of a state machine with a preset number of samplings to force the state machine to identify level signals and perform level signal superposition judgment; performing edge recognition judgment on the signal based on the global clock or frequency-divided sub-clock of the CPL; and performing combinational logic operations on the multiple judgment results to output a target valid signal. The technical solution of this application can improve the overall reliability of the server.

The invention provides a combinational logic circuit for outputting a high-voltage signal, and the circuit comprises a power circuit which is provided with a high-voltage source connected to a high voltage PH and a low-voltage source grounded, and is used for outputting a first low voltage PL1 and a second low voltage PL2; a high-voltage source of the low-voltage output signal generation circuit is connected to the first low voltage PL1, a low-voltage source of the low-voltage output signal generation circuit is grounded, and the low-voltage output signal generation circuit is used for outputting a plurality of low-voltage output signals with the same frequency and different phases according to the first low-voltage input signal SL1 and the second low-voltage input signal SL2; each high-voltage signal output circuit is provided with a first high-voltage source, a second high-voltage source, a first low-voltage source and a second low-voltage source, the first high-voltage source is connected to the high voltage PH, the second high-voltage source is connected to the first low voltage PL1, the first low-voltage source is connected to the second low voltage PL2, and the second low-voltage source is grounded; and each high-voltage signal output circuit accesses a corresponding low-voltage output signal and outputs a high-voltage signal according to the corresponding low-voltage output signal, and the high-voltage signals output by the plurality of high-voltage signal output circuits are signals with the same frequency but different phases.

The application discloses a simulation result optimization method and application in chip verification and relates to the technical field of chip development.The method comprises the following steps: starting simulation on a to-be-tested chip to generate a simulation file;forming a signal line group by grabbing the signal lines of relevant signals in the simulation file based on a specified RTL layer;packing the signal values in the signal line group to form a data packet, extracting a key data packet from the data packet, comparing the values of the signal lines in the key data packet with expected values, and / or comparing the combined logic among the multiple signal lines in the key data packet with expected signal line combined logic;and generating a key data verification result text file according to the comparison result.The application realizes automatic analysis and checking of the simulation result of the required signal within a set range, improves the simulation result checking efficiency, and reduces the labor and computing resource cost of simulation debugging.

The application discloses a Verilog RTL code reinforcing method and related equipment, relates to the programming technical field, and mainly aims at solving the problem that there is no proper reinforcing method to make the circuit resist 0 and 1 error flip. The method comprises the following steps: obtaining a time sequence logic code section of an original Verilog RTL code file containing time sequence logic; performing format identification on the time sequence logic code section to generate a time sequence logic identification version code file; determining a flip-flop code in the code section with the format identification; and adding redundant combination logic voting circuit code to the flip-flop code to reinforce the original Verilog RTL code. The application is used in the Verilog RTL code reinforcing process.