360 results about "Combinational logic" patented technology

The invention discloses an Agent-based tool combination and task processing method and device, equipment and a medium, and the method comprises the steps: carrying out the natural language processing of a task instruction inputted by a user, and generating a structured semantic vector containing task semantics; performing similarity matching on the structured semantic vector and a predefined tool node semantic tag in a knowledge base, and outputting a candidate tool node set related to the current task; performing dynamic priority ranking on the candidate tool node set based on context parameters to generate an initial thinking chain; converting the thinking chain into a tree flow chart structure, and performing dynamic addition and deletion or parameter adjustment on tool nodes in the flow chart according to a feedback or preset optimization strategy; and updating tool combinational logic according to the adjusted thinking chain, processing the task instruction, and outputting a task processing result. The tool nodes are matched through the Agent agents, and the thinking chain is generated through dynamic sorting, so that the task processing efficiency and accuracy are improved.

The invention provides an image enhancement system and method and a medium. The system comprises (N-1) row cache FIFO (First In First Out) which are connected in series, N row cache registers, a Demosaic module, a G component cache FIFO and a G component cache register. According to the invention, by reasonably controlling the read-write of the row cache FIFO and the register, at least five pixel points are output all the time under the condition that any number of pixel data is transmitted for each row of image data of each clock, so that the calculation requirement of the Demosaic algorithm is met. Under the condition of balancing and optimizing the combinational logic series to be executed in each clock period and the occupation of the total register, in the pipeline design of the Demosaic algorithm, the finiteness of hardware internal resources and the time sequence convergence problem of high clock frequency are fully considered, and by combining the combinational logic series optimization and the pipeline series optimization, the time sequence convergence problem of the high clock frequency is fully solved. In this way, better occupation of various resources of the FPGA is achieved, and efficient calculation is achieved. Based on the calculation strategy provided by the invention, the image enhancement process is finally realized, and the high-quality color display image is obtained.

A multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit.

The invention discloses a combinational logic clustering optimization method and system based on reinforcement learning. The method comprises the following steps: S1, counting fan-out information of registers and combinational logic units in a circuit netlist; s2, according to the fan-out information, screening out registers and combinational logic units of which the fan-out quantity is greater than a first preset threshold and the worst time sequence path time sequence violation value of the output signal is smaller than a second preset threshold, and generating a target unit list; s3, acquiring fan-out combinational logic information of each unit in the target unit list; s4, on the basis of the fan-out combinatorial logic information, clustering operation is carried out on fan-out logic units on the basis of a reinforcement learning algorithm; s5, after logic clustering is completed, revising the netlist of the circuit; after the revision is completed, carrying out equivalence check; and S6, rearranging and wiring the circuit according to the modified netlist. The method can effectively reduce key path delay, optimizes circuit performance, and is especially suitable for large-scale integrated circuit design.

The invention relates to the technical field of calculation, and discloses a continuous time digital Isin model hardware solver based on combinational logic, which comprises a plurality of neurons; the data initialization module is used for carrying out initialization assignment on corresponding coefficients of the hardware solver; after the control signal is used for carrying out initialization assignment on neurons, iterative calculation is started; the neuron updating module is used for carrying out matrix operation on an interaction relation weight matrix formed by the initialized weight coefficients and initialized neurons, and adding the matrix operation and bias to obtain the cumulative sum of each neuron in the current neuron state; the neuron activation module is used for adding nonlinear factors for iterative calculation; the high precision of a digital circuit is utilized, but the continuity of a physical system is also utilized at the same time, so that acceleration hardware which is lower in energy consumption and faster in digit solving is realized.

A controller for a multi-level power converter that utilizes a look-up-table (LUT) in combination with a fast flash analog-to-digital converter (ADC) circuit to implement a complex set of control states for the multi-level power converter. Since the set of control states can be pre-processed, a LUT is very well suited for such selecting such control states. This technique can be fast because the delay is only the LUT access time, rather than the propagation delay through a complex network of combinational logic. The fast flash ADC has been designed to achieve all the following: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements for properly balancing fly capacitor voltages in a multi-level converter cell.

The invention discloses a BUCK converter over-current protection circuit based on ripple V2COT control. The BUCK converter over-current protection circuit comprises a current sampling circuit, a comparator and a frequency reduction circuit which are connected in sequence. The current sampling circuit generates a sampling voltage, the current sampling circuit further comprises a reference voltage generating circuit which outputs a reference voltage and inputs the voltage and the reference voltage into a comparator for comparison to obtain an overcurrent signal, and the overcurrent signal is input into the frequency reduction circuit to generate a frequency reduction signal. Through combinational logic of a gate circuit, a frequency reduction signal is output. The ripple injection circuit is connected to the grid electrode of the MOS tube, and the output waveform of the ripple injection circuit is adjusted by controlling the on and off of the MOS tube, so that the working frequency of the system is reduced. The problem that the circuit recovery time is long after the overcurrent is eliminated is solved, the faster the circuit recovery is, the smaller the risk of element damage is, the higher the system reliability is correspondingly, and the development requirements of high reliability and safety of contemporary electronic products are met.

The invention relates to an analog quantity selection method and system based on a Boolean switch, in particular to the field of industrial automation, and aims to directly realize signal mapping by adopting a pure hardware combinational logic circuit and thoroughly eliminate instruction execution time, so that the state change of a Boolean switch signal can be instantaneously reflected on analog quantity output; according to the method, real zero-delay switching is achieved, meanwhile, program adjusting algorithms in any form are avoided, disturbance phenomena such as overshoot or undershoot are completely eradicated from the principle, and high stability and accuracy of output signals are ensured. Finally, according to the technology, the control instruction can be accurately and synchronously issued without delay, and the response speed and the synchronization precision of the whole control system in a high dynamic response industrial scene are remarkably improved.

The invention discloses a half-bridge driving circuit and method in a multi-level topology based on an FPGA (Field Programmable Gate Array), the half-bridge driving circuit comprises an MCU (Microprogrammed Control Unit), an FPGA logic circuit and a signal isolation circuit, the FPGA logic circuit gathers fault signals of other circuits in a complete machine, when other circuits fail, the circuit is notified to carry out shutdown operation, and when the other circuits fail, the FPGA logic circuit does not fail, the signal isolation circuit does not fail. In the process of switching on to switching off and the process of switching off to switching on, a transition state that switching-on voltage and switching-off voltage are invalid exists in a period of time, impact in the state switching process is solved, soft switching-off of an outer tube and an inner tube of a power main device in the multi-level topology from outside to inside is achieved in case of a fault, and soft switching-off of the outer tube and the inner tube of the power main device in the multi-level topology is achieved. The gate driver has the advantages that the gate driver is simple in structure, combinational logic and complex sequential logic functions can be realized at low cost, the signal isolation circuit is used for controlling conversion and isolation of PWM (pulse-width modulation) pulse to voltage required by gate control signals of a power device of a main circuit, peak voltage limitation and inner and outer tube switching time sequences are realized, various faults can be monitored, and fault protection can be safely implemented.

The invention discloses an oscillation detection and optimization method and system for strongly connected components of a combinational logic circuit, and the method comprises the steps: building an oscillation detection module according to an external input signal in the strongly connected components and a signal value of the signal, and building an equivalent transformation module in combination with a multiplexer; and inserting the equivalent transformation module into the nested logic ring containing the negative feedback ring to share the output end of the logic gate, and outputting the transformed netlist. According to the invention, the oscillation can be successfully detected and interrupted under the condition that the circuit oscillates, the logic function of the original circuit is not influenced under the condition that the circuit does not oscillate, and the simulation efficiency and stability of the combinational circuit are improved.

An apparatus to facilitate redundant parallel computing structures as a cache is disclosed. The apparatus includes redundant parallel computing hardware circuitry comprising redundant sets of computing combinatorial logic and register-based storage circuitry; and crossbar fabric connected to the registers of the redundant parallel computing hardware circuitry, wherein the crossbar fabric to cause register state of the register-based storage circuitry to be selected based on a tagged cache model.

The embodiment of the invention provides a connection relation establishing method and device, a storage medium and electronic device.The method comprises the steps that target combinational logic with the fan-out number meeting a preset condition is determined, and a start register, a first end point register set and a logic gate in a combinational logic path corresponding to the target combinational logic are determined; copying the start register and the logic gate to obtain a first copy register and a first copy logic gate; and establishing a first connection relationship between the first copy register and the first copy logic gate, and establishing a second connection relationship between the first copy logic gate and a first endpoint register of the first endpoint register set.

The invention discloses a digital circuit optimization method and system based on logic clustering. The method comprises the following steps: S1, counting fan-out information of all registers in a circuit netlist; s2, according to the fan-out information of the registers, screening out the registers of which the fan-out quantity is greater than a first preset threshold value and the logic series is greater than a second preset threshold value and which are located on the critical path, and generating a candidate register list; s3, obtaining register fan-out first-level combinatorial logic information; s4, performing clustering operation on the logic units based on the first-level combinational logic information, and dividing physically adjacent logic units into the same cluster according to the physical position relationship of the logic units; s5, associating the clustered logic units together and adjusting the connection relation of the logic units; s6, carrying out equivalence check; and S7, rearranging and wiring the circuit according to the modified netlist. The physical distance of a time sequence path can be effectively reduced, the time sequence performance of the circuit is optimized, and the method is suitable for large-scale integrated circuit design.

The invention belongs to the field of integrated circuit design, and provides a novel transaction ID coding method applied to an AXI protocol. Address decoding is carried out in advance in an AXI host interface, gating signals of all slaves are compiled into transaction IDs in a one-hot code mode, and therefore coding of all transaction IDs can be completed in the host interface instead of expanding the bit width of ID coding step by step in next-level interconnection. The address decoder is located on the critical path of the interconnection matrix in a traditional interconnection architecture, the address decoder is moved into the host interface, the delay of the critical path in the interconnection matrix is shortened, the dominant frequency of the system can be improved, address decoding is not needed in the interconnection matrix any more, combinational logic in the interconnection matrix can be simplified, and the system reliability is improved. The design complexity is reduced, meanwhile, the data cache position needing to be returned in an order-preserving mode can be closer to a host end, the memory access efficiency is improved, and the problem of a memory wall is effectively relieved.

The subject matter of the invention is a redundant parallel computing structure as a cache. An apparatus for facilitating a redundant parallel computing fabric as a cache is disclosed. The device comprises a redundant parallel computing hardware circuit module, wherein the redundant parallel computing hardware circuit module comprises computing combinatorial logic and a redundant set of register-based storage circuit modules; and a crossbar fabric connected to the registers of the redundant parallel computing hardware circuit module, where the crossbar fabric is to cause the tag-based cache model to select the register state of the register-based memory circuit module.

The invention relates to the technical field of multi-scene dynamic orchestration, in particular to a multi-scene-based orchestrable unified preprocessing rule method and system, and the method comprises the steps: carrying out the dynamic matching of a rule according to scene information, employing a visual rule orchestration engine, and employing a micro-service architecture design; the method has the beneficial effects that different service scenes can be covered through the modular rule base and the dynamic configuration capability, repeated development of a traditional single scene preprocessing system is avoided, and the technology reuse rate is improved. Visual flow arrangement is adopted, a user is allowed to customize a rule execution sequence, conditional branches and combinatorial logic, complex business demand changes are flexibly dealt with, and the technology coupling degree is reduced.

The embodiment of the invention provides a vulnerability scanning method and device, a storage medium and computer equipment, and the method comprises the steps: obtaining a flow graph description which is obtained by compiling the concept verification names of a plurality of concept verifications in a concept verification library according to a flow graph rule; converting the flow graph description into a syntax tree, wherein the syntax tree comprises a concept verification name of each concept verification and an execution rule between the concept verifications; and calling each concept verification according to an execution rule in the syntax tree to perform vulnerability scanning to obtain a scanning result, and expressing combinational logic of a plurality of POCs in an abstract mode of a flow graph rule through flow graph description, so that the computer equipment converts the flow graph description into the syntax tree, and performs vulnerability scanning on the syntax tree. According to the method, the execution rule between the POCs is visually presented in a tree form, so that each POC is called in sequence for vulnerability scanning, the POCs stored in a POC library are prevented from being recompiled, and the POC reusability and vulnerability scanning efficiency are improved.

The invention relates to a current source inverter short circuit fault diagnosis method based on phase current and average absolute value mixed error thereof. The invention relates to the technical field of motor control, and the method comprises the steps: collecting the A, B and C three-phase current of a permanent magnet synchronous motor in real time in a process that a current source inverter drives the permanent magnet synchronous motor to operate, and carrying out the filtering and noise reduction of the A, B and C three-phase current; a Park vector module value is obtained through Park transformation, and the three-phase current is divided by the Park vector module value to carry out normalization processing on the phase current; generating a hybrid diagnosis variable and an auxiliary diagnosis variable based on the reference current and actual current error and the average absolute value and average value error of the normalized current; and in combination with a preset threshold value and variable combinational logic, precise positioning of single-tube short circuit, same-side out-of-phase double-tube short circuit and different-side out-of-phase double-tube short circuit is realized.

The invention discloses a self-service door opening method for a store, and relates to the technical field of self-service stores. The system carries out intelligent matching according to a pre-stored user file, calculates a similarity threshold value through an algorithm, judges that a user is a legal user if the matching degree exceeds a preset value, or rejects access; a dynamic combination strategy is adopted to allow an administrator to configure weights and combination modes of different fields according to the security requirements of the store, so that the user experience is optimized and the privacy leakage risk is reduced on the premise of ensuring the security; a background management system flexibly sets a weight value and combinatorial logic of each verification element, the matching efficiency is dynamically optimized based on a preset similarity threshold, if a comprehensive score after element combination reaches a security level score configured by the system, rapid door opening is automatically authorized, otherwise, secondary verification or manual auditing is triggered, and the safety of the system is ensured. The false rejection rate is reduced, the safety protection capability is improved, the verification modes are automatically switched according to regions or time periods, and the door opening speed is high when the operation is successful.

The invention discloses a carry chain test circuit and a test method, the test circuit comprises N test units with the same structure, and each test unit is composed of a reconfigurable combinational logic, a carry chain, an output selection circuit and an assembly line. According to the test method, a test process covering fixed faults and element functions of each node of the carry chain is preset and configured, and a general modular test circuit design is adopted, so that when a large number of carry chain units need to be tested, only the test circuits need to be logically copied and then combined into a test link.

The invention provides a power consumption optimization method, an integrated circuit and a chip. The method comprises the following steps: acquiring a first endpoint register with a time sequence violation in a load register based on a time sequence report of EDA (Electronic Design Automation); obtaining all first load registers driven by the ICG; acquiring a second endpoint register driven by the ICG and limiting the overall performance of the circuit according to the first load register and the first endpoint register; dividing each load register into a plurality of register files which are not mutually coherent logically according to combinational logic; and copying one ICG for each register file to drive the CP end of each load register in the register file. According to the scheme, the ICG copying function of the EDA tool is utilized, ICG copying and placement of the key registers influencing the overall performance of the circuit are achieved, and the time sequence of the path between the load registers can be optimized to the limit on the premise that the process complexity is not increased and the power consumption of the integrated circuit is saved.

The invention discloses a single-phase photovoltaic energy storage inverter parallel operation system relay fault detection method. The method comprises the following steps of determining a relay detection sequence according to configuration of a master machine and a slave machine; obtaining an absolute value of a difference value between the grid-connected port voltage effective value and the load port voltage effective value, comparing the absolute value with a preset first threshold value, and selecting a corresponding relay detection logic; the photovoltaic energy storage inverter unit is controlled to output open-loop voltage, the turn-on and turn-off sequence of the corresponding relays is controlled, and whether each relay has a sticking fault or a non-closing fault or not is detected in combination with a voltage judgment result. According to the method, all-working-condition adaptation of all-unit detection before grid connection of the parallel operation system, independent detection of a new machine and a reconnected slave machine in operation and all-unit re-detection after failure recovery of a host is met, and the detection problem in a dynamic adjustment scene of the parallel operation system is solved. Through the combinational logic of voltage threshold judgment and relay action time sequence control, the faults that the relay is stuck and cannot be closed can be accurately recognized, and missing detection and false detection are avoided.

The invention discloses a universal multiphase clock generation circuit and a combinational logic circuit thereof. The combinational logic circuit comprises a first-stage NAND gate and a second-stage NAND gate which are cascaded, the generation circuit is constructed by taking the combinational logic circuit as a basic unit; the generation circuit is a closed loop formed by connecting 2N basic units end to end; the first-stage NAND gates of the odd-numbered basic units form latches pairwise, and the first-stage NAND gates of the even-numbered basic units also form latches pairwise; each basic unit takes the output of the adjacent previous basic unit as the input and outputs a basic clock signal with a preset duty ratio based on a preset selection signal; performing odd number of times of phase inversion on the 2N basic clock signals output by the 2N basic units to obtain 2N-phase non-overlapping clock signals; and when N is an odd number, performing NAND operation on the N groups of adjacent two basic clock signals to obtain N-phase non-overlapping clock signals.

Receiving a codeword of a forward error correction (FEC) code, each codeword in the FEC code having a minimum distance of at least seven to any other codeword in the FEC code, calculating multi-bit syndromes by applying columns of a check matrix to the received codeword using combinatorial logic, and responsively determining the received codeword comprises at least three errors, determining coefficients of an error locator polynomial using a coefficient combinatorial logic circuit by combining the multi-bit syndromes using non-iterative combinatorial logic performing arithmetic operations in a finite field F(2 n ), determining respective error positions for each error of the at least three errors by determining roots of the error locator polynomial using a non-iterative root-finding combinatorial logic circuit, the non-iterative root-finding combinatorial logic circuit performing arithmetic operations in the finite field F(2 n ), and correcting each of the at least three errors in the received codeword.

The invention belongs to the technical field of tag systems, and provides a user-defined tag generation method and system based on a metadata configuration tag rule, and the technical scheme is as follows: constructing a database by using obtained data information of each enterprise; reading table field information based on the database, and setting a label rule based on the read table field information; the method comprises the following steps: receiving batch label generation tasks, judging an associated label rule according to the generation tasks, determining the size of a required thread pool and a thread allocation scheme based on the label rule, hardware resources of a system and the complexity of the tasks, executing the label generation tasks by each thread, and generating corresponding labels; and assembling based on the generated single label result and a set combinatorial logic relationship to obtain a composite label. The custom labels can be timely and effectively generated in batches, and the real-time data analysis requirement of an enterprise is met.

A critical path tracking system for an integrated circuit (IC) is described. The system may include a real critical path with a first set of combinatorial logic receiving data and clock inputs, generating a first output. The system may include a replica critical path with a second set of combinatorial logic replicating the first set, generating a second output. Capture flip-flops (CFFs) may be coupled to paths, capturing the first and second outputs at different points. A programmable delay element may introduce adjustable delays to the second output. A multiplexer may select between the first and delayed outputs for the CFFs, and a comparator may generate a path_failure_signature by comparing the outputs. A control circuit may dynamically adjust the delay settings and the IC's supply voltage based on the path failure signature. A software loop may read the signature, analyze timing margins, and control the circuit.

In the conventional eFPGAs, there have been two challenges: the first one being size reduction of the logic cells to improve the implemented logic density, and the second one being minimization of the speed difference with the ASIC. According to the present embodiment, there is provided a method for configuring a programmable logic circuit represented by a gate-level netlist, wherein this is done by assigning the gate-level netlist to a 4-input, 3-output combinational logic cell, which is composed of a combination of 3 of 2-input (m-input) basic logic cells, wherein the combinational logic cell covers 3 (n) nodes constituting a graph of the netlist.

The present application relates to the field of communication technology, especially to a CRC check code generation circuit, wherein the first input end of the jth first calculation unit is used for receiving the jth data block of current data to be processed, when j=1, the second input end is used for receiving data 0, when j>1, the first input end is used for receiving the output data of the j-1th first calculation unit. The jth first calculation unit is used for generating output data, which is transmitted to the first input end of the jth exclusive or unit. The jth second calculation unit is used for generating output data, which is transmitted to the second input end of the jth exclusive or unit. The jth exclusive or unit is used for generating output data, which is transmitted to the jth input port of the J-way selector; the J-way selector is used for selecting the kth input port and outputting the CRC check code. The present application can reduce the combination logic resources occupied by the CRC check code generation circuit and improve the operation frequency of the CRC check code generation circuit.

The invention discloses a memory alloy part durability experiment data analysis method and system, relates to the technical field of data processing, and aims to solve the problem of poor alloy performance detection effect caused by environmental noise interference and signal scattering of existing memory alloy durability experiment data. A differential signal processing strategy is adopted to carry out noise reduction optimization on multi-dimensional performance response data, characteristic factors representing deformation recovery, residual deformation and energy dissipation are extracted and corrected, and combined logic of the characteristic factors is dynamically judged by combining a recognition rule set based on an application scene so as to determine a specific performance degradation mode. Corresponding residual use cycle prediction models are constructed according to different degradation modes, the credibility range is calculated, finally, a performance optimization strategy is generated through matching, and full-process closed-loop analysis from data preprocessing and feature extraction to degradation mode recognition, service life prediction and strategy generation is achieved. And the performance prediction precision and the reliability evaluation efficiency of the memory alloy part under the complex working condition are remarkably improved.

A method and system for ensuring consistency between a floating-point arithmetic algorithm verification prototype and hardware engineering, relating to the field of floating-point arithmetic, are disclosed. The method includes: obtaining the HDL source code of a hardware floating-point IP core; converting the sequential logic describing floating-point operations in the HDL source code into a behavioral-level combinational logic expression, which retains the computational logic of floating-point operations; compiling the converted HDL source code using an HDL compilation tool to generate a library file executable on a processor; calling function interfaces in the library file to perform floating-point operations in a prototype verification program running on the processor; and integrating a hardware floating-point IP core into the hardware system to implement floating-point operations, wherein the library file and the hardware floating-point IP core are based on the same HDL source code. Implementing this method can reduce the cost of ensuring consistency between the floating-point arithmetic algorithm verification prototype and hardware engineering.