219 results about "Combinational logic" patented technology

The invention relates to an analog quantity selection method and system based on a Boolean switch, in particular to the field of industrial automation, and aims to directly realize signal mapping by adopting a pure hardware combinational logic circuit and thoroughly eliminate instruction execution time, so that the state change of a Boolean switch signal can be instantaneously reflected on analog quantity output; according to the method, real zero-delay switching is achieved, meanwhile, program adjusting algorithms in any form are avoided, disturbance phenomena such as overshoot or undershoot are completely eradicated from the principle, and high stability and accuracy of output signals are ensured. Finally, according to the technology, the control instruction can be accurately and synchronously issued without delay, and the response speed and the synchronization precision of the whole control system in a high dynamic response industrial scene are remarkably improved.

An apparatus to facilitate redundant parallel computing structures as a cache is disclosed. The apparatus includes redundant parallel computing hardware circuitry comprising redundant sets of computing combinatorial logic and register-based storage circuitry; and crossbar fabric connected to the registers of the redundant parallel computing hardware circuitry, wherein the crossbar fabric to cause register state of the register-based storage circuitry to be selected based on a tagged cache model.

The subject matter of the invention is a redundant parallel computing structure as a cache. An apparatus for facilitating a redundant parallel computing fabric as a cache is disclosed. The device comprises a redundant parallel computing hardware circuit module, wherein the redundant parallel computing hardware circuit module comprises computing combinatorial logic and a redundant set of register-based storage circuit modules; and a crossbar fabric connected to the registers of the redundant parallel computing hardware circuit module, where the crossbar fabric is to cause the tag-based cache model to select the register state of the register-based memory circuit module.

The invention relates to the technical field of multi-scene dynamic orchestration, in particular to a multi-scene-based orchestrable unified preprocessing rule method and system, and the method comprises the steps: carrying out the dynamic matching of a rule according to scene information, employing a visual rule orchestration engine, and employing a micro-service architecture design; the method has the beneficial effects that different service scenes can be covered through the modular rule base and the dynamic configuration capability, repeated development of a traditional single scene preprocessing system is avoided, and the technology reuse rate is improved. Visual flow arrangement is adopted, a user is allowed to customize a rule execution sequence, conditional branches and combinatorial logic, complex business demand changes are flexibly dealt with, and the technology coupling degree is reduced.

The invention relates to a current source inverter short circuit fault diagnosis method based on phase current and average absolute value mixed error thereof. The invention relates to the technical field of motor control, and the method comprises the steps: collecting the A, B and C three-phase current of a permanent magnet synchronous motor in real time in a process that a current source inverter drives the permanent magnet synchronous motor to operate, and carrying out the filtering and noise reduction of the A, B and C three-phase current; a Park vector module value is obtained through Park transformation, and the three-phase current is divided by the Park vector module value to carry out normalization processing on the phase current; generating a hybrid diagnosis variable and an auxiliary diagnosis variable based on the reference current and actual current error and the average absolute value and average value error of the normalized current; and in combination with a preset threshold value and variable combinational logic, precise positioning of single-tube short circuit, same-side out-of-phase double-tube short circuit and different-side out-of-phase double-tube short circuit is realized.

The invention discloses a self-service door opening method for a store, and relates to the technical field of self-service stores. The system carries out intelligent matching according to a pre-stored user file, calculates a similarity threshold value through an algorithm, judges that a user is a legal user if the matching degree exceeds a preset value, or rejects access; a dynamic combination strategy is adopted to allow an administrator to configure weights and combination modes of different fields according to the security requirements of the store, so that the user experience is optimized and the privacy leakage risk is reduced on the premise of ensuring the security; a background management system flexibly sets a weight value and combinatorial logic of each verification element, the matching efficiency is dynamically optimized based on a preset similarity threshold, if a comprehensive score after element combination reaches a security level score configured by the system, rapid door opening is automatically authorized, otherwise, secondary verification or manual auditing is triggered, and the safety of the system is ensured. The false rejection rate is reduced, the safety protection capability is improved, the verification modes are automatically switched according to regions or time periods, and the door opening speed is high when the operation is successful.

The invention discloses a single-phase photovoltaic energy storage inverter parallel operation system relay fault detection method. The method comprises the following steps of determining a relay detection sequence according to configuration of a master machine and a slave machine; obtaining an absolute value of a difference value between the grid-connected port voltage effective value and the load port voltage effective value, comparing the absolute value with a preset first threshold value, and selecting a corresponding relay detection logic; the photovoltaic energy storage inverter unit is controlled to output open-loop voltage, the turn-on and turn-off sequence of the corresponding relays is controlled, and whether each relay has a sticking fault or a non-closing fault or not is detected in combination with a voltage judgment result. According to the method, all-working-condition adaptation of all-unit detection before grid connection of the parallel operation system, independent detection of a new machine and a reconnected slave machine in operation and all-unit re-detection after failure recovery of a host is met, and the detection problem in a dynamic adjustment scene of the parallel operation system is solved. Through the combinational logic of voltage threshold judgment and relay action time sequence control, the faults that the relay is stuck and cannot be closed can be accurately recognized, and missing detection and false detection are avoided.

Receiving a codeword of a forward error correction (FEC) code, each codeword in the FEC code having a minimum distance of at least seven to any other codeword in the FEC code, calculating multi-bit syndromes by applying columns of a check matrix to the received codeword using combinatorial logic, and responsively determining the received codeword comprises at least three errors, determining coefficients of an error locator polynomial using a coefficient combinatorial logic circuit by combining the multi-bit syndromes using non-iterative combinatorial logic performing arithmetic operations in a finite field F(2 n ), determining respective error positions for each error of the at least three errors by determining roots of the error locator polynomial using a non-iterative root-finding combinatorial logic circuit, the non-iterative root-finding combinatorial logic circuit performing arithmetic operations in the finite field F(2 n ), and correcting each of the at least three errors in the received codeword.

A critical path tracking system for an integrated circuit (IC) is described. The system may include a real critical path with a first set of combinatorial logic receiving data and clock inputs, generating a first output. The system may include a replica critical path with a second set of combinatorial logic replicating the first set, generating a second output. Capture flip-flops (CFFs) may be coupled to paths, capturing the first and second outputs at different points. A programmable delay element may introduce adjustable delays to the second output. A multiplexer may select between the first and delayed outputs for the CFFs, and a comparator may generate a path_failure_signature by comparing the outputs. A control circuit may dynamically adjust the delay settings and the IC's supply voltage based on the path failure signature. A software loop may read the signature, analyze timing margins, and control the circuit.

The present application relates to the field of communication technology, especially to a CRC check code generation circuit, wherein the first input end of the jth first calculation unit is used for receiving the jth data block of current data to be processed, when j=1, the second input end is used for receiving data 0, when j>1, the first input end is used for receiving the output data of the j-1th first calculation unit. The jth first calculation unit is used for generating output data, which is transmitted to the first input end of the jth exclusive or unit. The jth second calculation unit is used for generating output data, which is transmitted to the second input end of the jth exclusive or unit. The jth exclusive or unit is used for generating output data, which is transmitted to the jth input port of the J-way selector; the J-way selector is used for selecting the kth input port and outputting the CRC check code. The present application can reduce the combination logic resources occupied by the CRC check code generation circuit and improve the operation frequency of the CRC check code generation circuit.

The invention discloses a memory alloy part durability experiment data analysis method and system, relates to the technical field of data processing, and aims to solve the problem of poor alloy performance detection effect caused by environmental noise interference and signal scattering of existing memory alloy durability experiment data. A differential signal processing strategy is adopted to carry out noise reduction optimization on multi-dimensional performance response data, characteristic factors representing deformation recovery, residual deformation and energy dissipation are extracted and corrected, and combined logic of the characteristic factors is dynamically judged by combining a recognition rule set based on an application scene so as to determine a specific performance degradation mode. Corresponding residual use cycle prediction models are constructed according to different degradation modes, the credibility range is calculated, finally, a performance optimization strategy is generated through matching, and full-process closed-loop analysis from data preprocessing and feature extraction to degradation mode recognition, service life prediction and strategy generation is achieved. And the performance prediction precision and the reliability evaluation efficiency of the memory alloy part under the complex working condition are remarkably improved.

A method and system for ensuring consistency between a floating-point arithmetic algorithm verification prototype and hardware engineering, relating to the field of floating-point arithmetic, are disclosed. The method includes: obtaining the HDL source code of a hardware floating-point IP core; converting the sequential logic describing floating-point operations in the HDL source code into a behavioral-level combinational logic expression, which retains the computational logic of floating-point operations; compiling the converted HDL source code using an HDL compilation tool to generate a library file executable on a processor; calling function interfaces in the library file to perform floating-point operations in a prototype verification program running on the processor; and integrating a hardware floating-point IP core into the hardware system to implement floating-point operations, wherein the library file and the hardware floating-point IP core are based on the same HDL source code. Implementing this method can reduce the cost of ensuring consistency between the floating-point arithmetic algorithm verification prototype and hardware engineering.

The application discloses a micro-vibration motor armature defect detection method and system, based on collected images, multi-scale features are extracted by using a backbone network; and the multi-scale features are fused by using a feature pyramid network (FPN); the fused features are classified and positioned by using a detector, and tin segment, boundary line and cross point auxiliary features are detected and marked; according to the auxiliary features, combined with complex combination logic conditions, effective detection of tin prying defects with high identification difficulty can be realized.

The application discloses a batch control switching method based on dynamic recombination and decoupling, comprising the following steps: step 1, constructing an extensible control unit library, wherein the control unit library comprises a plurality of independent control modules formed by abstracting the functions of physical devices; step 2, in response to a new production task request, selecting corresponding control modules from the control unit library, and performing dynamic recombination to generate a unit combination logic matched with the production task; and step 3, providing a recipe parameter set separated from the unit combination logic. Through the implementation of the application, the modular dynamic recombination of the control logic is realized, the production line can be quickly adapted to a new production task within minutes, and the problems of low switching efficiency and poor flexibility caused by unit rigidity, process and recipe coupling and chain waiting in the traditional system are fundamentally solved, and the agility and overall equipment efficiency of batch production are significantly improved.

The invention provides a synchronous time sequence sub-threshold logic circuit optimization method and device, and relates to the technical field of electronics. Converting a basic combinational logic unit in the sub-threshold logic circuit to be optimized into a sensitive amplifier-pass transistor logic circuit to form a first sub-threshold logic circuit; the sub-threshold logic circuit to be optimized is a circuit which is based on a sub-threshold digital standard cell library and is composed of a basic combinational logic unit and a trigger unit. Then determining matching device groups respectively included in a sensitive amplifier and a transmission transistor network in the sensitive amplifier-transmission transistor logic circuit, setting an incidence relation of device size parameters in each matching device group, and optimizing the device size parameters of the sensitive amplifier-transmission transistor logic circuit; and forming a second sub-threshold logic circuit. Thus, signal weakening is reduced, time delay is reduced, the working frequency of the subthreshold logic circuit is improved, and the transmission transistor network is adopted to support circuit units with unfixed logic functions.

The application discloses a view processing method, system and device based on DSL, and a storage medium, and the method comprises the following steps: constructing a DSL query statement according to view configuration information input by a user, and executing the DSL query statement to query library table data and obtain a data query result; wherein the view configuration information comprises field filtering logic information and multi-field combination logic information; matching the data query result with a preselected view component to obtain a data dimension mapping relationship; rendering the preselected view component according to the data dimension mapping relationship, and displaying a view rendering result; the application supports a user in editing filtering logic by using a natural language, and a back end automatically analyzes a word meaning to translate a DSL query statement, so that a data query result is returned based on the DSL query statement, a visual page is automatically rendered, quick view rendering is realized, a developer does not need to participate, and front-end development is reduced.

Embodiments of the present disclosure include countermeasure circuit techniques for cyberattacks. In one embodiment, portions of combinational logic receive shared input bit groups and produce shared output bit groups. Shared output bit groups may be coupled between series configured combinational logic portions using control gates. Clock signals are delayed to activate the control gates after the outputs are stable. In some embodiments, a first combinational logic group and second combinational logic group operate on a clock and inverse clock.

The invention discloses a gated clock conversion method, device and system for realizing a double-edge clock selection circuit based on a frequency multiplication clock. The method comprises the following steps: acquiring design information of a to-be-converted circuit; generating a frequency multiplication clock signal based on the clock input signal; constructing a combinational logic circuit; constructing a clock enabling generation logic based on the frequency multiplication clock signal, the post comb, the pre comb, the gating signal and the edge selection signal; a clock input terminal of the timing device is connected to the frequency multiplication clock signal, and an output of the clock enable generation logic is connected to a clock enable terminal of the timing device. According to the invention, the output of the combinational logic driven by the frequency multiplication clock sampling frequency dividing circuit is utilized, so that the function of selecting the rising edge and the falling edge is realized on the clock enabling pin of the register, the clock tree on the register is very clean, the higher frequency on an FPGA (Field Programmable Gate Array) is realized, and the hold timing is easier to converge.

This application discloses a signal distortion processing method, apparatus, device, and medium, relating to the field of server design technology. Applied to complex programmable logic devices (CPLs), the method includes: debouncing and filtering a real-time acquired external signal to filter out instantaneous stray interference signals with a duration less than a filtering time threshold; performing multiple judgment processing on the debounced signal to be judged to generate multiple judgment results, including: constructing a purely digital delay circuit within the CPL for delayed judgment; repeatedly superimposing the signal to be judged onto the conditional statements of a state machine with a preset number of samplings to force the state machine to identify level signals and perform level signal superposition judgment; performing edge recognition judgment on the signal based on the global clock or frequency-divided sub-clock of the CPL; and performing combinational logic operations on the multiple judgment results to output a target valid signal. The technical solution of this application can improve the overall reliability of the server.

The application discloses a simulation result optimization method and application in chip verification and relates to the technical field of chip development.The method comprises the following steps: starting simulation on a to-be-tested chip to generate a simulation file;forming a signal line group by grabbing the signal lines of relevant signals in the simulation file based on a specified RTL layer;packing the signal values in the signal line group to form a data packet, extracting a key data packet from the data packet, comparing the values of the signal lines in the key data packet with expected values, and / or comparing the combined logic among the multiple signal lines in the key data packet with expected signal line combined logic;and generating a key data verification result text file according to the comparison result.The application realizes automatic analysis and checking of the simulation result of the required signal within a set range, improves the simulation result checking efficiency, and reduces the labor and computing resource cost of simulation debugging.

The application discloses a Verilog RTL code reinforcing method and related equipment, relates to the programming technical field, and mainly aims at solving the problem that there is no proper reinforcing method to make the circuit resist 0 and 1 error flip. The method comprises the following steps: obtaining a time sequence logic code section of an original Verilog RTL code file containing time sequence logic; performing format identification on the time sequence logic code section to generate a time sequence logic identification version code file; determining a flip-flop code in the code section with the format identification; and adding redundant combination logic voting circuit code to the flip-flop code to reinforce the original Verilog RTL code. The application is used in the Verilog RTL code reinforcing process.

The present invention discloses a two-dimensional AMR sensor switch chip signal architecture and detection method. In the signal circuit architecture, the clock signal output terminal of the fast clock circuit is connected to the clock signal input terminal of the first combinational logic operation module and the clock signal input terminal of the second combinational logic operation module, and the clock signal output terminal of the slow clock circuit is connected to the clock signal input terminal of the first combinational logic operation module; the first combinational logic operation module outputs an X-direction sampling signal, a Y-direction sampling signal, and a detection enable signal, and the second combinational logic operation module outputs a comparator enable signal, a chopping signal, and an XY-direction switching signal. Chopping offset cancellation technology is used to improve detection accuracy, and time-division multiplexing technology is used to share a processing signal chain, achieving low-power two-dimensional signal acquisition and detection in the X and Y directions, and flexible switching of directions according to actual needs.

The application discloses a digital processing circuit, comprising a logic unit, at least one combinational logic device, the combinational logic device comprising at least one input terminal; a filter unit is used to divide the waveform of the received initial input signal into at least two segments of waveforms within a cycle of the clock signal of the combinational logic device, and to prevent the back propagation of glitches contained in at least one segment of waveforms, so as to provide a filtered input signal to the input terminal of the combinational logic device. By preventing the back propagation of the glitches contained in at least one segment of waveforms in the initial input signal through the filter unit, the application can eliminate the influence of the glitches in the signal on the power consumption of the entire circuit in time, so as to effectively reduce the additional power consumption caused by the glitches.

To provide a semiconductor device capable of recovering changes in transistor characteristics due to BTI.SOLUTION: A semiconductor device 11 includes: a control input 13 receiving a control signal SCNT; one or more signal inputs 15; a BTI avoidance circuit 19 including a plurality of inputs and one or more outputs and configured to receive signals from the signal inputs 15 and the control inputs 13; and a combination logic circuit 17 including an input connected to the signal inputs 15 via the BTI avoidance circuit 19 and at least one output. The BTI avoidance circuit 19 includes at least one exclusive OR gate 21. The exclusive OR gate 21 receives signals from the control input 13, and the excluding OR gate 21 receives signals from the signal inputs 15 and provides output signals to one of the outputs of the BTI avoidance circuit 19 in response to the received signals.SELECTED DRAWING: Figure 1

The application provides a multi-application combined compilation method and system. The method comprises the following steps: obtaining a global configuration of a total project and a module configuration of an application module; configuring a first construction rule of a main module and a second construction rule of an application logic module based on the global configuration, the module configuration and a type identifier of the application module; scanning the application logic module, extracting first combination information and first dependency information of a plurality of first logic components in the application logic module; analyzing a first dependency relationship of the plurality of first logic components based on the first combination information and the first dependency information; determining an initialization sequence of a target logic component based on the first dependency relationship, the target logic component comprising the first logic component; inserting a custom compilation stage in a standard compilation process, and generating combined logic code for sequentially calling the target logic component based on the initialization sequence. The application realizes combined compilation of multi-application through custom configuration and compilation process, and improves the running efficiency of a device.

The invention provides a method and device for determining a target group, electronic equipment and a storage medium, and relates to the technical field of artificial intelligence, in particular to the fields of large models, generative models, resource recommendation and the like. The specific implementation scheme is as follows: determining at least one target screening tool in a plurality of candidate screening tools and at least one reference screening rule for the at least one target screening tool by utilizing a large model according to description information of the plurality of candidate screening tools and a historical context comprising demand information; calling at least one target screening tool by utilizing at least one reference screening rule to obtain at least one label expression; according to combinational logic, processing each label in the at least one label expression into a target screening rule; and determining a target group from the plurality of candidate objects according to a target screening rule.

This invention discloses a low-scan-power scanning unit and scanning chain, belonging to the field of integrated circuit design-for-test (DTBT). The invention uses a low-scan-power scanning unit, adding an OR gate to control the switching activity of two tri-state gates in the secondary latch unit during the scanning phase, and using a high-threshold PMOS as a power supply gating to control the power supply VDD of the two inverters inside the secondary latch unit, thus reducing the dynamic power consumption of the secondary latch and unnecessary dynamic power consumption of the combinational logic during the scanning phase. Additionally, a test vector output port P is added, whose signal originates from the output of the primary latch unit inside the scanning unit, reducing the transmission path delay during the scanning phase. This invention is applicable to the DTBT stage of digital circuits; by simply adding an OR gate and a high-threshold PMOS, without affecting the original logic circuit function, it achieves the goal of reducing dynamic power consumption during the shift phase.

A controller for a multi-level power converter that utilizes a look-up-table (LUT) in combination with a fast flash analog-to-digital converter (ADC) circuit to implement a complex set of control states for the multi-level power converter. Since the set of control states can be pre-processed, a LUT is very well suited for such selecting such control states. This technique can be fast because the delay is only the LUT access time, rather than the propagation delay through a complex network of combinational logic. The fast flash ADC has been designed to achieve all the following: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements for properly balancing fly capacitor voltages in a multi-level converter cell.

This application provides a DWA algorithm implementation circuit and an analog-to-digital converter. The DWA algorithm implementation circuit includes a shifter and a combinational logic circuit. The shifter's data input terminal receives thermometer codes output by a quantizer based on a first clock control signal; the shifter's data output terminal is connected to the input terminal of the combinational logic circuit and serves as the output terminal of the DWA algorithm implementation circuit; the combinational logic circuit concatenates the thermometer codes output by the shifter and performs combinational logic operations on the concatenated thermometer codes to generate a shift indication signal for the shifter; the shifter performs shift operations based on the shift indication signal. This application significantly simplifies the circuit structure, saves circuit area, and reduces circuit cost; simultaneously, it improves circuit speed and increases its flexibility.