154 results about "Combinational logic" patented technology

The invention relates to an analog quantity selection method and system based on a Boolean switch, in particular to the field of industrial automation, and aims to directly realize signal mapping by adopting a pure hardware combinational logic circuit and thoroughly eliminate instruction execution time, so that the state change of a Boolean switch signal can be instantaneously reflected on analog quantity output; according to the method, real zero-delay switching is achieved, meanwhile, program adjusting algorithms in any form are avoided, disturbance phenomena such as overshoot or undershoot are completely eradicated from the principle, and high stability and accuracy of output signals are ensured. Finally, according to the technology, the control instruction can be accurately and synchronously issued without delay, and the response speed and the synchronization precision of the whole control system in a high dynamic response industrial scene are remarkably improved.

A critical path tracking system for an integrated circuit (IC) is described. The system may include a real critical path with a first set of combinatorial logic receiving data and clock inputs, generating a first output. The system may include a replica critical path with a second set of combinatorial logic replicating the first set, generating a second output. Capture flip-flops (CFFs) may be coupled to paths, capturing the first and second outputs at different points. A programmable delay element may introduce adjustable delays to the second output. A multiplexer may select between the first and delayed outputs for the CFFs, and a comparator may generate a path_failure_signature by comparing the outputs. A control circuit may dynamically adjust the delay settings and the IC's supply voltage based on the path failure signature. A software loop may read the signature, analyze timing margins, and control the circuit.

The present application relates to the field of communication technology, especially to a CRC check code generation circuit, wherein the first input end of the jth first calculation unit is used for receiving the jth data block of current data to be processed, when j=1, the second input end is used for receiving data 0, when j>1, the first input end is used for receiving the output data of the j-1th first calculation unit. The jth first calculation unit is used for generating output data, which is transmitted to the first input end of the jth exclusive or unit. The jth second calculation unit is used for generating output data, which is transmitted to the second input end of the jth exclusive or unit. The jth exclusive or unit is used for generating output data, which is transmitted to the jth input port of the J-way selector; the J-way selector is used for selecting the kth input port and outputting the CRC check code. The present application can reduce the combination logic resources occupied by the CRC check code generation circuit and improve the operation frequency of the CRC check code generation circuit.

The invention discloses a memory alloy part durability experiment data analysis method and system, relates to the technical field of data processing, and aims to solve the problem of poor alloy performance detection effect caused by environmental noise interference and signal scattering of existing memory alloy durability experiment data. A differential signal processing strategy is adopted to carry out noise reduction optimization on multi-dimensional performance response data, characteristic factors representing deformation recovery, residual deformation and energy dissipation are extracted and corrected, and combined logic of the characteristic factors is dynamically judged by combining a recognition rule set based on an application scene so as to determine a specific performance degradation mode. Corresponding residual use cycle prediction models are constructed according to different degradation modes, the credibility range is calculated, finally, a performance optimization strategy is generated through matching, and full-process closed-loop analysis from data preprocessing and feature extraction to degradation mode recognition, service life prediction and strategy generation is achieved. And the performance prediction precision and the reliability evaluation efficiency of the memory alloy part under the complex working condition are remarkably improved.

A method and system for ensuring consistency between a floating-point arithmetic algorithm verification prototype and hardware engineering, relating to the field of floating-point arithmetic, are disclosed. The method includes: obtaining the HDL source code of a hardware floating-point IP core; converting the sequential logic describing floating-point operations in the HDL source code into a behavioral-level combinational logic expression, which retains the computational logic of floating-point operations; compiling the converted HDL source code using an HDL compilation tool to generate a library file executable on a processor; calling function interfaces in the library file to perform floating-point operations in a prototype verification program running on the processor; and integrating a hardware floating-point IP core into the hardware system to implement floating-point operations, wherein the library file and the hardware floating-point IP core are based on the same HDL source code. Implementing this method can reduce the cost of ensuring consistency between the floating-point arithmetic algorithm verification prototype and hardware engineering.

The application discloses a batch control switching method based on dynamic recombination and decoupling, comprising the following steps: step 1, constructing an extensible control unit library, wherein the control unit library comprises a plurality of independent control modules formed by abstracting the functions of physical devices; step 2, in response to a new production task request, selecting corresponding control modules from the control unit library, and performing dynamic recombination to generate a unit combination logic matched with the production task; and step 3, providing a recipe parameter set separated from the unit combination logic. Through the implementation of the application, the modular dynamic recombination of the control logic is realized, the production line can be quickly adapted to a new production task within minutes, and the problems of low switching efficiency and poor flexibility caused by unit rigidity, process and recipe coupling and chain waiting in the traditional system are fundamentally solved, and the agility and overall equipment efficiency of batch production are significantly improved.

The application discloses a view processing method, system and device based on DSL, and a storage medium, and the method comprises the following steps: constructing a DSL query statement according to view configuration information input by a user, and executing the DSL query statement to query library table data and obtain a data query result; wherein the view configuration information comprises field filtering logic information and multi-field combination logic information; matching the data query result with a preselected view component to obtain a data dimension mapping relationship; rendering the preselected view component according to the data dimension mapping relationship, and displaying a view rendering result; the application supports a user in editing filtering logic by using a natural language, and a back end automatically analyzes a word meaning to translate a DSL query statement, so that a data query result is returned based on the DSL query statement, a visual page is automatically rendered, quick view rendering is realized, a developer does not need to participate, and front-end development is reduced.

Embodiments of the present disclosure include countermeasure circuit techniques for cyberattacks. In one embodiment, portions of combinational logic receive shared input bit groups and produce shared output bit groups. Shared output bit groups may be coupled between series configured combinational logic portions using control gates. Clock signals are delayed to activate the control gates after the outputs are stable. In some embodiments, a first combinational logic group and second combinational logic group operate on a clock and inverse clock.

The invention discloses a gated clock conversion method, device and system for realizing a double-edge clock selection circuit based on a frequency multiplication clock. The method comprises the following steps: acquiring design information of a to-be-converted circuit; generating a frequency multiplication clock signal based on the clock input signal; constructing a combinational logic circuit; constructing a clock enabling generation logic based on the frequency multiplication clock signal, the post comb, the pre comb, the gating signal and the edge selection signal; a clock input terminal of the timing device is connected to the frequency multiplication clock signal, and an output of the clock enable generation logic is connected to a clock enable terminal of the timing device. According to the invention, the output of the combinational logic driven by the frequency multiplication clock sampling frequency dividing circuit is utilized, so that the function of selecting the rising edge and the falling edge is realized on the clock enabling pin of the register, the clock tree on the register is very clean, the higher frequency on an FPGA (Field Programmable Gate Array) is realized, and the hold timing is easier to converge.

This application discloses a signal distortion processing method, apparatus, device, and medium, relating to the field of server design technology. Applied to complex programmable logic devices (CPLs), the method includes: debouncing and filtering a real-time acquired external signal to filter out instantaneous stray interference signals with a duration less than a filtering time threshold; performing multiple judgment processing on the debounced signal to be judged to generate multiple judgment results, including: constructing a purely digital delay circuit within the CPL for delayed judgment; repeatedly superimposing the signal to be judged onto the conditional statements of a state machine with a preset number of samplings to force the state machine to identify level signals and perform level signal superposition judgment; performing edge recognition judgment on the signal based on the global clock or frequency-divided sub-clock of the CPL; and performing combinational logic operations on the multiple judgment results to output a target valid signal. The technical solution of this application can improve the overall reliability of the server.

The application discloses a simulation result optimization method and application in chip verification and relates to the technical field of chip development.The method comprises the following steps: starting simulation on a to-be-tested chip to generate a simulation file;forming a signal line group by grabbing the signal lines of relevant signals in the simulation file based on a specified RTL layer;packing the signal values in the signal line group to form a data packet, extracting a key data packet from the data packet, comparing the values of the signal lines in the key data packet with expected values, and / or comparing the combined logic among the multiple signal lines in the key data packet with expected signal line combined logic;and generating a key data verification result text file according to the comparison result.The application realizes automatic analysis and checking of the simulation result of the required signal within a set range, improves the simulation result checking efficiency, and reduces the labor and computing resource cost of simulation debugging.

The application discloses a Verilog RTL code reinforcing method and related equipment, relates to the programming technical field, and mainly aims at solving the problem that there is no proper reinforcing method to make the circuit resist 0 and 1 error flip. The method comprises the following steps: obtaining a time sequence logic code section of an original Verilog RTL code file containing time sequence logic; performing format identification on the time sequence logic code section to generate a time sequence logic identification version code file; determining a flip-flop code in the code section with the format identification; and adding redundant combination logic voting circuit code to the flip-flop code to reinforce the original Verilog RTL code. The application is used in the Verilog RTL code reinforcing process.

This invention discloses a low-scan-power scanning unit and scanning chain, belonging to the field of integrated circuit design-for-test (DTBT). The invention uses a low-scan-power scanning unit, adding an OR gate to control the switching activity of two tri-state gates in the secondary latch unit during the scanning phase, and using a high-threshold PMOS as a power supply gating to control the power supply VDD of the two inverters inside the secondary latch unit, thus reducing the dynamic power consumption of the secondary latch and unnecessary dynamic power consumption of the combinational logic during the scanning phase. Additionally, a test vector output port P is added, whose signal originates from the output of the primary latch unit inside the scanning unit, reducing the transmission path delay during the scanning phase. This invention is applicable to the DTBT stage of digital circuits; by simply adding an OR gate and a high-threshold PMOS, without affecting the original logic circuit function, it achieves the goal of reducing dynamic power consumption during the shift phase.

A controller for a multi-level power converter that utilizes a look-up-table (LUT) in combination with a fast flash analog-to-digital converter (ADC) circuit to implement a complex set of control states for the multi-level power converter. Since the set of control states can be pre-processed, a LUT is very well suited for such selecting such control states. This technique can be fast because the delay is only the LUT access time, rather than the propagation delay through a complex network of combinational logic. The fast flash ADC has been designed to achieve all the following: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements for properly balancing fly capacitor voltages in a multi-level converter cell.

This application provides a DWA algorithm implementation circuit and an analog-to-digital converter. The DWA algorithm implementation circuit includes a shifter and a combinational logic circuit. The shifter's data input terminal receives thermometer codes output by a quantizer based on a first clock control signal; the shifter's data output terminal is connected to the input terminal of the combinational logic circuit and serves as the output terminal of the DWA algorithm implementation circuit; the combinational logic circuit concatenates the thermometer codes output by the shifter and performs combinational logic operations on the concatenated thermometer codes to generate a shift indication signal for the shifter; the shifter performs shift operations based on the shift indication signal. This application significantly simplifies the circuit structure, saves circuit area, and reduces circuit cost; simultaneously, it improves circuit speed and increases its flexibility.

The invention discloses an event processing method and related equipment, in the method, filtering can be executed based on an additional state except event message content, that is, filtering is executed based on a filtering rule of an additional condition, and specifically, the filtering efficiency is improved. The filtering distribution of the event messages can be realized by actively acquiring additional states (such as other states that the event source does not provide within the event messages, surrounding environment states irrelevant to the event source and the like) and based on filtering conditions of the additional states. Besides, AND and OR combinatorial logic of the conditions can be realized through combined arrangement of a plurality of additional conditions, so that a higher-order filtering mode is generated, an arrangement page can be provided, arrangement is performed in a dragging mode on the arrangement page, combinations of the additional conditions can be quickly generated, and usability is improved.

The invention relates to the field of chip verification, in particular to a strong connection circuit classification method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a strong connection circuit SCC comprising at least one closed loop, and obtaining an external input set P composed of external input signals of the SCC and a feedback set F composed of feedback signals; constructing a first Boolean formula G for describing the logic consistency of all combinational logic circuits in the SCC by taking elements in P and F as independent variable signals; when any signal value is taken by the external input signal in the P, and a group of feedback signals exist to enable G to be equal to 1 and have a solution, the SCC is determined to be a stable circuit; otherwise, determining that the SCC is an oscillating circuit; and the purpose of efficiently and accurately classifying the circuits is achieved.

This application discloses a method and system for preventing dragging of rail transit vehicle doors based on contact-type sensitive edge resistance detection. The method includes: acquiring train zero-speed signals, door closing and locking status signals, and isolation status signals; and using a controller to determine whether to activate sensitive edge detection based on the combined logic of the acquired signals. When sensitive edge detection is activated, the controller detects the resistance change of the sensitive edge, and converts the detected sensitive edge resistance signal into a voltage signal via a resistance sampling circuit inside the controller. The voltage value corresponding to the converted voltage signal is used as a decision variable. If the decision variable corresponding to the sensitive edge meets a first preset condition, it is determined that the sensitive edge has been triggered and an object is being clamped. The controller then controls the disconnection of the safety relay contacts to cut off the train traction circuit, and simultaneously triggers an alarm device to issue an audible and visual warning signal. This application can reliably identify and lock soft, thin objects clamped by the vehicle, eliminating the risk of dragging.

Method for modulating an n-phase current source converter, comprising the steps: a) obtaining duty ratio values, which are identified by using the following four sub-steps: i. obtaining initial duty ratio values, which are used to determine required output currents, from the ratio of AC output current reference values and a DC supply current value, ii. determining excess duty ratio values, which are used to compensate a missing duty ratio value, wherein the missing duty ratio value results from the subtraction between 1 and a sum of the initial upper or initial lower duty ratio values, wherein the sum of initial upper duty ratio values equals the sum of initial lower duty ratio values, iii. splitting the missing duty ratio value among converter legs that results in final duty ratio values and iv. obtaining cumulative sums of the initial or final duty ratio values, which are supplied to the comparator array as thresholds, b) comparing multiple thresholds through the comparison of the cumulative sums of the initial duty ratio values or final duty ratio values to a piecewise linear carrier signal, which results in n-1 digital signals obtained from n-1 comparators, wherein the comparing of multiple thresholds is performed by a first multiple threshold modulator for the upper switches and a second multiple threshold modulator for the lower switches, and c) processing of the digital signals from the multiple threshold comparator to obtain gating signals by using a digital combinatorial logic.

The invention relates to the technical field of power system automation, in particular to a power plant starting and standby transformer gateway metering voltage logic switching method and system, and the method comprises the steps: collecting a switching state signal and a disconnecting link position signal of gas insulated switchgear in a power grid of a power plant and an operation power signal of a generator set in real time through a data communication gateway machine; based on a preset self-generation self-use combinatorial logic rule, analyzing the collected signals, and judging whether the current operation state of the power plant is a self-generation self-use state or a self-generation non-self-use state; when the self-generating and self-using state is judged, a control instruction is output to a metering voltage loop contactor of the standby transformer starting equipment, a gateway meter voltage loop is disconnected, and voltage input of a gateway meter is cut off; when it is judged that the self-generation and self-use state is not achieved, a control instruction is output to close the contactor, a gateway meter voltage loop is closed, metering is recovered, and the problems of mistaken metering and metering omission of the electric quantity of the standby transformer under the working condition of parallel operation of multiple units are solved.

The invention provides a vehicle-mounted antenna automatic control method adaptive to various external antenna deployments. The vehicle-mounted antenna automatic control method comprises the following steps: reading pre-stored vehicle external antenna configuration parameters; detecting circuit level states of the first external antenna and the second external antenna, and identifying a current actual external antenna deployment mode and a working state of the external antenna; determining respective target setting states of the first single-pole double-throw switch, the second single-pole double-throw switch and the double-pole double-throw switch through preset antenna switching combinational logic, and generating corresponding switch switching instructions; sending the switch switching instruction to a corresponding switch, and controlling the switch to execute switching operation; and if the verification switching is successful, updating the pre-stored vehicle external antenna configuration parameters according to the currently effective antenna combination for initialization identification when the vehicle is powered on next time, so as to solve the problem that the existing antenna arrangement mode is not flexible, improve the flexibility of the antenna arrangement mode and reduce the cost.

The invention provides an induction cooker sound interaction method and system and an induction cooker, and relates to the technical field of intelligent household electrical appliances. According to the method, wireless communication connection between the induction cooker and a user terminal is established, so that a user can flexibly customize the sound type, melody or recording content of key prompt sound and alarm sound; corresponding relations between different cooking scenes and specific sounds are set, and after the configurations are stored as sound parameters, the sound output module can be driven to play corresponding audios when a trigger event is detected; according to the method, a current cooking scene can be automatically identified through combinational logic based on multi-dimensional heating parameters such as real-time power, power change rate, pot bottom temperature, temperature change rate, key pressing times or function switching frequency of a user within limited time and the like in the operation process of the induction cooker; and the sound configuration matched with the scene is intelligently called for playing, so that the sound interaction effect which is highly personalized and fits the actual cooking state is realized.

The invention discloses an automatic test method of a commodity display card and a related device, and relates to the field of automatic test, the automatic test process of the commodity display card in the application occurs in a configuration stage, and the test does not need to be performed after the commodity display card is released. Directly generating commodity display card simulation data according to configuration requirements by using the large model, and detecting whether abnormity exists or not; the large model can generate any commodity display card simulation data needing to be tested according to configuration requirements based on a basic database with configuration information including different business type data and all combinational logics of commodity display cards, and all possible combinational logics needing to be tested can be provided. And the coverage rate of the boundary and the combined scene is greatly improved.

Combinatorial logic circuits with feedback, which include at least two combinatorial logic elements, are disclosed. At least one of the combinatorial logic elements receives an external input (i.e., from outside the circuit), at least one of the combinatorial logic elements receives an input that is feedback of the circuit output, and at least one of the combinatorial logic elements receives an input that is neither an external input nor an output of the circuit but rather is from another of the combinatorial logic elements and thus only “implicit” to the circuit. No staticizers are needed; the logic circuits effectively create implicit equations to perform functions that were previously thought to require sequential logic. The combinatorial logic circuits result in a stable output (in some instances after a brief period of time) due to the implicit equations, rather than achieving stability from an explicit expression of some input to the circuit.

This invention discloses an accelerated method and apparatus for precise probabilistic simulation in combinatorial equivalence checking, relating to the fields of electronic design automation (EDA) and high-performance computing. The method includes: parsing the input circuit combinational logic netlist to form an EPS operator graph and corresponding data distribution configuration, transmitting this data to a GPU; starting the GPU to distribute the EPS operator graph to a processing unit array for EPS calculation based on the data distribution configuration using a data flow-driven approach; and collecting the running status information of each round of calculation and feeding it back to the CPU for dynamic optimization of the next round of calculation. This method can transform circuit calculation tasks into data flow-driven EPS operator graphs and execute them on the GPU, efficiently utilizing the GPU's massively parallel computing capabilities to overcome performance bottlenecks. The pipelined task advancement based on superblocks and the dynamic optimization mechanism based on performance reports can adapt to the computational characteristics of different circuit structures, balance the load, optimize resource allocation, and significantly shorten the verification cycle of combinatorial equivalence checking.

The application relates to the technical field of computing models, and discloses a continuous-time Ising model hardware solving system based on multi-chip interconnection, which comprises the following: an upper computer, which is used for carrying out cluster analysis and graph partitioning on a global weight matrix of an Ising model; a plurality of chips, which are used for realizing continuous-time updating of neuron states through combined logic; a data transceiving module, which is used for receiving and storing the weights of neurons related to the current chip from the upper computer; a system control module, which is used for controlling the loading of sub-weight matrix data, the iterative calculation of each logic accumulation unit and an activation function unit according to a scheduling table; an output interconnection structure, which is used for realizing the state transmission of neurons between chips and inside the chips; and an external communication module, which is used for transmitting sub-weight matrix data, neuron states and control instructions between the upper computer and the chips. The application can realize the solution of Max-Cut problems or Ising model problems of any scale.

The invention discloses a photon logic gate which comprises (1) electromagnetic waves; (2) lookup table electromagnetic waves which are used as carriers for transmitting data, data addresses and control signals of logic operation and are used for transmitting at least one of the data, the data addresses and the control signals; the carrier signal of the electromagnetic wave comprises at least one of millimeter wave, centimeter wave, sub-6GHz and optical fiber; carrier signals of electromagnetic waves are determined based on application scenarios of the electromagnetic waves, the lookup table is a table based on an internal memory (RAM), corresponding data or results can be quickly obtained through various corresponding truth tables in the lookup table, and an important function of the lookup table is to be used as a logic function generator and a logic function generator. Essentially, the logic function generator stores the content of a truth table, the truth table is obtained through a Boolean expression, the truth tables of various logic gates or combinational logic are filled into an internal memory RAM, and the internal memory RAM has the capability of performing operation according to the logic gates or combinational logic functions. Therefore, when a signal is input for logical operation, the operation that an address is input for table look-up, content corresponding to the address is found out and then output is carried out, and then complex logical operation is completed through repeated transmitting, receiving and processing. The method is a technology for processing information by using electromagnetic waves as a carrier, has the advantages of large bandwidth, low time delay, low power consumption and the like, and can exponentially improve the efficiency of logical operation.

The invention relates to the technical field of calculation models, and discloses a continuous time Isin model hardware solving system based on multi-chip interconnection, comprising an upper computer used for performing clustering analysis and graph division on a global weight matrix of an Isin model; the plurality of chips are used for realizing continuous time updating of neuron states through combinational logic; the data receiving and transmitting module is used for receiving and storing the weight of the neuron which comes from the upper computer and is related to the current chip; the system control module is used for controlling the loading of the sub-weight matrix data and the iterative calculation of each logic accumulation unit and the activation function unit according to the dispatch table; the output interconnection structure is used for realizing state transmission between chips and state transmission of neurons in the chips; and the external communication module is used for transmitting the sub-weight matrix data, the neuron state and the control instruction between the upper computer and each chip. According to the method, the solution of the Max-Cut problem or the Isin model problem of any scale can be realized.

This invention relates to a circuit for suppressing glitches on digital signals. The circuit includes a delay chain, an AND logic module, an OR logic module, and a latch. Input signals are connected to the input terminals of the delay chain, the AND logic module, and the OR logic module, respectively. Simultaneously, the output terminal of the delay chain is connected to the input terminals of the AND logic module and the OR logic module. The output terminal of the AND logic module is connected to one input terminal of the latch, and the output terminal of the OR logic module is connected to the other input terminal of the latch. The output terminal of the latch outputs a signal. This invention is based on combinational logic gates and latches, and can filter out high-level and low-level glitches on digital signals without a clock. It is particularly suitable for low-power scenarios where a clock is not required.